eos_s3/spi/
risr.rs

1#[doc = "Register `RISR` reader"]
2pub struct R(crate::R<RISR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RISR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RISR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RISR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `RISR` writer"]
17pub struct W(crate::W<RISR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RISR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RISR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RISR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TXEIS` reader - Transmit FIFO Empty Raw Interrupt Status"]
38pub struct TXEIS_R(crate::FieldReader<bool, bool>);
39impl TXEIS_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        TXEIS_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for TXEIS_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `TXEIS` writer - Transmit FIFO Empty Raw Interrupt Status"]
53pub struct TXEIS_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> TXEIS_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
71        self.w
72    }
73}
74#[doc = "Field `TXOIS` reader - Transmit FIFO Overflow Raw Interrupt Status"]
75pub struct TXOIS_R(crate::FieldReader<bool, bool>);
76impl TXOIS_R {
77    #[inline(always)]
78    pub(crate) fn new(bits: bool) -> Self {
79        TXOIS_R(crate::FieldReader::new(bits))
80    }
81}
82impl core::ops::Deref for TXOIS_R {
83    type Target = crate::FieldReader<bool, bool>;
84    #[inline(always)]
85    fn deref(&self) -> &Self::Target {
86        &self.0
87    }
88}
89#[doc = "Field `TXOIS` writer - Transmit FIFO Overflow Raw Interrupt Status"]
90pub struct TXOIS_W<'a> {
91    w: &'a mut W,
92}
93impl<'a> TXOIS_W<'a> {
94    #[doc = r"Sets the field bit"]
95    #[inline(always)]
96    pub fn set_bit(self) -> &'a mut W {
97        self.bit(true)
98    }
99    #[doc = r"Clears the field bit"]
100    #[inline(always)]
101    pub fn clear_bit(self) -> &'a mut W {
102        self.bit(false)
103    }
104    #[doc = r"Writes raw bits to the field"]
105    #[inline(always)]
106    pub fn bit(self, value: bool) -> &'a mut W {
107        self.w.bits =
108            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
109        self.w
110    }
111}
112#[doc = "Field `RXUIS` reader - Receive FIFO Underflow Raw Interrupt Status"]
113pub struct RXUIS_R(crate::FieldReader<bool, bool>);
114impl RXUIS_R {
115    #[inline(always)]
116    pub(crate) fn new(bits: bool) -> Self {
117        RXUIS_R(crate::FieldReader::new(bits))
118    }
119}
120impl core::ops::Deref for RXUIS_R {
121    type Target = crate::FieldReader<bool, bool>;
122    #[inline(always)]
123    fn deref(&self) -> &Self::Target {
124        &self.0
125    }
126}
127#[doc = "Field `RXUIS` writer - Receive FIFO Underflow Raw Interrupt Status"]
128pub struct RXUIS_W<'a> {
129    w: &'a mut W,
130}
131impl<'a> RXUIS_W<'a> {
132    #[doc = r"Sets the field bit"]
133    #[inline(always)]
134    pub fn set_bit(self) -> &'a mut W {
135        self.bit(true)
136    }
137    #[doc = r"Clears the field bit"]
138    #[inline(always)]
139    pub fn clear_bit(self) -> &'a mut W {
140        self.bit(false)
141    }
142    #[doc = r"Writes raw bits to the field"]
143    #[inline(always)]
144    pub fn bit(self, value: bool) -> &'a mut W {
145        self.w.bits =
146            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
147        self.w
148    }
149}
150#[doc = "Field `RXOIS` reader - Receive FIFO Overflow Raw Interrupt Status"]
151pub struct RXOIS_R(crate::FieldReader<bool, bool>);
152impl RXOIS_R {
153    #[inline(always)]
154    pub(crate) fn new(bits: bool) -> Self {
155        RXOIS_R(crate::FieldReader::new(bits))
156    }
157}
158impl core::ops::Deref for RXOIS_R {
159    type Target = crate::FieldReader<bool, bool>;
160    #[inline(always)]
161    fn deref(&self) -> &Self::Target {
162        &self.0
163    }
164}
165#[doc = "Field `RXOIS` writer - Receive FIFO Overflow Raw Interrupt Status"]
166pub struct RXOIS_W<'a> {
167    w: &'a mut W,
168}
169impl<'a> RXOIS_W<'a> {
170    #[doc = r"Sets the field bit"]
171    #[inline(always)]
172    pub fn set_bit(self) -> &'a mut W {
173        self.bit(true)
174    }
175    #[doc = r"Clears the field bit"]
176    #[inline(always)]
177    pub fn clear_bit(self) -> &'a mut W {
178        self.bit(false)
179    }
180    #[doc = r"Writes raw bits to the field"]
181    #[inline(always)]
182    pub fn bit(self, value: bool) -> &'a mut W {
183        self.w.bits =
184            (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
185        self.w
186    }
187}
188#[doc = "Field `RXFIS` reader - Receive FIFO Full Raw Interrupt Status"]
189pub struct RXFIS_R(crate::FieldReader<bool, bool>);
190impl RXFIS_R {
191    #[inline(always)]
192    pub(crate) fn new(bits: bool) -> Self {
193        RXFIS_R(crate::FieldReader::new(bits))
194    }
195}
196impl core::ops::Deref for RXFIS_R {
197    type Target = crate::FieldReader<bool, bool>;
198    #[inline(always)]
199    fn deref(&self) -> &Self::Target {
200        &self.0
201    }
202}
203#[doc = "Field `RXFIS` writer - Receive FIFO Full Raw Interrupt Status"]
204pub struct RXFIS_W<'a> {
205    w: &'a mut W,
206}
207impl<'a> RXFIS_W<'a> {
208    #[doc = r"Sets the field bit"]
209    #[inline(always)]
210    pub fn set_bit(self) -> &'a mut W {
211        self.bit(true)
212    }
213    #[doc = r"Clears the field bit"]
214    #[inline(always)]
215    pub fn clear_bit(self) -> &'a mut W {
216        self.bit(false)
217    }
218    #[doc = r"Writes raw bits to the field"]
219    #[inline(always)]
220    pub fn bit(self, value: bool) -> &'a mut W {
221        self.w.bits =
222            (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
223        self.w
224    }
225}
226#[doc = "Field `MSTIS` reader - Multi-Master Contention Raw Interrupt Status. This bit field is not present if the SPI Master is configured as a serial-slave device."]
227pub struct MSTIS_R(crate::FieldReader<bool, bool>);
228impl MSTIS_R {
229    #[inline(always)]
230    pub(crate) fn new(bits: bool) -> Self {
231        MSTIS_R(crate::FieldReader::new(bits))
232    }
233}
234impl core::ops::Deref for MSTIS_R {
235    type Target = crate::FieldReader<bool, bool>;
236    #[inline(always)]
237    fn deref(&self) -> &Self::Target {
238        &self.0
239    }
240}
241#[doc = "Field `MSTIS` writer - Multi-Master Contention Raw Interrupt Status. This bit field is not present if the SPI Master is configured as a serial-slave device."]
242pub struct MSTIS_W<'a> {
243    w: &'a mut W,
244}
245impl<'a> MSTIS_W<'a> {
246    #[doc = r"Sets the field bit"]
247    #[inline(always)]
248    pub fn set_bit(self) -> &'a mut W {
249        self.bit(true)
250    }
251    #[doc = r"Clears the field bit"]
252    #[inline(always)]
253    pub fn clear_bit(self) -> &'a mut W {
254        self.bit(false)
255    }
256    #[doc = r"Writes raw bits to the field"]
257    #[inline(always)]
258    pub fn bit(self, value: bool) -> &'a mut W {
259        self.w.bits =
260            (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
261        self.w
262    }
263}
264impl R {
265    #[doc = "Bit 0 - Transmit FIFO Empty Raw Interrupt Status"]
266    #[inline(always)]
267    pub fn txeis(&self) -> TXEIS_R {
268        TXEIS_R::new((self.bits & 0x01) != 0)
269    }
270    #[doc = "Bit 1 - Transmit FIFO Overflow Raw Interrupt Status"]
271    #[inline(always)]
272    pub fn txois(&self) -> TXOIS_R {
273        TXOIS_R::new(((self.bits >> 1) & 0x01) != 0)
274    }
275    #[doc = "Bit 2 - Receive FIFO Underflow Raw Interrupt Status"]
276    #[inline(always)]
277    pub fn rxuis(&self) -> RXUIS_R {
278        RXUIS_R::new(((self.bits >> 2) & 0x01) != 0)
279    }
280    #[doc = "Bit 3 - Receive FIFO Overflow Raw Interrupt Status"]
281    #[inline(always)]
282    pub fn rxois(&self) -> RXOIS_R {
283        RXOIS_R::new(((self.bits >> 3) & 0x01) != 0)
284    }
285    #[doc = "Bit 4 - Receive FIFO Full Raw Interrupt Status"]
286    #[inline(always)]
287    pub fn rxfis(&self) -> RXFIS_R {
288        RXFIS_R::new(((self.bits >> 4) & 0x01) != 0)
289    }
290    #[doc = "Bit 5 - Multi-Master Contention Raw Interrupt Status. This bit field is not present if the SPI Master is configured as a serial-slave device."]
291    #[inline(always)]
292    pub fn mstis(&self) -> MSTIS_R {
293        MSTIS_R::new(((self.bits >> 5) & 0x01) != 0)
294    }
295}
296impl W {
297    #[doc = "Bit 0 - Transmit FIFO Empty Raw Interrupt Status"]
298    #[inline(always)]
299    pub fn txeis(&mut self) -> TXEIS_W {
300        TXEIS_W { w: self }
301    }
302    #[doc = "Bit 1 - Transmit FIFO Overflow Raw Interrupt Status"]
303    #[inline(always)]
304    pub fn txois(&mut self) -> TXOIS_W {
305        TXOIS_W { w: self }
306    }
307    #[doc = "Bit 2 - Receive FIFO Underflow Raw Interrupt Status"]
308    #[inline(always)]
309    pub fn rxuis(&mut self) -> RXUIS_W {
310        RXUIS_W { w: self }
311    }
312    #[doc = "Bit 3 - Receive FIFO Overflow Raw Interrupt Status"]
313    #[inline(always)]
314    pub fn rxois(&mut self) -> RXOIS_W {
315        RXOIS_W { w: self }
316    }
317    #[doc = "Bit 4 - Receive FIFO Full Raw Interrupt Status"]
318    #[inline(always)]
319    pub fn rxfis(&mut self) -> RXFIS_W {
320        RXFIS_W { w: self }
321    }
322    #[doc = "Bit 5 - Multi-Master Contention Raw Interrupt Status. This bit field is not present if the SPI Master is configured as a serial-slave device."]
323    #[inline(always)]
324    pub fn mstis(&mut self) -> MSTIS_W {
325        MSTIS_W { w: self }
326    }
327    #[doc = "Writes raw bits to the register."]
328    #[inline(always)]
329    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
330        self.0.bits(bits);
331        self
332    }
333}
334#[doc = "Raw Interrupt Status Register: This read-only register reports the status of the SPI Master interrupts prior to masking.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [risr](index.html) module"]
335pub struct RISR_SPEC;
336impl crate::RegisterSpec for RISR_SPEC {
337    type Ux = u32;
338}
339#[doc = "`read()` method returns [risr::R](R) reader structure"]
340impl crate::Readable for RISR_SPEC {
341    type Reader = R;
342}
343#[doc = "`write(|w| ..)` method takes [risr::W](W) writer structure"]
344impl crate::Writable for RISR_SPEC {
345    type Writer = W;
346}
347#[doc = "`reset()` method sets RISR to value 0"]
348impl crate::Resettable for RISR_SPEC {
349    #[inline(always)]
350    fn reset_value() -> Self::Ux {
351        0
352    }
353}
eos_s3/spi/risr.rs

eos_s3/spi/
risr.rs
