use core::sync::atomic::{self, Ordering};
use cortex_m::{
interrupt,
peripheral::{scb::VectActive, SCB},
register::primask,
};
use rp2040_hal::sio::Sio;
#[no_mangle]
#[doc(hidden)]
#[allow(non_snake_case)]
pub fn _runtime_threadsafe_e0LtH0x3(code: &mut dyn FnMut()) {
critical_section::with(|_| code())
}
#[no_mangle]
#[doc(hidden)]
#[allow(non_snake_case)]
pub fn _runtime_interruptsafe_1l52Ge5e(code: &mut dyn FnMut()) {
let interrupts_active = primask::read().is_active();
interrupt::disable();
atomic::compiler_fence(Ordering::SeqCst);
code();
atomic::compiler_fence(Ordering::SeqCst);
if interrupts_active {
unsafe { interrupt::enable() };
}
}
#[no_mangle]
#[doc(hidden)]
#[allow(non_snake_case)]
pub fn _runtime_threadid_ZhZIZBv4() -> usize {
Sio::core() as usize
}
#[no_mangle]
#[doc(hidden)]
#[allow(non_snake_case)]
pub fn _runtime_isinterrupted_v5tnnoC7() -> bool {
SCB::vect_active() != VectActive::ThreadMode
}