mod bus_width;
mod card_mode;
mod card_type;
mod fifo_status;
mod reset;
pub mod command;
pub mod response;
pub mod tuning;
pub use bus_width::BusWidth;
pub use card_mode::CardMode;
pub use card_type::CardType;
pub use fifo_status::FifoStatus;
pub use reset::Reset;
use command::Command;
use response::Response;
use tuning::{TuningMode, TuningWidth};
pub trait Common {
type Error;
fn card_type(&self) -> CardType;
fn card_mode(&self) -> CardMode;
fn setup_bus(&mut self) -> Result<(), Self::Error>;
fn init(&mut self) -> Result<(), Self::Error>;
fn wait_for_reset(&mut self, reset: Reset, timeout: u64) -> Result<(), Self::Error>;
fn wait_while_busy(&mut self, timout_us: u64) -> Result<(), Self::Error>;
fn read_data(&mut self, data: &mut [u8]) -> Result<(), Self::Error>;
fn write_data(&mut self, data: &[u8]) -> Result<(), Self::Error>;
fn set_sample_phase(&mut self, sample_phase: u8);
fn fifo_ready(&self, fifo_status: FifoStatus) -> Result<(), Self::Error>;
fn send_tuning(&mut self, mode: TuningMode, width: TuningWidth) -> Result<(), Self::Error>;
fn interrupt(&self) -> u32;
fn set_interrupt(&mut self, int: u32);
fn clear_all_interrupt(&mut self);
fn response_interrupt(&self) -> u32;
fn set_response_interrupt(&mut self, int: u32);
fn clear_all_response_interrupt(&mut self);
}
pub trait Host: Common {
fn write_command<C: Command>(&mut self, cmd: &C) -> Result<(), Self::Error>;
fn read_response<C: Command, R: Response>(&mut self, cmd: &C) -> Result<R, Self::Error>;
}
pub trait Device: Common {
fn read_command<C: Command>(&mut self) -> Result<C, Self::Error>;
fn write_response<R: Response>(&mut self, response: &R) -> Result<(), Self::Error>;
}