embassy_stm32/
cpu.rs

1//! Multicore utilities.
2/// The enum values are identical to the bus master IDs / core Ids defined for each
3/// chip family (i.e. stm32h747 see rm0399 table 95)
4#[derive(Debug, PartialEq, Eq, Clone, Copy, Hash)]
5#[repr(u8)]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7pub enum CoreId {
8    #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
9    /// Cortex-M7, core 1.
10    Core0 = 0x3,
11
12    #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
13    /// Cortex-M4, core 2.
14    Core1 = 0x1,
15
16    #[cfg(not(any(stm32h745, stm32h747, stm32h755, stm32h757)))]
17    /// Cortex-M4, core 1
18    Core0 = 0x4,
19
20    #[cfg(any(stm32wb, stm32wl))]
21    /// Cortex-M0+, core 2.
22    Core1 = 0x8,
23}
24
25impl CoreId {
26    /// Get the current core id
27    /// This code assume that it is only executed on a Cortex-M M0+, M4 or M7 core.
28    pub fn current() -> Self {
29        let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() };
30        match (cpuid & 0x000000F0) >> 4 {
31            #[cfg(any(stm32wb, stm32wl))]
32            0x0 => CoreId::Core1,
33
34            #[cfg(not(any(stm32h745, stm32h747, stm32h755, stm32h757)))]
35            0x4 => CoreId::Core0,
36
37            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
38            0x4 => CoreId::Core1,
39
40            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
41            0x7 => CoreId::Core0,
42            _ => panic!("Unknown Cortex-M core"),
43        }
44    }
45
46    #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757, stm32wb, stm32wl))]
47    /// Get the other core id
48    pub const fn other(&self) -> Self {
49        match &self {
50            Self::Core0 => Self::Core1,
51            Self::Core1 => Self::Core0,
52        }
53    }
54
55    /// Translates the core ID to an index into the interrupt registers.
56    pub const fn to_index(&self) -> usize {
57        match &self {
58            CoreId::Core0 => 0,
59            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757, stm32wb, stm32wl))]
60            CoreId::Core1 => 1,
61        }
62    }
63}
embassy_stm32/cpu.rs

embassy_stm32/
cpu.rs
