Struct efr32x12p::ldma::RegisterBlock [−] [src]

#[repr(C)]

pub struct RegisterBlock {
    pub ctrl: CTRL,
    pub status: STATUS,
    pub sync: SYNC,
    pub chen: CHEN,
    pub chbusy: CHBUSY,
    pub chdone: CHDONE,
    pub dbghalt: DBGHALT,
    pub swreq: SWREQ,
    pub reqdis: REQDIS,
    pub reqpend: REQPEND,
    pub linkload: LINKLOAD,
    pub reqclear: REQCLEAR,
    pub if_: IF,
    pub ifs: IFS,
    pub ifc: IFC,
    pub ien: IEN,
    pub ch0_reqsel: CH0_REQSEL,
    pub ch0_cfg: CH0_CFG,
    pub ch0_loop: CH0_LOOP,
    pub ch0_ctrl: CH0_CTRL,
    pub ch0_src: CH0_SRC,
    pub ch0_dst: CH0_DST,
    pub ch0_link: CH0_LINK,
    pub ch1_reqsel: CH1_REQSEL,
    pub ch1_cfg: CH1_CFG,
    pub ch1_loop: CH1_LOOP,
    pub ch1_ctrl: CH1_CTRL,
    pub ch1_src: CH1_SRC,
    pub ch1_dst: CH1_DST,
    pub ch1_link: CH1_LINK,
    pub ch2_reqsel: CH2_REQSEL,
    pub ch2_cfg: CH2_CFG,
    pub ch2_loop: CH2_LOOP,
    pub ch2_ctrl: CH2_CTRL,
    pub ch2_src: CH2_SRC,
    pub ch2_dst: CH2_DST,
    pub ch2_link: CH2_LINK,
    pub ch3_reqsel: CH3_REQSEL,
    pub ch3_cfg: CH3_CFG,
    pub ch3_loop: CH3_LOOP,
    pub ch3_ctrl: CH3_CTRL,
    pub ch3_src: CH3_SRC,
    pub ch3_dst: CH3_DST,
    pub ch3_link: CH3_LINK,
    pub ch4_reqsel: CH4_REQSEL,
    pub ch4_cfg: CH4_CFG,
    pub ch4_loop: CH4_LOOP,
    pub ch4_ctrl: CH4_CTRL,
    pub ch4_src: CH4_SRC,
    pub ch4_dst: CH4_DST,
    pub ch4_link: CH4_LINK,
    pub ch5_reqsel: CH5_REQSEL,
    pub ch5_cfg: CH5_CFG,
    pub ch5_loop: CH5_LOOP,
    pub ch5_ctrl: CH5_CTRL,
    pub ch5_src: CH5_SRC,
    pub ch5_dst: CH5_DST,
    pub ch5_link: CH5_LINK,
    pub ch6_reqsel: CH6_REQSEL,
    pub ch6_cfg: CH6_CFG,
    pub ch6_loop: CH6_LOOP,
    pub ch6_ctrl: CH6_CTRL,
    pub ch6_src: CH6_SRC,
    pub ch6_dst: CH6_DST,
    pub ch6_link: CH6_LINK,
    pub ch7_reqsel: CH7_REQSEL,
    pub ch7_cfg: CH7_CFG,
    pub ch7_loop: CH7_LOOP,
    pub ch7_ctrl: CH7_CTRL,
    pub ch7_src: CH7_SRC,
    pub ch7_dst: CH7_DST,
    pub ch7_link: CH7_LINK,
    // some fields omitted
}

Register block

Fields

0x00 - DMA Control Register

0x04 - DMA Status Register

0x08 - DMA Synchronization Trigger Register (Single-Cycle RMW)

0x20 - DMA Channel Enable Register (Single-Cycle RMW)

0x24 - DMA Channel Busy Register

0x28 - DMA Channel Linking Done Register (Single-Cycle RMW)

0x2c - DMA Channel Debug Halt Register

0x30 - DMA Channel Software Transfer Request Register

0x34 - DMA Channel Request Disable Register

0x38 - DMA Channel Requests Pending Register

0x3c - DMA Channel Link Load Register

0x40 - DMA Channel Request Clear Register

0x60 - Interrupt Flag Register

0x64 - Interrupt Flag Set Register

0x68 - Interrupt Flag Clear Register

0x6c - Interrupt Enable register

0x80 - Channel Peripheral Request Select Register

0x84 - Channel Configuration Register

0x88 - Channel Loop Counter Register

0x8c - Channel Descriptor Control Word Register

0x90 - Channel Descriptor Source Data Address Register

0x94 - Channel Descriptor Destination Data Address Register

0x98 - Channel Descriptor Link Structure Address Register

0xb0 - Channel Peripheral Request Select Register

0xb4 - Channel Configuration Register

0xb8 - Channel Loop Counter Register

0xbc - Channel Descriptor Control Word Register

0xc0 - Channel Descriptor Source Data Address Register

0xc4 - Channel Descriptor Destination Data Address Register

0xc8 - Channel Descriptor Link Structure Address Register

0xe0 - Channel Peripheral Request Select Register

0xe4 - Channel Configuration Register

0xe8 - Channel Loop Counter Register

0xec - Channel Descriptor Control Word Register

0xf0 - Channel Descriptor Source Data Address Register

0xf4 - Channel Descriptor Destination Data Address Register

0xf8 - Channel Descriptor Link Structure Address Register

0x110 - Channel Peripheral Request Select Register

0x114 - Channel Configuration Register

0x118 - Channel Loop Counter Register

0x11c - Channel Descriptor Control Word Register

0x120 - Channel Descriptor Source Data Address Register

0x124 - Channel Descriptor Destination Data Address Register

0x128 - Channel Descriptor Link Structure Address Register

0x140 - Channel Peripheral Request Select Register

0x144 - Channel Configuration Register

0x148 - Channel Loop Counter Register

0x14c - Channel Descriptor Control Word Register

0x150 - Channel Descriptor Source Data Address Register

0x154 - Channel Descriptor Destination Data Address Register

0x158 - Channel Descriptor Link Structure Address Register

0x170 - Channel Peripheral Request Select Register

0x174 - Channel Configuration Register

0x178 - Channel Loop Counter Register

0x17c - Channel Descriptor Control Word Register

0x180 - Channel Descriptor Source Data Address Register

0x184 - Channel Descriptor Destination Data Address Register

0x188 - Channel Descriptor Link Structure Address Register

0x1a0 - Channel Peripheral Request Select Register

0x1a4 - Channel Configuration Register

0x1a8 - Channel Loop Counter Register

0x1ac - Channel Descriptor Control Word Register

0x1b0 - Channel Descriptor Source Data Address Register

0x1b4 - Channel Descriptor Destination Data Address Register

0x1b8 - Channel Descriptor Link Structure Address Register

0x1d0 - Channel Peripheral Request Select Register

0x1d4 - Channel Configuration Register

0x1d8 - Channel Loop Counter Register

0x1dc - Channel Descriptor Control Word Register

0x1e0 - Channel Descriptor Source Data Address Register

0x1e4 - Channel Descriptor Destination Data Address Register

0x1e8 - Channel Descriptor Link Structure Address Register