Module efr32x12p::ldma
[−]
[src]
LDMA
Modules
ch0_cfg |
Channel Configuration Register |
ch0_ctrl |
Channel Descriptor Control Word Register |
ch0_dst |
Channel Descriptor Destination Data Address Register |
ch0_link |
Channel Descriptor Link Structure Address Register |
ch0_loop |
Channel Loop Counter Register |
ch0_reqsel |
Channel Peripheral Request Select Register |
ch0_src |
Channel Descriptor Source Data Address Register |
ch1_cfg |
Channel Configuration Register |
ch1_ctrl |
Channel Descriptor Control Word Register |
ch1_dst |
Channel Descriptor Destination Data Address Register |
ch1_link |
Channel Descriptor Link Structure Address Register |
ch1_loop |
Channel Loop Counter Register |
ch1_reqsel |
Channel Peripheral Request Select Register |
ch1_src |
Channel Descriptor Source Data Address Register |
ch2_cfg |
Channel Configuration Register |
ch2_ctrl |
Channel Descriptor Control Word Register |
ch2_dst |
Channel Descriptor Destination Data Address Register |
ch2_link |
Channel Descriptor Link Structure Address Register |
ch2_loop |
Channel Loop Counter Register |
ch2_reqsel |
Channel Peripheral Request Select Register |
ch2_src |
Channel Descriptor Source Data Address Register |
ch3_cfg |
Channel Configuration Register |
ch3_ctrl |
Channel Descriptor Control Word Register |
ch3_dst |
Channel Descriptor Destination Data Address Register |
ch3_link |
Channel Descriptor Link Structure Address Register |
ch3_loop |
Channel Loop Counter Register |
ch3_reqsel |
Channel Peripheral Request Select Register |
ch3_src |
Channel Descriptor Source Data Address Register |
ch4_cfg |
Channel Configuration Register |
ch4_ctrl |
Channel Descriptor Control Word Register |
ch4_dst |
Channel Descriptor Destination Data Address Register |
ch4_link |
Channel Descriptor Link Structure Address Register |
ch4_loop |
Channel Loop Counter Register |
ch4_reqsel |
Channel Peripheral Request Select Register |
ch4_src |
Channel Descriptor Source Data Address Register |
ch5_cfg |
Channel Configuration Register |
ch5_ctrl |
Channel Descriptor Control Word Register |
ch5_dst |
Channel Descriptor Destination Data Address Register |
ch5_link |
Channel Descriptor Link Structure Address Register |
ch5_loop |
Channel Loop Counter Register |
ch5_reqsel |
Channel Peripheral Request Select Register |
ch5_src |
Channel Descriptor Source Data Address Register |
ch6_cfg |
Channel Configuration Register |
ch6_ctrl |
Channel Descriptor Control Word Register |
ch6_dst |
Channel Descriptor Destination Data Address Register |
ch6_link |
Channel Descriptor Link Structure Address Register |
ch6_loop |
Channel Loop Counter Register |
ch6_reqsel |
Channel Peripheral Request Select Register |
ch6_src |
Channel Descriptor Source Data Address Register |
ch7_cfg |
Channel Configuration Register |
ch7_ctrl |
Channel Descriptor Control Word Register |
ch7_dst |
Channel Descriptor Destination Data Address Register |
ch7_link |
Channel Descriptor Link Structure Address Register |
ch7_loop |
Channel Loop Counter Register |
ch7_reqsel |
Channel Peripheral Request Select Register |
ch7_src |
Channel Descriptor Source Data Address Register |
chbusy |
DMA Channel Busy Register |
chdone |
DMA Channel Linking Done Register (Single-Cycle RMW) |
chen |
DMA Channel Enable Register (Single-Cycle RMW) |
ctrl |
DMA Control Register |
dbghalt |
DMA Channel Debug Halt Register |
ien |
Interrupt Enable register |
if_ |
Interrupt Flag Register |
ifc |
Interrupt Flag Clear Register |
ifs |
Interrupt Flag Set Register |
linkload |
DMA Channel Link Load Register |
reqclear |
DMA Channel Request Clear Register |
reqdis |
DMA Channel Request Disable Register |
reqpend |
DMA Channel Requests Pending Register |
status |
DMA Status Register |
swreq |
DMA Channel Software Transfer Request Register |
sync |
DMA Synchronization Trigger Register (Single-Cycle RMW) |
Structs
CH0_CFG |
Channel Configuration Register |
CH0_CTRL |
Channel Descriptor Control Word Register |
CH0_DST |
Channel Descriptor Destination Data Address Register |
CH0_LINK |
Channel Descriptor Link Structure Address Register |
CH0_LOOP |
Channel Loop Counter Register |
CH0_REQSEL |
Channel Peripheral Request Select Register |
CH0_SRC |
Channel Descriptor Source Data Address Register |
CH1_CFG |
Channel Configuration Register |
CH1_CTRL |
Channel Descriptor Control Word Register |
CH1_DST |
Channel Descriptor Destination Data Address Register |
CH1_LINK |
Channel Descriptor Link Structure Address Register |
CH1_LOOP |
Channel Loop Counter Register |
CH1_REQSEL |
Channel Peripheral Request Select Register |
CH1_SRC |
Channel Descriptor Source Data Address Register |
CH2_CFG |
Channel Configuration Register |
CH2_CTRL |
Channel Descriptor Control Word Register |
CH2_DST |
Channel Descriptor Destination Data Address Register |
CH2_LINK |
Channel Descriptor Link Structure Address Register |
CH2_LOOP |
Channel Loop Counter Register |
CH2_REQSEL |
Channel Peripheral Request Select Register |
CH2_SRC |
Channel Descriptor Source Data Address Register |
CH3_CFG |
Channel Configuration Register |
CH3_CTRL |
Channel Descriptor Control Word Register |
CH3_DST |
Channel Descriptor Destination Data Address Register |
CH3_LINK |
Channel Descriptor Link Structure Address Register |
CH3_LOOP |
Channel Loop Counter Register |
CH3_REQSEL |
Channel Peripheral Request Select Register |
CH3_SRC |
Channel Descriptor Source Data Address Register |
CH4_CFG |
Channel Configuration Register |
CH4_CTRL |
Channel Descriptor Control Word Register |
CH4_DST |
Channel Descriptor Destination Data Address Register |
CH4_LINK |
Channel Descriptor Link Structure Address Register |
CH4_LOOP |
Channel Loop Counter Register |
CH4_REQSEL |
Channel Peripheral Request Select Register |
CH4_SRC |
Channel Descriptor Source Data Address Register |
CH5_CFG |
Channel Configuration Register |
CH5_CTRL |
Channel Descriptor Control Word Register |
CH5_DST |
Channel Descriptor Destination Data Address Register |
CH5_LINK |
Channel Descriptor Link Structure Address Register |
CH5_LOOP |
Channel Loop Counter Register |
CH5_REQSEL |
Channel Peripheral Request Select Register |
CH5_SRC |
Channel Descriptor Source Data Address Register |
CH6_CFG |
Channel Configuration Register |
CH6_CTRL |
Channel Descriptor Control Word Register |
CH6_DST |
Channel Descriptor Destination Data Address Register |
CH6_LINK |
Channel Descriptor Link Structure Address Register |
CH6_LOOP |
Channel Loop Counter Register |
CH6_REQSEL |
Channel Peripheral Request Select Register |
CH6_SRC |
Channel Descriptor Source Data Address Register |
CH7_CFG |
Channel Configuration Register |
CH7_CTRL |
Channel Descriptor Control Word Register |
CH7_DST |
Channel Descriptor Destination Data Address Register |
CH7_LINK |
Channel Descriptor Link Structure Address Register |
CH7_LOOP |
Channel Loop Counter Register |
CH7_REQSEL |
Channel Peripheral Request Select Register |
CH7_SRC |
Channel Descriptor Source Data Address Register |
CHBUSY |
DMA Channel Busy Register |
CHDONE |
DMA Channel Linking Done Register (Single-Cycle RMW) |
CHEN |
DMA Channel Enable Register (Single-Cycle RMW) |
CTRL |
DMA Control Register |
DBGHALT |
DMA Channel Debug Halt Register |
IEN |
Interrupt Enable register |
IF |
Interrupt Flag Register |
IFC |
Interrupt Flag Clear Register |
IFS |
Interrupt Flag Set Register |
LINKLOAD |
DMA Channel Link Load Register |
REQCLEAR |
DMA Channel Request Clear Register |
REQDIS |
DMA Channel Request Disable Register |
REQPEND |
DMA Channel Requests Pending Register |
RegisterBlock |
Register block |
STATUS |
DMA Status Register |
SWREQ |
DMA Channel Software Transfer Request Register |
SYNC |
DMA Synchronization Trigger Register (Single-Cycle RMW) |