1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - System Control Register"]
5 pub ctrl: crate::Reg<ctrl::CTRL_SPEC>,
6 #[doc = "0x04 - System Status Register"]
7 pub status: crate::Reg<status::STATUS_SPEC>,
8 #[doc = "0x08 - Interrupt Flag Register"]
9 pub if_: crate::Reg<if_::IF_SPEC>,
10 #[doc = "0x0c - Interrupt Flag Set Register"]
11 pub ifs: crate::Reg<ifs::IFS_SPEC>,
12 #[doc = "0x10 - Interrupt Flag Clear Register"]
13 pub ifc: crate::Reg<ifc::IFC_SPEC>,
14 #[doc = "0x14 - Interrupt Enable Register"]
15 pub ien: crate::Reg<ien::IEN_SPEC>,
16 #[doc = "0x18 - I/O Routing Register"]
17 pub route: crate::Reg<route::ROUTE_SPEC>,
18 _reserved7: [u8; 0x0003_bfe4],
19 #[doc = "0x3c000 - OTG Control and Status Register"]
20 pub gotgctl: crate::Reg<gotgctl::GOTGCTL_SPEC>,
21 #[doc = "0x3c004 - OTG Interrupt Register"]
22 pub gotgint: crate::Reg<gotgint::GOTGINT_SPEC>,
23 #[doc = "0x3c008 - AHB Configuration Register"]
24 pub gahbcfg: crate::Reg<gahbcfg::GAHBCFG_SPEC>,
25 #[doc = "0x3c00c - USB Configuration Register"]
26 pub gusbcfg: crate::Reg<gusbcfg::GUSBCFG_SPEC>,
27 #[doc = "0x3c010 - Reset Register"]
28 pub grstctl: crate::Reg<grstctl::GRSTCTL_SPEC>,
29 #[doc = "0x3c014 - Interrupt Register"]
30 pub gintsts: crate::Reg<gintsts::GINTSTS_SPEC>,
31 #[doc = "0x3c018 - Interrupt Mask Register"]
32 pub gintmsk: crate::Reg<gintmsk::GINTMSK_SPEC>,
33 #[doc = "0x3c01c - Receive Status Debug Read Register"]
34 pub grxstsr: crate::Reg<grxstsr::GRXSTSR_SPEC>,
35 #[doc = "0x3c020 - Receive Status Read and Pop Register"]
36 pub grxstsp: crate::Reg<grxstsp::GRXSTSP_SPEC>,
37 #[doc = "0x3c024 - Receive FIFO Size Register"]
38 pub grxfsiz: crate::Reg<grxfsiz::GRXFSIZ_SPEC>,
39 #[doc = "0x3c028 - Non-periodic Transmit FIFO Size Register"]
40 pub gnptxfsiz: crate::Reg<gnptxfsiz::GNPTXFSIZ_SPEC>,
41 #[doc = "0x3c02c - Non-periodic Transmit FIFO/Queue Status Register"]
42 pub gnptxsts: crate::Reg<gnptxsts::GNPTXSTS_SPEC>,
43 _reserved19: [u8; 0x2c],
44 #[doc = "0x3c05c - Global DFIFO Configuration Register"]
45 pub gdfifocfg: crate::Reg<gdfifocfg::GDFIFOCFG_SPEC>,
46 _reserved20: [u8; 0xa0],
47 #[doc = "0x3c100 - Host Periodic Transmit FIFO Size Register"]
48 pub hptxfsiz: crate::Reg<hptxfsiz::HPTXFSIZ_SPEC>,
49 #[doc = "0x3c104 - Device IN Endpoint Transmit FIFO 1 Size Register"]
50 pub dieptxf1: crate::Reg<dieptxf1::DIEPTXF1_SPEC>,
51 #[doc = "0x3c108 - Device IN Endpoint Transmit FIFO 2 Size Register"]
52 pub dieptxf2: crate::Reg<dieptxf2::DIEPTXF2_SPEC>,
53 #[doc = "0x3c10c - Device IN Endpoint Transmit FIFO 3 Size Register"]
54 pub dieptxf3: crate::Reg<dieptxf3::DIEPTXF3_SPEC>,
55 #[doc = "0x3c110 - Device IN Endpoint Transmit FIFO 4 Size Register"]
56 pub dieptxf4: crate::Reg<dieptxf4::DIEPTXF4_SPEC>,
57 #[doc = "0x3c114 - Device IN Endpoint Transmit FIFO 5 Size Register"]
58 pub dieptxf5: crate::Reg<dieptxf5::DIEPTXF5_SPEC>,
59 #[doc = "0x3c118 - Device IN Endpoint Transmit FIFO 6 Size Register"]
60 pub dieptxf6: crate::Reg<dieptxf6::DIEPTXF6_SPEC>,
61 _reserved27: [u8; 0x02e4],
62 #[doc = "0x3c400 - Host Configuration Register"]
63 pub hcfg: crate::Reg<hcfg::HCFG_SPEC>,
64 #[doc = "0x3c404 - Host Frame Interval Register"]
65 pub hfir: crate::Reg<hfir::HFIR_SPEC>,
66 #[doc = "0x3c408 - Host Frame Number/Frame Time Remaining Register"]
67 pub hfnum: crate::Reg<hfnum::HFNUM_SPEC>,
68 _reserved30: [u8; 0x04],
69 #[doc = "0x3c410 - Host Periodic Transmit FIFO/Queue Status Register"]
70 pub hptxsts: crate::Reg<hptxsts::HPTXSTS_SPEC>,
71 #[doc = "0x3c414 - Host All Channels Interrupt Register"]
72 pub haint: crate::Reg<haint::HAINT_SPEC>,
73 #[doc = "0x3c418 - Host All Channels Interrupt Mask Register"]
74 pub haintmsk: crate::Reg<haintmsk::HAINTMSK_SPEC>,
75 _reserved33: [u8; 0x24],
76 #[doc = "0x3c440 - Host Port Control and Status Register"]
77 pub hprt: crate::Reg<hprt::HPRT_SPEC>,
78 _reserved34: [u8; 0xbc],
79 #[doc = "0x3c500 - Host Channel x Characteristics Register"]
80 pub hc0_char: crate::Reg<hc0_char::HC0_CHAR_SPEC>,
81 _reserved35: [u8; 0x04],
82 #[doc = "0x3c508 - Host Channel x Interrupt Register"]
83 pub hc0_int: crate::Reg<hc0_int::HC0_INT_SPEC>,
84 #[doc = "0x3c50c - Host Channel x Interrupt Mask Register"]
85 pub hc0_intmsk: crate::Reg<hc0_intmsk::HC0_INTMSK_SPEC>,
86 #[doc = "0x3c510 - Host Channel x Transfer Size Register"]
87 pub hc0_tsiz: crate::Reg<hc0_tsiz::HC0_TSIZ_SPEC>,
88 #[doc = "0x3c514 - Host Channel x DMA Address Register"]
89 pub hc0_dmaaddr: crate::Reg<hc0_dmaaddr::HC0_DMAADDR_SPEC>,
90 _reserved39: [u8; 0x08],
91 #[doc = "0x3c520 - Host Channel x Characteristics Register"]
92 pub hc1_char: crate::Reg<hc1_char::HC1_CHAR_SPEC>,
93 _reserved40: [u8; 0x04],
94 #[doc = "0x3c528 - Host Channel x Interrupt Register"]
95 pub hc1_int: crate::Reg<hc1_int::HC1_INT_SPEC>,
96 #[doc = "0x3c52c - Host Channel x Interrupt Mask Register"]
97 pub hc1_intmsk: crate::Reg<hc1_intmsk::HC1_INTMSK_SPEC>,
98 #[doc = "0x3c530 - Host Channel x Transfer Size Register"]
99 pub hc1_tsiz: crate::Reg<hc1_tsiz::HC1_TSIZ_SPEC>,
100 #[doc = "0x3c534 - Host Channel x DMA Address Register"]
101 pub hc1_dmaaddr: crate::Reg<hc1_dmaaddr::HC1_DMAADDR_SPEC>,
102 _reserved44: [u8; 0x08],
103 #[doc = "0x3c540 - Host Channel x Characteristics Register"]
104 pub hc2_char: crate::Reg<hc2_char::HC2_CHAR_SPEC>,
105 _reserved45: [u8; 0x04],
106 #[doc = "0x3c548 - Host Channel x Interrupt Register"]
107 pub hc2_int: crate::Reg<hc2_int::HC2_INT_SPEC>,
108 #[doc = "0x3c54c - Host Channel x Interrupt Mask Register"]
109 pub hc2_intmsk: crate::Reg<hc2_intmsk::HC2_INTMSK_SPEC>,
110 #[doc = "0x3c550 - Host Channel x Transfer Size Register"]
111 pub hc2_tsiz: crate::Reg<hc2_tsiz::HC2_TSIZ_SPEC>,
112 #[doc = "0x3c554 - Host Channel x DMA Address Register"]
113 pub hc2_dmaaddr: crate::Reg<hc2_dmaaddr::HC2_DMAADDR_SPEC>,
114 _reserved49: [u8; 0x08],
115 #[doc = "0x3c560 - Host Channel x Characteristics Register"]
116 pub hc3_char: crate::Reg<hc3_char::HC3_CHAR_SPEC>,
117 _reserved50: [u8; 0x04],
118 #[doc = "0x3c568 - Host Channel x Interrupt Register"]
119 pub hc3_int: crate::Reg<hc3_int::HC3_INT_SPEC>,
120 #[doc = "0x3c56c - Host Channel x Interrupt Mask Register"]
121 pub hc3_intmsk: crate::Reg<hc3_intmsk::HC3_INTMSK_SPEC>,
122 #[doc = "0x3c570 - Host Channel x Transfer Size Register"]
123 pub hc3_tsiz: crate::Reg<hc3_tsiz::HC3_TSIZ_SPEC>,
124 #[doc = "0x3c574 - Host Channel x DMA Address Register"]
125 pub hc3_dmaaddr: crate::Reg<hc3_dmaaddr::HC3_DMAADDR_SPEC>,
126 _reserved54: [u8; 0x08],
127 #[doc = "0x3c580 - Host Channel x Characteristics Register"]
128 pub hc4_char: crate::Reg<hc4_char::HC4_CHAR_SPEC>,
129 _reserved55: [u8; 0x04],
130 #[doc = "0x3c588 - Host Channel x Interrupt Register"]
131 pub hc4_int: crate::Reg<hc4_int::HC4_INT_SPEC>,
132 #[doc = "0x3c58c - Host Channel x Interrupt Mask Register"]
133 pub hc4_intmsk: crate::Reg<hc4_intmsk::HC4_INTMSK_SPEC>,
134 #[doc = "0x3c590 - Host Channel x Transfer Size Register"]
135 pub hc4_tsiz: crate::Reg<hc4_tsiz::HC4_TSIZ_SPEC>,
136 #[doc = "0x3c594 - Host Channel x DMA Address Register"]
137 pub hc4_dmaaddr: crate::Reg<hc4_dmaaddr::HC4_DMAADDR_SPEC>,
138 _reserved59: [u8; 0x08],
139 #[doc = "0x3c5a0 - Host Channel x Characteristics Register"]
140 pub hc5_char: crate::Reg<hc5_char::HC5_CHAR_SPEC>,
141 _reserved60: [u8; 0x04],
142 #[doc = "0x3c5a8 - Host Channel x Interrupt Register"]
143 pub hc5_int: crate::Reg<hc5_int::HC5_INT_SPEC>,
144 #[doc = "0x3c5ac - Host Channel x Interrupt Mask Register"]
145 pub hc5_intmsk: crate::Reg<hc5_intmsk::HC5_INTMSK_SPEC>,
146 #[doc = "0x3c5b0 - Host Channel x Transfer Size Register"]
147 pub hc5_tsiz: crate::Reg<hc5_tsiz::HC5_TSIZ_SPEC>,
148 #[doc = "0x3c5b4 - Host Channel x DMA Address Register"]
149 pub hc5_dmaaddr: crate::Reg<hc5_dmaaddr::HC5_DMAADDR_SPEC>,
150 _reserved64: [u8; 0x08],
151 #[doc = "0x3c5c0 - Host Channel x Characteristics Register"]
152 pub hc6_char: crate::Reg<hc6_char::HC6_CHAR_SPEC>,
153 _reserved65: [u8; 0x04],
154 #[doc = "0x3c5c8 - Host Channel x Interrupt Register"]
155 pub hc6_int: crate::Reg<hc6_int::HC6_INT_SPEC>,
156 #[doc = "0x3c5cc - Host Channel x Interrupt Mask Register"]
157 pub hc6_intmsk: crate::Reg<hc6_intmsk::HC6_INTMSK_SPEC>,
158 #[doc = "0x3c5d0 - Host Channel x Transfer Size Register"]
159 pub hc6_tsiz: crate::Reg<hc6_tsiz::HC6_TSIZ_SPEC>,
160 #[doc = "0x3c5d4 - Host Channel x DMA Address Register"]
161 pub hc6_dmaaddr: crate::Reg<hc6_dmaaddr::HC6_DMAADDR_SPEC>,
162 _reserved69: [u8; 0x08],
163 #[doc = "0x3c5e0 - Host Channel x Characteristics Register"]
164 pub hc7_char: crate::Reg<hc7_char::HC7_CHAR_SPEC>,
165 _reserved70: [u8; 0x04],
166 #[doc = "0x3c5e8 - Host Channel x Interrupt Register"]
167 pub hc7_int: crate::Reg<hc7_int::HC7_INT_SPEC>,
168 #[doc = "0x3c5ec - Host Channel x Interrupt Mask Register"]
169 pub hc7_intmsk: crate::Reg<hc7_intmsk::HC7_INTMSK_SPEC>,
170 #[doc = "0x3c5f0 - Host Channel x Transfer Size Register"]
171 pub hc7_tsiz: crate::Reg<hc7_tsiz::HC7_TSIZ_SPEC>,
172 #[doc = "0x3c5f4 - Host Channel x DMA Address Register"]
173 pub hc7_dmaaddr: crate::Reg<hc7_dmaaddr::HC7_DMAADDR_SPEC>,
174 _reserved74: [u8; 0x08],
175 #[doc = "0x3c600 - Host Channel x Characteristics Register"]
176 pub hc8_char: crate::Reg<hc8_char::HC8_CHAR_SPEC>,
177 _reserved75: [u8; 0x04],
178 #[doc = "0x3c608 - Host Channel x Interrupt Register"]
179 pub hc8_int: crate::Reg<hc8_int::HC8_INT_SPEC>,
180 #[doc = "0x3c60c - Host Channel x Interrupt Mask Register"]
181 pub hc8_intmsk: crate::Reg<hc8_intmsk::HC8_INTMSK_SPEC>,
182 #[doc = "0x3c610 - Host Channel x Transfer Size Register"]
183 pub hc8_tsiz: crate::Reg<hc8_tsiz::HC8_TSIZ_SPEC>,
184 #[doc = "0x3c614 - Host Channel x DMA Address Register"]
185 pub hc8_dmaaddr: crate::Reg<hc8_dmaaddr::HC8_DMAADDR_SPEC>,
186 _reserved79: [u8; 0x08],
187 #[doc = "0x3c620 - Host Channel x Characteristics Register"]
188 pub hc9_char: crate::Reg<hc9_char::HC9_CHAR_SPEC>,
189 _reserved80: [u8; 0x04],
190 #[doc = "0x3c628 - Host Channel x Interrupt Register"]
191 pub hc9_int: crate::Reg<hc9_int::HC9_INT_SPEC>,
192 #[doc = "0x3c62c - Host Channel x Interrupt Mask Register"]
193 pub hc9_intmsk: crate::Reg<hc9_intmsk::HC9_INTMSK_SPEC>,
194 #[doc = "0x3c630 - Host Channel x Transfer Size Register"]
195 pub hc9_tsiz: crate::Reg<hc9_tsiz::HC9_TSIZ_SPEC>,
196 #[doc = "0x3c634 - Host Channel x DMA Address Register"]
197 pub hc9_dmaaddr: crate::Reg<hc9_dmaaddr::HC9_DMAADDR_SPEC>,
198 _reserved84: [u8; 0x08],
199 #[doc = "0x3c640 - Host Channel x Characteristics Register"]
200 pub hc10_char: crate::Reg<hc10_char::HC10_CHAR_SPEC>,
201 _reserved85: [u8; 0x04],
202 #[doc = "0x3c648 - Host Channel x Interrupt Register"]
203 pub hc10_int: crate::Reg<hc10_int::HC10_INT_SPEC>,
204 #[doc = "0x3c64c - Host Channel x Interrupt Mask Register"]
205 pub hc10_intmsk: crate::Reg<hc10_intmsk::HC10_INTMSK_SPEC>,
206 #[doc = "0x3c650 - Host Channel x Transfer Size Register"]
207 pub hc10_tsiz: crate::Reg<hc10_tsiz::HC10_TSIZ_SPEC>,
208 #[doc = "0x3c654 - Host Channel x DMA Address Register"]
209 pub hc10_dmaaddr: crate::Reg<hc10_dmaaddr::HC10_DMAADDR_SPEC>,
210 _reserved89: [u8; 0x08],
211 #[doc = "0x3c660 - Host Channel x Characteristics Register"]
212 pub hc11_char: crate::Reg<hc11_char::HC11_CHAR_SPEC>,
213 _reserved90: [u8; 0x04],
214 #[doc = "0x3c668 - Host Channel x Interrupt Register"]
215 pub hc11_int: crate::Reg<hc11_int::HC11_INT_SPEC>,
216 #[doc = "0x3c66c - Host Channel x Interrupt Mask Register"]
217 pub hc11_intmsk: crate::Reg<hc11_intmsk::HC11_INTMSK_SPEC>,
218 #[doc = "0x3c670 - Host Channel x Transfer Size Register"]
219 pub hc11_tsiz: crate::Reg<hc11_tsiz::HC11_TSIZ_SPEC>,
220 #[doc = "0x3c674 - Host Channel x DMA Address Register"]
221 pub hc11_dmaaddr: crate::Reg<hc11_dmaaddr::HC11_DMAADDR_SPEC>,
222 _reserved94: [u8; 0x08],
223 #[doc = "0x3c680 - Host Channel x Characteristics Register"]
224 pub hc12_char: crate::Reg<hc12_char::HC12_CHAR_SPEC>,
225 _reserved95: [u8; 0x04],
226 #[doc = "0x3c688 - Host Channel x Interrupt Register"]
227 pub hc12_int: crate::Reg<hc12_int::HC12_INT_SPEC>,
228 #[doc = "0x3c68c - Host Channel x Interrupt Mask Register"]
229 pub hc12_intmsk: crate::Reg<hc12_intmsk::HC12_INTMSK_SPEC>,
230 #[doc = "0x3c690 - Host Channel x Transfer Size Register"]
231 pub hc12_tsiz: crate::Reg<hc12_tsiz::HC12_TSIZ_SPEC>,
232 #[doc = "0x3c694 - Host Channel x DMA Address Register"]
233 pub hc12_dmaaddr: crate::Reg<hc12_dmaaddr::HC12_DMAADDR_SPEC>,
234 _reserved99: [u8; 0x08],
235 #[doc = "0x3c6a0 - Host Channel x Characteristics Register"]
236 pub hc13_char: crate::Reg<hc13_char::HC13_CHAR_SPEC>,
237 _reserved100: [u8; 0x04],
238 #[doc = "0x3c6a8 - Host Channel x Interrupt Register"]
239 pub hc13_int: crate::Reg<hc13_int::HC13_INT_SPEC>,
240 #[doc = "0x3c6ac - Host Channel x Interrupt Mask Register"]
241 pub hc13_intmsk: crate::Reg<hc13_intmsk::HC13_INTMSK_SPEC>,
242 #[doc = "0x3c6b0 - Host Channel x Transfer Size Register"]
243 pub hc13_tsiz: crate::Reg<hc13_tsiz::HC13_TSIZ_SPEC>,
244 #[doc = "0x3c6b4 - Host Channel x DMA Address Register"]
245 pub hc13_dmaaddr: crate::Reg<hc13_dmaaddr::HC13_DMAADDR_SPEC>,
246 _reserved104: [u8; 0x0148],
247 #[doc = "0x3c800 - Device Configuration Register"]
248 pub dcfg: crate::Reg<dcfg::DCFG_SPEC>,
249 #[doc = "0x3c804 - Device Control Register"]
250 pub dctl: crate::Reg<dctl::DCTL_SPEC>,
251 #[doc = "0x3c808 - Device Status Register"]
252 pub dsts: crate::Reg<dsts::DSTS_SPEC>,
253 _reserved107: [u8; 0x04],
254 #[doc = "0x3c810 - Device IN Endpoint Common Interrupt Mask Register"]
255 pub diepmsk: crate::Reg<diepmsk::DIEPMSK_SPEC>,
256 #[doc = "0x3c814 - Device OUT Endpoint Common Interrupt Mask Register"]
257 pub doepmsk: crate::Reg<doepmsk::DOEPMSK_SPEC>,
258 #[doc = "0x3c818 - Device All Endpoints Interrupt Register"]
259 pub daint: crate::Reg<daint::DAINT_SPEC>,
260 #[doc = "0x3c81c - Device All Endpoints Interrupt Mask Register"]
261 pub daintmsk: crate::Reg<daintmsk::DAINTMSK_SPEC>,
262 _reserved111: [u8; 0x08],
263 #[doc = "0x3c828 - Device VBUS Discharge Time Register"]
264 pub dvbusdis: crate::Reg<dvbusdis::DVBUSDIS_SPEC>,
265 #[doc = "0x3c82c - Device VBUS Pulsing Time Register"]
266 pub dvbuspulse: crate::Reg<dvbuspulse::DVBUSPULSE_SPEC>,
267 _reserved113: [u8; 0x04],
268 #[doc = "0x3c834 - Device IN Endpoint FIFO Empty Interrupt Mask Register"]
269 pub diepempmsk: crate::Reg<diepempmsk::DIEPEMPMSK_SPEC>,
270 _reserved114: [u8; 0xc8],
271 #[doc = "0x3c900 - Device IN Endpoint 0 Control Register"]
272 pub diep0ctl: crate::Reg<diep0ctl::DIEP0CTL_SPEC>,
273 _reserved115: [u8; 0x04],
274 #[doc = "0x3c908 - Device IN Endpoint 0 Interrupt Register"]
275 pub diep0int: crate::Reg<diep0int::DIEP0INT_SPEC>,
276 _reserved116: [u8; 0x04],
277 #[doc = "0x3c910 - Device IN Endpoint 0 Transfer Size Register"]
278 pub diep0tsiz: crate::Reg<diep0tsiz::DIEP0TSIZ_SPEC>,
279 #[doc = "0x3c914 - Device IN Endpoint 0 DMA Address Register"]
280 pub diep0dmaaddr: crate::Reg<diep0dmaaddr::DIEP0DMAADDR_SPEC>,
281 #[doc = "0x3c918 - Device IN Endpoint 0 Transmit FIFO Status Register"]
282 pub diep0txfsts: crate::Reg<diep0txfsts::DIEP0TXFSTS_SPEC>,
283 _reserved119: [u8; 0x04],
284 #[doc = "0x3c920 - Device IN Endpoint x+1 Control Register"]
285 pub diep0_ctl: crate::Reg<diep0_ctl::DIEP0_CTL_SPEC>,
286 _reserved120: [u8; 0x04],
287 #[doc = "0x3c928 - Device IN Endpoint x+1 Interrupt Register"]
288 pub diep0_int: crate::Reg<diep0_int::DIEP0_INT_SPEC>,
289 _reserved121: [u8; 0x04],
290 #[doc = "0x3c930 - Device IN Endpoint x+1 Transfer Size Register"]
291 pub diep0_tsiz: crate::Reg<diep0_tsiz::DIEP0_TSIZ_SPEC>,
292 #[doc = "0x3c934 - Device IN Endpoint x+1 DMA Address Register"]
293 pub diep0_dmaaddr: crate::Reg<diep0_dmaaddr::DIEP0_DMAADDR_SPEC>,
294 #[doc = "0x3c938 - Device IN Endpoint x+1 Transmit FIFO Status Register"]
295 pub diep0_txfsts: crate::Reg<diep0_txfsts::DIEP0_TXFSTS_SPEC>,
296 _reserved124: [u8; 0x04],
297 #[doc = "0x3c940 - Device IN Endpoint x+1 Control Register"]
298 pub diep1_ctl: crate::Reg<diep1_ctl::DIEP1_CTL_SPEC>,
299 _reserved125: [u8; 0x04],
300 #[doc = "0x3c948 - Device IN Endpoint x+1 Interrupt Register"]
301 pub diep1_int: crate::Reg<diep1_int::DIEP1_INT_SPEC>,
302 _reserved126: [u8; 0x04],
303 #[doc = "0x3c950 - Device IN Endpoint x+1 Transfer Size Register"]
304 pub diep1_tsiz: crate::Reg<diep1_tsiz::DIEP1_TSIZ_SPEC>,
305 #[doc = "0x3c954 - Device IN Endpoint x+1 DMA Address Register"]
306 pub diep1_dmaaddr: crate::Reg<diep1_dmaaddr::DIEP1_DMAADDR_SPEC>,
307 #[doc = "0x3c958 - Device IN Endpoint x+1 Transmit FIFO Status Register"]
308 pub diep1_txfsts: crate::Reg<diep1_txfsts::DIEP1_TXFSTS_SPEC>,
309 _reserved129: [u8; 0x04],
310 #[doc = "0x3c960 - Device IN Endpoint x+1 Control Register"]
311 pub diep2_ctl: crate::Reg<diep2_ctl::DIEP2_CTL_SPEC>,
312 _reserved130: [u8; 0x04],
313 #[doc = "0x3c968 - Device IN Endpoint x+1 Interrupt Register"]
314 pub diep2_int: crate::Reg<diep2_int::DIEP2_INT_SPEC>,
315 _reserved131: [u8; 0x04],
316 #[doc = "0x3c970 - Device IN Endpoint x+1 Transfer Size Register"]
317 pub diep2_tsiz: crate::Reg<diep2_tsiz::DIEP2_TSIZ_SPEC>,
318 #[doc = "0x3c974 - Device IN Endpoint x+1 DMA Address Register"]
319 pub diep2_dmaaddr: crate::Reg<diep2_dmaaddr::DIEP2_DMAADDR_SPEC>,
320 #[doc = "0x3c978 - Device IN Endpoint x+1 Transmit FIFO Status Register"]
321 pub diep2_txfsts: crate::Reg<diep2_txfsts::DIEP2_TXFSTS_SPEC>,
322 _reserved134: [u8; 0x04],
323 #[doc = "0x3c980 - Device IN Endpoint x+1 Control Register"]
324 pub diep3_ctl: crate::Reg<diep3_ctl::DIEP3_CTL_SPEC>,
325 _reserved135: [u8; 0x04],
326 #[doc = "0x3c988 - Device IN Endpoint x+1 Interrupt Register"]
327 pub diep3_int: crate::Reg<diep3_int::DIEP3_INT_SPEC>,
328 _reserved136: [u8; 0x04],
329 #[doc = "0x3c990 - Device IN Endpoint x+1 Transfer Size Register"]
330 pub diep3_tsiz: crate::Reg<diep3_tsiz::DIEP3_TSIZ_SPEC>,
331 #[doc = "0x3c994 - Device IN Endpoint x+1 DMA Address Register"]
332 pub diep3_dmaaddr: crate::Reg<diep3_dmaaddr::DIEP3_DMAADDR_SPEC>,
333 #[doc = "0x3c998 - Device IN Endpoint x+1 Transmit FIFO Status Register"]
334 pub diep3_txfsts: crate::Reg<diep3_txfsts::DIEP3_TXFSTS_SPEC>,
335 _reserved139: [u8; 0x04],
336 #[doc = "0x3c9a0 - Device IN Endpoint x+1 Control Register"]
337 pub diep4_ctl: crate::Reg<diep4_ctl::DIEP4_CTL_SPEC>,
338 _reserved140: [u8; 0x04],
339 #[doc = "0x3c9a8 - Device IN Endpoint x+1 Interrupt Register"]
340 pub diep4_int: crate::Reg<diep4_int::DIEP4_INT_SPEC>,
341 _reserved141: [u8; 0x04],
342 #[doc = "0x3c9b0 - Device IN Endpoint x+1 Transfer Size Register"]
343 pub diep4_tsiz: crate::Reg<diep4_tsiz::DIEP4_TSIZ_SPEC>,
344 #[doc = "0x3c9b4 - Device IN Endpoint x+1 DMA Address Register"]
345 pub diep4_dmaaddr: crate::Reg<diep4_dmaaddr::DIEP4_DMAADDR_SPEC>,
346 #[doc = "0x3c9b8 - Device IN Endpoint x+1 Transmit FIFO Status Register"]
347 pub diep4_txfsts: crate::Reg<diep4_txfsts::DIEP4_TXFSTS_SPEC>,
348 _reserved144: [u8; 0x04],
349 #[doc = "0x3c9c0 - Device IN Endpoint x+1 Control Register"]
350 pub diep5_ctl: crate::Reg<diep5_ctl::DIEP5_CTL_SPEC>,
351 _reserved145: [u8; 0x04],
352 #[doc = "0x3c9c8 - Device IN Endpoint x+1 Interrupt Register"]
353 pub diep5_int: crate::Reg<diep5_int::DIEP5_INT_SPEC>,
354 _reserved146: [u8; 0x04],
355 #[doc = "0x3c9d0 - Device IN Endpoint x+1 Transfer Size Register"]
356 pub diep5_tsiz: crate::Reg<diep5_tsiz::DIEP5_TSIZ_SPEC>,
357 #[doc = "0x3c9d4 - Device IN Endpoint x+1 DMA Address Register"]
358 pub diep5_dmaaddr: crate::Reg<diep5_dmaaddr::DIEP5_DMAADDR_SPEC>,
359 #[doc = "0x3c9d8 - Device IN Endpoint x+1 Transmit FIFO Status Register"]
360 pub diep5_txfsts: crate::Reg<diep5_txfsts::DIEP5_TXFSTS_SPEC>,
361 _reserved149: [u8; 0x0124],
362 #[doc = "0x3cb00 - Device OUT Endpoint 0 Control Register"]
363 pub doep0ctl: crate::Reg<doep0ctl::DOEP0CTL_SPEC>,
364 _reserved150: [u8; 0x04],
365 #[doc = "0x3cb08 - Device OUT Endpoint 0 Interrupt Register"]
366 pub doep0int: crate::Reg<doep0int::DOEP0INT_SPEC>,
367 _reserved151: [u8; 0x04],
368 #[doc = "0x3cb10 - Device OUT Endpoint 0 Transfer Size Register"]
369 pub doep0tsiz: crate::Reg<doep0tsiz::DOEP0TSIZ_SPEC>,
370 #[doc = "0x3cb14 - Device OUT Endpoint 0 DMA Address Register"]
371 pub doep0dmaaddr: crate::Reg<doep0dmaaddr::DOEP0DMAADDR_SPEC>,
372 _reserved153: [u8; 0x08],
373 #[doc = "0x3cb20 - Device OUT Endpoint x+1 Control Register"]
374 pub doep0_ctl: crate::Reg<doep0_ctl::DOEP0_CTL_SPEC>,
375 _reserved154: [u8; 0x04],
376 #[doc = "0x3cb28 - Device OUT Endpoint x+1 Interrupt Register"]
377 pub doep0_int: crate::Reg<doep0_int::DOEP0_INT_SPEC>,
378 _reserved155: [u8; 0x04],
379 #[doc = "0x3cb30 - Device OUT Endpoint x+1 Transfer Size Register"]
380 pub doep0_tsiz: crate::Reg<doep0_tsiz::DOEP0_TSIZ_SPEC>,
381 #[doc = "0x3cb34 - Device OUT Endpoint x+1 DMA Address Register"]
382 pub doep0_dmaaddr: crate::Reg<doep0_dmaaddr::DOEP0_DMAADDR_SPEC>,
383 _reserved157: [u8; 0x08],
384 #[doc = "0x3cb40 - Device OUT Endpoint x+1 Control Register"]
385 pub doep1_ctl: crate::Reg<doep1_ctl::DOEP1_CTL_SPEC>,
386 _reserved158: [u8; 0x04],
387 #[doc = "0x3cb48 - Device OUT Endpoint x+1 Interrupt Register"]
388 pub doep1_int: crate::Reg<doep1_int::DOEP1_INT_SPEC>,
389 _reserved159: [u8; 0x04],
390 #[doc = "0x3cb50 - Device OUT Endpoint x+1 Transfer Size Register"]
391 pub doep1_tsiz: crate::Reg<doep1_tsiz::DOEP1_TSIZ_SPEC>,
392 #[doc = "0x3cb54 - Device OUT Endpoint x+1 DMA Address Register"]
393 pub doep1_dmaaddr: crate::Reg<doep1_dmaaddr::DOEP1_DMAADDR_SPEC>,
394 _reserved161: [u8; 0x08],
395 #[doc = "0x3cb60 - Device OUT Endpoint x+1 Control Register"]
396 pub doep2_ctl: crate::Reg<doep2_ctl::DOEP2_CTL_SPEC>,
397 _reserved162: [u8; 0x04],
398 #[doc = "0x3cb68 - Device OUT Endpoint x+1 Interrupt Register"]
399 pub doep2_int: crate::Reg<doep2_int::DOEP2_INT_SPEC>,
400 _reserved163: [u8; 0x04],
401 #[doc = "0x3cb70 - Device OUT Endpoint x+1 Transfer Size Register"]
402 pub doep2_tsiz: crate::Reg<doep2_tsiz::DOEP2_TSIZ_SPEC>,
403 #[doc = "0x3cb74 - Device OUT Endpoint x+1 DMA Address Register"]
404 pub doep2_dmaaddr: crate::Reg<doep2_dmaaddr::DOEP2_DMAADDR_SPEC>,
405 _reserved165: [u8; 0x08],
406 #[doc = "0x3cb80 - Device OUT Endpoint x+1 Control Register"]
407 pub doep3_ctl: crate::Reg<doep3_ctl::DOEP3_CTL_SPEC>,
408 _reserved166: [u8; 0x04],
409 #[doc = "0x3cb88 - Device OUT Endpoint x+1 Interrupt Register"]
410 pub doep3_int: crate::Reg<doep3_int::DOEP3_INT_SPEC>,
411 _reserved167: [u8; 0x04],
412 #[doc = "0x3cb90 - Device OUT Endpoint x+1 Transfer Size Register"]
413 pub doep3_tsiz: crate::Reg<doep3_tsiz::DOEP3_TSIZ_SPEC>,
414 #[doc = "0x3cb94 - Device OUT Endpoint x+1 DMA Address Register"]
415 pub doep3_dmaaddr: crate::Reg<doep3_dmaaddr::DOEP3_DMAADDR_SPEC>,
416 _reserved169: [u8; 0x08],
417 #[doc = "0x3cba0 - Device OUT Endpoint x+1 Control Register"]
418 pub doep4_ctl: crate::Reg<doep4_ctl::DOEP4_CTL_SPEC>,
419 _reserved170: [u8; 0x04],
420 #[doc = "0x3cba8 - Device OUT Endpoint x+1 Interrupt Register"]
421 pub doep4_int: crate::Reg<doep4_int::DOEP4_INT_SPEC>,
422 _reserved171: [u8; 0x04],
423 #[doc = "0x3cbb0 - Device OUT Endpoint x+1 Transfer Size Register"]
424 pub doep4_tsiz: crate::Reg<doep4_tsiz::DOEP4_TSIZ_SPEC>,
425 #[doc = "0x3cbb4 - Device OUT Endpoint x+1 DMA Address Register"]
426 pub doep4_dmaaddr: crate::Reg<doep4_dmaaddr::DOEP4_DMAADDR_SPEC>,
427 _reserved173: [u8; 0x08],
428 #[doc = "0x3cbc0 - Device OUT Endpoint x+1 Control Register"]
429 pub doep5_ctl: crate::Reg<doep5_ctl::DOEP5_CTL_SPEC>,
430 _reserved174: [u8; 0x04],
431 #[doc = "0x3cbc8 - Device OUT Endpoint x+1 Interrupt Register"]
432 pub doep5_int: crate::Reg<doep5_int::DOEP5_INT_SPEC>,
433 _reserved175: [u8; 0x04],
434 #[doc = "0x3cbd0 - Device OUT Endpoint x+1 Transfer Size Register"]
435 pub doep5_tsiz: crate::Reg<doep5_tsiz::DOEP5_TSIZ_SPEC>,
436 #[doc = "0x3cbd4 - Device OUT Endpoint x+1 DMA Address Register"]
437 pub doep5_dmaaddr: crate::Reg<doep5_dmaaddr::DOEP5_DMAADDR_SPEC>,
438 _reserved177: [u8; 0x0228],
439 #[doc = "0x3ce00 - Power and Clock Gating Control Register"]
440 pub pcgcctl: crate::Reg<pcgcctl::PCGCCTL_SPEC>,
441}
442#[doc = "CTRL register accessor: an alias for `Reg<CTRL_SPEC>`"]
443pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
444#[doc = "System Control Register"]
445pub mod ctrl;
446#[doc = "STATUS register accessor: an alias for `Reg<STATUS_SPEC>`"]
447pub type STATUS = crate::Reg<status::STATUS_SPEC>;
448#[doc = "System Status Register"]
449pub mod status;
450#[doc = "IF register accessor: an alias for `Reg<IF_SPEC>`"]
451pub type IF = crate::Reg<if_::IF_SPEC>;
452#[doc = "Interrupt Flag Register"]
453pub mod if_;
454#[doc = "IFS register accessor: an alias for `Reg<IFS_SPEC>`"]
455pub type IFS = crate::Reg<ifs::IFS_SPEC>;
456#[doc = "Interrupt Flag Set Register"]
457pub mod ifs;
458#[doc = "IFC register accessor: an alias for `Reg<IFC_SPEC>`"]
459pub type IFC = crate::Reg<ifc::IFC_SPEC>;
460#[doc = "Interrupt Flag Clear Register"]
461pub mod ifc;
462#[doc = "IEN register accessor: an alias for `Reg<IEN_SPEC>`"]
463pub type IEN = crate::Reg<ien::IEN_SPEC>;
464#[doc = "Interrupt Enable Register"]
465pub mod ien;
466#[doc = "ROUTE register accessor: an alias for `Reg<ROUTE_SPEC>`"]
467pub type ROUTE = crate::Reg<route::ROUTE_SPEC>;
468#[doc = "I/O Routing Register"]
469pub mod route;
470#[doc = "GOTGCTL register accessor: an alias for `Reg<GOTGCTL_SPEC>`"]
471pub type GOTGCTL = crate::Reg<gotgctl::GOTGCTL_SPEC>;
472#[doc = "OTG Control and Status Register"]
473pub mod gotgctl;
474#[doc = "GOTGINT register accessor: an alias for `Reg<GOTGINT_SPEC>`"]
475pub type GOTGINT = crate::Reg<gotgint::GOTGINT_SPEC>;
476#[doc = "OTG Interrupt Register"]
477pub mod gotgint;
478#[doc = "GAHBCFG register accessor: an alias for `Reg<GAHBCFG_SPEC>`"]
479pub type GAHBCFG = crate::Reg<gahbcfg::GAHBCFG_SPEC>;
480#[doc = "AHB Configuration Register"]
481pub mod gahbcfg;
482#[doc = "GUSBCFG register accessor: an alias for `Reg<GUSBCFG_SPEC>`"]
483pub type GUSBCFG = crate::Reg<gusbcfg::GUSBCFG_SPEC>;
484#[doc = "USB Configuration Register"]
485pub mod gusbcfg;
486#[doc = "GRSTCTL register accessor: an alias for `Reg<GRSTCTL_SPEC>`"]
487pub type GRSTCTL = crate::Reg<grstctl::GRSTCTL_SPEC>;
488#[doc = "Reset Register"]
489pub mod grstctl;
490#[doc = "GINTSTS register accessor: an alias for `Reg<GINTSTS_SPEC>`"]
491pub type GINTSTS = crate::Reg<gintsts::GINTSTS_SPEC>;
492#[doc = "Interrupt Register"]
493pub mod gintsts;
494#[doc = "GINTMSK register accessor: an alias for `Reg<GINTMSK_SPEC>`"]
495pub type GINTMSK = crate::Reg<gintmsk::GINTMSK_SPEC>;
496#[doc = "Interrupt Mask Register"]
497pub mod gintmsk;
498#[doc = "GRXSTSR register accessor: an alias for `Reg<GRXSTSR_SPEC>`"]
499pub type GRXSTSR = crate::Reg<grxstsr::GRXSTSR_SPEC>;
500#[doc = "Receive Status Debug Read Register"]
501pub mod grxstsr;
502#[doc = "GRXSTSP register accessor: an alias for `Reg<GRXSTSP_SPEC>`"]
503pub type GRXSTSP = crate::Reg<grxstsp::GRXSTSP_SPEC>;
504#[doc = "Receive Status Read and Pop Register"]
505pub mod grxstsp;
506#[doc = "GRXFSIZ register accessor: an alias for `Reg<GRXFSIZ_SPEC>`"]
507pub type GRXFSIZ = crate::Reg<grxfsiz::GRXFSIZ_SPEC>;
508#[doc = "Receive FIFO Size Register"]
509pub mod grxfsiz;
510#[doc = "GNPTXFSIZ register accessor: an alias for `Reg<GNPTXFSIZ_SPEC>`"]
511pub type GNPTXFSIZ = crate::Reg<gnptxfsiz::GNPTXFSIZ_SPEC>;
512#[doc = "Non-periodic Transmit FIFO Size Register"]
513pub mod gnptxfsiz;
514#[doc = "GNPTXSTS register accessor: an alias for `Reg<GNPTXSTS_SPEC>`"]
515pub type GNPTXSTS = crate::Reg<gnptxsts::GNPTXSTS_SPEC>;
516#[doc = "Non-periodic Transmit FIFO/Queue Status Register"]
517pub mod gnptxsts;
518#[doc = "GDFIFOCFG register accessor: an alias for `Reg<GDFIFOCFG_SPEC>`"]
519pub type GDFIFOCFG = crate::Reg<gdfifocfg::GDFIFOCFG_SPEC>;
520#[doc = "Global DFIFO Configuration Register"]
521pub mod gdfifocfg;
522#[doc = "HPTXFSIZ register accessor: an alias for `Reg<HPTXFSIZ_SPEC>`"]
523pub type HPTXFSIZ = crate::Reg<hptxfsiz::HPTXFSIZ_SPEC>;
524#[doc = "Host Periodic Transmit FIFO Size Register"]
525pub mod hptxfsiz;
526#[doc = "DIEPTXF1 register accessor: an alias for `Reg<DIEPTXF1_SPEC>`"]
527pub type DIEPTXF1 = crate::Reg<dieptxf1::DIEPTXF1_SPEC>;
528#[doc = "Device IN Endpoint Transmit FIFO 1 Size Register"]
529pub mod dieptxf1;
530#[doc = "DIEPTXF2 register accessor: an alias for `Reg<DIEPTXF2_SPEC>`"]
531pub type DIEPTXF2 = crate::Reg<dieptxf2::DIEPTXF2_SPEC>;
532#[doc = "Device IN Endpoint Transmit FIFO 2 Size Register"]
533pub mod dieptxf2;
534#[doc = "DIEPTXF3 register accessor: an alias for `Reg<DIEPTXF3_SPEC>`"]
535pub type DIEPTXF3 = crate::Reg<dieptxf3::DIEPTXF3_SPEC>;
536#[doc = "Device IN Endpoint Transmit FIFO 3 Size Register"]
537pub mod dieptxf3;
538#[doc = "DIEPTXF4 register accessor: an alias for `Reg<DIEPTXF4_SPEC>`"]
539pub type DIEPTXF4 = crate::Reg<dieptxf4::DIEPTXF4_SPEC>;
540#[doc = "Device IN Endpoint Transmit FIFO 4 Size Register"]
541pub mod dieptxf4;
542#[doc = "DIEPTXF5 register accessor: an alias for `Reg<DIEPTXF5_SPEC>`"]
543pub type DIEPTXF5 = crate::Reg<dieptxf5::DIEPTXF5_SPEC>;
544#[doc = "Device IN Endpoint Transmit FIFO 5 Size Register"]
545pub mod dieptxf5;
546#[doc = "DIEPTXF6 register accessor: an alias for `Reg<DIEPTXF6_SPEC>`"]
547pub type DIEPTXF6 = crate::Reg<dieptxf6::DIEPTXF6_SPEC>;
548#[doc = "Device IN Endpoint Transmit FIFO 6 Size Register"]
549pub mod dieptxf6;
550#[doc = "HCFG register accessor: an alias for `Reg<HCFG_SPEC>`"]
551pub type HCFG = crate::Reg<hcfg::HCFG_SPEC>;
552#[doc = "Host Configuration Register"]
553pub mod hcfg;
554#[doc = "HFIR register accessor: an alias for `Reg<HFIR_SPEC>`"]
555pub type HFIR = crate::Reg<hfir::HFIR_SPEC>;
556#[doc = "Host Frame Interval Register"]
557pub mod hfir;
558#[doc = "HFNUM register accessor: an alias for `Reg<HFNUM_SPEC>`"]
559pub type HFNUM = crate::Reg<hfnum::HFNUM_SPEC>;
560#[doc = "Host Frame Number/Frame Time Remaining Register"]
561pub mod hfnum;
562#[doc = "HPTXSTS register accessor: an alias for `Reg<HPTXSTS_SPEC>`"]
563pub type HPTXSTS = crate::Reg<hptxsts::HPTXSTS_SPEC>;
564#[doc = "Host Periodic Transmit FIFO/Queue Status Register"]
565pub mod hptxsts;
566#[doc = "HAINT register accessor: an alias for `Reg<HAINT_SPEC>`"]
567pub type HAINT = crate::Reg<haint::HAINT_SPEC>;
568#[doc = "Host All Channels Interrupt Register"]
569pub mod haint;
570#[doc = "HAINTMSK register accessor: an alias for `Reg<HAINTMSK_SPEC>`"]
571pub type HAINTMSK = crate::Reg<haintmsk::HAINTMSK_SPEC>;
572#[doc = "Host All Channels Interrupt Mask Register"]
573pub mod haintmsk;
574#[doc = "HPRT register accessor: an alias for `Reg<HPRT_SPEC>`"]
575pub type HPRT = crate::Reg<hprt::HPRT_SPEC>;
576#[doc = "Host Port Control and Status Register"]
577pub mod hprt;
578#[doc = "HC0_CHAR register accessor: an alias for `Reg<HC0_CHAR_SPEC>`"]
579pub type HC0_CHAR = crate::Reg<hc0_char::HC0_CHAR_SPEC>;
580#[doc = "Host Channel x Characteristics Register"]
581pub mod hc0_char;
582#[doc = "HC0_INT register accessor: an alias for `Reg<HC0_INT_SPEC>`"]
583pub type HC0_INT = crate::Reg<hc0_int::HC0_INT_SPEC>;
584#[doc = "Host Channel x Interrupt Register"]
585pub mod hc0_int;
586#[doc = "HC0_INTMSK register accessor: an alias for `Reg<HC0_INTMSK_SPEC>`"]
587pub type HC0_INTMSK = crate::Reg<hc0_intmsk::HC0_INTMSK_SPEC>;
588#[doc = "Host Channel x Interrupt Mask Register"]
589pub mod hc0_intmsk;
590#[doc = "HC0_TSIZ register accessor: an alias for `Reg<HC0_TSIZ_SPEC>`"]
591pub type HC0_TSIZ = crate::Reg<hc0_tsiz::HC0_TSIZ_SPEC>;
592#[doc = "Host Channel x Transfer Size Register"]
593pub mod hc0_tsiz;
594#[doc = "HC0_DMAADDR register accessor: an alias for `Reg<HC0_DMAADDR_SPEC>`"]
595pub type HC0_DMAADDR = crate::Reg<hc0_dmaaddr::HC0_DMAADDR_SPEC>;
596#[doc = "Host Channel x DMA Address Register"]
597pub mod hc0_dmaaddr;
598#[doc = "HC1_CHAR register accessor: an alias for `Reg<HC1_CHAR_SPEC>`"]
599pub type HC1_CHAR = crate::Reg<hc1_char::HC1_CHAR_SPEC>;
600#[doc = "Host Channel x Characteristics Register"]
601pub mod hc1_char;
602#[doc = "HC1_INT register accessor: an alias for `Reg<HC1_INT_SPEC>`"]
603pub type HC1_INT = crate::Reg<hc1_int::HC1_INT_SPEC>;
604#[doc = "Host Channel x Interrupt Register"]
605pub mod hc1_int;
606#[doc = "HC1_INTMSK register accessor: an alias for `Reg<HC1_INTMSK_SPEC>`"]
607pub type HC1_INTMSK = crate::Reg<hc1_intmsk::HC1_INTMSK_SPEC>;
608#[doc = "Host Channel x Interrupt Mask Register"]
609pub mod hc1_intmsk;
610#[doc = "HC1_TSIZ register accessor: an alias for `Reg<HC1_TSIZ_SPEC>`"]
611pub type HC1_TSIZ = crate::Reg<hc1_tsiz::HC1_TSIZ_SPEC>;
612#[doc = "Host Channel x Transfer Size Register"]
613pub mod hc1_tsiz;
614#[doc = "HC1_DMAADDR register accessor: an alias for `Reg<HC1_DMAADDR_SPEC>`"]
615pub type HC1_DMAADDR = crate::Reg<hc1_dmaaddr::HC1_DMAADDR_SPEC>;
616#[doc = "Host Channel x DMA Address Register"]
617pub mod hc1_dmaaddr;
618#[doc = "HC2_CHAR register accessor: an alias for `Reg<HC2_CHAR_SPEC>`"]
619pub type HC2_CHAR = crate::Reg<hc2_char::HC2_CHAR_SPEC>;
620#[doc = "Host Channel x Characteristics Register"]
621pub mod hc2_char;
622#[doc = "HC2_INT register accessor: an alias for `Reg<HC2_INT_SPEC>`"]
623pub type HC2_INT = crate::Reg<hc2_int::HC2_INT_SPEC>;
624#[doc = "Host Channel x Interrupt Register"]
625pub mod hc2_int;
626#[doc = "HC2_INTMSK register accessor: an alias for `Reg<HC2_INTMSK_SPEC>`"]
627pub type HC2_INTMSK = crate::Reg<hc2_intmsk::HC2_INTMSK_SPEC>;
628#[doc = "Host Channel x Interrupt Mask Register"]
629pub mod hc2_intmsk;
630#[doc = "HC2_TSIZ register accessor: an alias for `Reg<HC2_TSIZ_SPEC>`"]
631pub type HC2_TSIZ = crate::Reg<hc2_tsiz::HC2_TSIZ_SPEC>;
632#[doc = "Host Channel x Transfer Size Register"]
633pub mod hc2_tsiz;
634#[doc = "HC2_DMAADDR register accessor: an alias for `Reg<HC2_DMAADDR_SPEC>`"]
635pub type HC2_DMAADDR = crate::Reg<hc2_dmaaddr::HC2_DMAADDR_SPEC>;
636#[doc = "Host Channel x DMA Address Register"]
637pub mod hc2_dmaaddr;
638#[doc = "HC3_CHAR register accessor: an alias for `Reg<HC3_CHAR_SPEC>`"]
639pub type HC3_CHAR = crate::Reg<hc3_char::HC3_CHAR_SPEC>;
640#[doc = "Host Channel x Characteristics Register"]
641pub mod hc3_char;
642#[doc = "HC3_INT register accessor: an alias for `Reg<HC3_INT_SPEC>`"]
643pub type HC3_INT = crate::Reg<hc3_int::HC3_INT_SPEC>;
644#[doc = "Host Channel x Interrupt Register"]
645pub mod hc3_int;
646#[doc = "HC3_INTMSK register accessor: an alias for `Reg<HC3_INTMSK_SPEC>`"]
647pub type HC3_INTMSK = crate::Reg<hc3_intmsk::HC3_INTMSK_SPEC>;
648#[doc = "Host Channel x Interrupt Mask Register"]
649pub mod hc3_intmsk;
650#[doc = "HC3_TSIZ register accessor: an alias for `Reg<HC3_TSIZ_SPEC>`"]
651pub type HC3_TSIZ = crate::Reg<hc3_tsiz::HC3_TSIZ_SPEC>;
652#[doc = "Host Channel x Transfer Size Register"]
653pub mod hc3_tsiz;
654#[doc = "HC3_DMAADDR register accessor: an alias for `Reg<HC3_DMAADDR_SPEC>`"]
655pub type HC3_DMAADDR = crate::Reg<hc3_dmaaddr::HC3_DMAADDR_SPEC>;
656#[doc = "Host Channel x DMA Address Register"]
657pub mod hc3_dmaaddr;
658#[doc = "HC4_CHAR register accessor: an alias for `Reg<HC4_CHAR_SPEC>`"]
659pub type HC4_CHAR = crate::Reg<hc4_char::HC4_CHAR_SPEC>;
660#[doc = "Host Channel x Characteristics Register"]
661pub mod hc4_char;
662#[doc = "HC4_INT register accessor: an alias for `Reg<HC4_INT_SPEC>`"]
663pub type HC4_INT = crate::Reg<hc4_int::HC4_INT_SPEC>;
664#[doc = "Host Channel x Interrupt Register"]
665pub mod hc4_int;
666#[doc = "HC4_INTMSK register accessor: an alias for `Reg<HC4_INTMSK_SPEC>`"]
667pub type HC4_INTMSK = crate::Reg<hc4_intmsk::HC4_INTMSK_SPEC>;
668#[doc = "Host Channel x Interrupt Mask Register"]
669pub mod hc4_intmsk;
670#[doc = "HC4_TSIZ register accessor: an alias for `Reg<HC4_TSIZ_SPEC>`"]
671pub type HC4_TSIZ = crate::Reg<hc4_tsiz::HC4_TSIZ_SPEC>;
672#[doc = "Host Channel x Transfer Size Register"]
673pub mod hc4_tsiz;
674#[doc = "HC4_DMAADDR register accessor: an alias for `Reg<HC4_DMAADDR_SPEC>`"]
675pub type HC4_DMAADDR = crate::Reg<hc4_dmaaddr::HC4_DMAADDR_SPEC>;
676#[doc = "Host Channel x DMA Address Register"]
677pub mod hc4_dmaaddr;
678#[doc = "HC5_CHAR register accessor: an alias for `Reg<HC5_CHAR_SPEC>`"]
679pub type HC5_CHAR = crate::Reg<hc5_char::HC5_CHAR_SPEC>;
680#[doc = "Host Channel x Characteristics Register"]
681pub mod hc5_char;
682#[doc = "HC5_INT register accessor: an alias for `Reg<HC5_INT_SPEC>`"]
683pub type HC5_INT = crate::Reg<hc5_int::HC5_INT_SPEC>;
684#[doc = "Host Channel x Interrupt Register"]
685pub mod hc5_int;
686#[doc = "HC5_INTMSK register accessor: an alias for `Reg<HC5_INTMSK_SPEC>`"]
687pub type HC5_INTMSK = crate::Reg<hc5_intmsk::HC5_INTMSK_SPEC>;
688#[doc = "Host Channel x Interrupt Mask Register"]
689pub mod hc5_intmsk;
690#[doc = "HC5_TSIZ register accessor: an alias for `Reg<HC5_TSIZ_SPEC>`"]
691pub type HC5_TSIZ = crate::Reg<hc5_tsiz::HC5_TSIZ_SPEC>;
692#[doc = "Host Channel x Transfer Size Register"]
693pub mod hc5_tsiz;
694#[doc = "HC5_DMAADDR register accessor: an alias for `Reg<HC5_DMAADDR_SPEC>`"]
695pub type HC5_DMAADDR = crate::Reg<hc5_dmaaddr::HC5_DMAADDR_SPEC>;
696#[doc = "Host Channel x DMA Address Register"]
697pub mod hc5_dmaaddr;
698#[doc = "HC6_CHAR register accessor: an alias for `Reg<HC6_CHAR_SPEC>`"]
699pub type HC6_CHAR = crate::Reg<hc6_char::HC6_CHAR_SPEC>;
700#[doc = "Host Channel x Characteristics Register"]
701pub mod hc6_char;
702#[doc = "HC6_INT register accessor: an alias for `Reg<HC6_INT_SPEC>`"]
703pub type HC6_INT = crate::Reg<hc6_int::HC6_INT_SPEC>;
704#[doc = "Host Channel x Interrupt Register"]
705pub mod hc6_int;
706#[doc = "HC6_INTMSK register accessor: an alias for `Reg<HC6_INTMSK_SPEC>`"]
707pub type HC6_INTMSK = crate::Reg<hc6_intmsk::HC6_INTMSK_SPEC>;
708#[doc = "Host Channel x Interrupt Mask Register"]
709pub mod hc6_intmsk;
710#[doc = "HC6_TSIZ register accessor: an alias for `Reg<HC6_TSIZ_SPEC>`"]
711pub type HC6_TSIZ = crate::Reg<hc6_tsiz::HC6_TSIZ_SPEC>;
712#[doc = "Host Channel x Transfer Size Register"]
713pub mod hc6_tsiz;
714#[doc = "HC6_DMAADDR register accessor: an alias for `Reg<HC6_DMAADDR_SPEC>`"]
715pub type HC6_DMAADDR = crate::Reg<hc6_dmaaddr::HC6_DMAADDR_SPEC>;
716#[doc = "Host Channel x DMA Address Register"]
717pub mod hc6_dmaaddr;
718#[doc = "HC7_CHAR register accessor: an alias for `Reg<HC7_CHAR_SPEC>`"]
719pub type HC7_CHAR = crate::Reg<hc7_char::HC7_CHAR_SPEC>;
720#[doc = "Host Channel x Characteristics Register"]
721pub mod hc7_char;
722#[doc = "HC7_INT register accessor: an alias for `Reg<HC7_INT_SPEC>`"]
723pub type HC7_INT = crate::Reg<hc7_int::HC7_INT_SPEC>;
724#[doc = "Host Channel x Interrupt Register"]
725pub mod hc7_int;
726#[doc = "HC7_INTMSK register accessor: an alias for `Reg<HC7_INTMSK_SPEC>`"]
727pub type HC7_INTMSK = crate::Reg<hc7_intmsk::HC7_INTMSK_SPEC>;
728#[doc = "Host Channel x Interrupt Mask Register"]
729pub mod hc7_intmsk;
730#[doc = "HC7_TSIZ register accessor: an alias for `Reg<HC7_TSIZ_SPEC>`"]
731pub type HC7_TSIZ = crate::Reg<hc7_tsiz::HC7_TSIZ_SPEC>;
732#[doc = "Host Channel x Transfer Size Register"]
733pub mod hc7_tsiz;
734#[doc = "HC7_DMAADDR register accessor: an alias for `Reg<HC7_DMAADDR_SPEC>`"]
735pub type HC7_DMAADDR = crate::Reg<hc7_dmaaddr::HC7_DMAADDR_SPEC>;
736#[doc = "Host Channel x DMA Address Register"]
737pub mod hc7_dmaaddr;
738#[doc = "HC8_CHAR register accessor: an alias for `Reg<HC8_CHAR_SPEC>`"]
739pub type HC8_CHAR = crate::Reg<hc8_char::HC8_CHAR_SPEC>;
740#[doc = "Host Channel x Characteristics Register"]
741pub mod hc8_char;
742#[doc = "HC8_INT register accessor: an alias for `Reg<HC8_INT_SPEC>`"]
743pub type HC8_INT = crate::Reg<hc8_int::HC8_INT_SPEC>;
744#[doc = "Host Channel x Interrupt Register"]
745pub mod hc8_int;
746#[doc = "HC8_INTMSK register accessor: an alias for `Reg<HC8_INTMSK_SPEC>`"]
747pub type HC8_INTMSK = crate::Reg<hc8_intmsk::HC8_INTMSK_SPEC>;
748#[doc = "Host Channel x Interrupt Mask Register"]
749pub mod hc8_intmsk;
750#[doc = "HC8_TSIZ register accessor: an alias for `Reg<HC8_TSIZ_SPEC>`"]
751pub type HC8_TSIZ = crate::Reg<hc8_tsiz::HC8_TSIZ_SPEC>;
752#[doc = "Host Channel x Transfer Size Register"]
753pub mod hc8_tsiz;
754#[doc = "HC8_DMAADDR register accessor: an alias for `Reg<HC8_DMAADDR_SPEC>`"]
755pub type HC8_DMAADDR = crate::Reg<hc8_dmaaddr::HC8_DMAADDR_SPEC>;
756#[doc = "Host Channel x DMA Address Register"]
757pub mod hc8_dmaaddr;
758#[doc = "HC9_CHAR register accessor: an alias for `Reg<HC9_CHAR_SPEC>`"]
759pub type HC9_CHAR = crate::Reg<hc9_char::HC9_CHAR_SPEC>;
760#[doc = "Host Channel x Characteristics Register"]
761pub mod hc9_char;
762#[doc = "HC9_INT register accessor: an alias for `Reg<HC9_INT_SPEC>`"]
763pub type HC9_INT = crate::Reg<hc9_int::HC9_INT_SPEC>;
764#[doc = "Host Channel x Interrupt Register"]
765pub mod hc9_int;
766#[doc = "HC9_INTMSK register accessor: an alias for `Reg<HC9_INTMSK_SPEC>`"]
767pub type HC9_INTMSK = crate::Reg<hc9_intmsk::HC9_INTMSK_SPEC>;
768#[doc = "Host Channel x Interrupt Mask Register"]
769pub mod hc9_intmsk;
770#[doc = "HC9_TSIZ register accessor: an alias for `Reg<HC9_TSIZ_SPEC>`"]
771pub type HC9_TSIZ = crate::Reg<hc9_tsiz::HC9_TSIZ_SPEC>;
772#[doc = "Host Channel x Transfer Size Register"]
773pub mod hc9_tsiz;
774#[doc = "HC9_DMAADDR register accessor: an alias for `Reg<HC9_DMAADDR_SPEC>`"]
775pub type HC9_DMAADDR = crate::Reg<hc9_dmaaddr::HC9_DMAADDR_SPEC>;
776#[doc = "Host Channel x DMA Address Register"]
777pub mod hc9_dmaaddr;
778#[doc = "HC10_CHAR register accessor: an alias for `Reg<HC10_CHAR_SPEC>`"]
779pub type HC10_CHAR = crate::Reg<hc10_char::HC10_CHAR_SPEC>;
780#[doc = "Host Channel x Characteristics Register"]
781pub mod hc10_char;
782#[doc = "HC10_INT register accessor: an alias for `Reg<HC10_INT_SPEC>`"]
783pub type HC10_INT = crate::Reg<hc10_int::HC10_INT_SPEC>;
784#[doc = "Host Channel x Interrupt Register"]
785pub mod hc10_int;
786#[doc = "HC10_INTMSK register accessor: an alias for `Reg<HC10_INTMSK_SPEC>`"]
787pub type HC10_INTMSK = crate::Reg<hc10_intmsk::HC10_INTMSK_SPEC>;
788#[doc = "Host Channel x Interrupt Mask Register"]
789pub mod hc10_intmsk;
790#[doc = "HC10_TSIZ register accessor: an alias for `Reg<HC10_TSIZ_SPEC>`"]
791pub type HC10_TSIZ = crate::Reg<hc10_tsiz::HC10_TSIZ_SPEC>;
792#[doc = "Host Channel x Transfer Size Register"]
793pub mod hc10_tsiz;
794#[doc = "HC10_DMAADDR register accessor: an alias for `Reg<HC10_DMAADDR_SPEC>`"]
795pub type HC10_DMAADDR = crate::Reg<hc10_dmaaddr::HC10_DMAADDR_SPEC>;
796#[doc = "Host Channel x DMA Address Register"]
797pub mod hc10_dmaaddr;
798#[doc = "HC11_CHAR register accessor: an alias for `Reg<HC11_CHAR_SPEC>`"]
799pub type HC11_CHAR = crate::Reg<hc11_char::HC11_CHAR_SPEC>;
800#[doc = "Host Channel x Characteristics Register"]
801pub mod hc11_char;
802#[doc = "HC11_INT register accessor: an alias for `Reg<HC11_INT_SPEC>`"]
803pub type HC11_INT = crate::Reg<hc11_int::HC11_INT_SPEC>;
804#[doc = "Host Channel x Interrupt Register"]
805pub mod hc11_int;
806#[doc = "HC11_INTMSK register accessor: an alias for `Reg<HC11_INTMSK_SPEC>`"]
807pub type HC11_INTMSK = crate::Reg<hc11_intmsk::HC11_INTMSK_SPEC>;
808#[doc = "Host Channel x Interrupt Mask Register"]
809pub mod hc11_intmsk;
810#[doc = "HC11_TSIZ register accessor: an alias for `Reg<HC11_TSIZ_SPEC>`"]
811pub type HC11_TSIZ = crate::Reg<hc11_tsiz::HC11_TSIZ_SPEC>;
812#[doc = "Host Channel x Transfer Size Register"]
813pub mod hc11_tsiz;
814#[doc = "HC11_DMAADDR register accessor: an alias for `Reg<HC11_DMAADDR_SPEC>`"]
815pub type HC11_DMAADDR = crate::Reg<hc11_dmaaddr::HC11_DMAADDR_SPEC>;
816#[doc = "Host Channel x DMA Address Register"]
817pub mod hc11_dmaaddr;
818#[doc = "HC12_CHAR register accessor: an alias for `Reg<HC12_CHAR_SPEC>`"]
819pub type HC12_CHAR = crate::Reg<hc12_char::HC12_CHAR_SPEC>;
820#[doc = "Host Channel x Characteristics Register"]
821pub mod hc12_char;
822#[doc = "HC12_INT register accessor: an alias for `Reg<HC12_INT_SPEC>`"]
823pub type HC12_INT = crate::Reg<hc12_int::HC12_INT_SPEC>;
824#[doc = "Host Channel x Interrupt Register"]
825pub mod hc12_int;
826#[doc = "HC12_INTMSK register accessor: an alias for `Reg<HC12_INTMSK_SPEC>`"]
827pub type HC12_INTMSK = crate::Reg<hc12_intmsk::HC12_INTMSK_SPEC>;
828#[doc = "Host Channel x Interrupt Mask Register"]
829pub mod hc12_intmsk;
830#[doc = "HC12_TSIZ register accessor: an alias for `Reg<HC12_TSIZ_SPEC>`"]
831pub type HC12_TSIZ = crate::Reg<hc12_tsiz::HC12_TSIZ_SPEC>;
832#[doc = "Host Channel x Transfer Size Register"]
833pub mod hc12_tsiz;
834#[doc = "HC12_DMAADDR register accessor: an alias for `Reg<HC12_DMAADDR_SPEC>`"]
835pub type HC12_DMAADDR = crate::Reg<hc12_dmaaddr::HC12_DMAADDR_SPEC>;
836#[doc = "Host Channel x DMA Address Register"]
837pub mod hc12_dmaaddr;
838#[doc = "HC13_CHAR register accessor: an alias for `Reg<HC13_CHAR_SPEC>`"]
839pub type HC13_CHAR = crate::Reg<hc13_char::HC13_CHAR_SPEC>;
840#[doc = "Host Channel x Characteristics Register"]
841pub mod hc13_char;
842#[doc = "HC13_INT register accessor: an alias for `Reg<HC13_INT_SPEC>`"]
843pub type HC13_INT = crate::Reg<hc13_int::HC13_INT_SPEC>;
844#[doc = "Host Channel x Interrupt Register"]
845pub mod hc13_int;
846#[doc = "HC13_INTMSK register accessor: an alias for `Reg<HC13_INTMSK_SPEC>`"]
847pub type HC13_INTMSK = crate::Reg<hc13_intmsk::HC13_INTMSK_SPEC>;
848#[doc = "Host Channel x Interrupt Mask Register"]
849pub mod hc13_intmsk;
850#[doc = "HC13_TSIZ register accessor: an alias for `Reg<HC13_TSIZ_SPEC>`"]
851pub type HC13_TSIZ = crate::Reg<hc13_tsiz::HC13_TSIZ_SPEC>;
852#[doc = "Host Channel x Transfer Size Register"]
853pub mod hc13_tsiz;
854#[doc = "HC13_DMAADDR register accessor: an alias for `Reg<HC13_DMAADDR_SPEC>`"]
855pub type HC13_DMAADDR = crate::Reg<hc13_dmaaddr::HC13_DMAADDR_SPEC>;
856#[doc = "Host Channel x DMA Address Register"]
857pub mod hc13_dmaaddr;
858#[doc = "DCFG register accessor: an alias for `Reg<DCFG_SPEC>`"]
859pub type DCFG = crate::Reg<dcfg::DCFG_SPEC>;
860#[doc = "Device Configuration Register"]
861pub mod dcfg;
862#[doc = "DCTL register accessor: an alias for `Reg<DCTL_SPEC>`"]
863pub type DCTL = crate::Reg<dctl::DCTL_SPEC>;
864#[doc = "Device Control Register"]
865pub mod dctl;
866#[doc = "DSTS register accessor: an alias for `Reg<DSTS_SPEC>`"]
867pub type DSTS = crate::Reg<dsts::DSTS_SPEC>;
868#[doc = "Device Status Register"]
869pub mod dsts;
870#[doc = "DIEPMSK register accessor: an alias for `Reg<DIEPMSK_SPEC>`"]
871pub type DIEPMSK = crate::Reg<diepmsk::DIEPMSK_SPEC>;
872#[doc = "Device IN Endpoint Common Interrupt Mask Register"]
873pub mod diepmsk;
874#[doc = "DOEPMSK register accessor: an alias for `Reg<DOEPMSK_SPEC>`"]
875pub type DOEPMSK = crate::Reg<doepmsk::DOEPMSK_SPEC>;
876#[doc = "Device OUT Endpoint Common Interrupt Mask Register"]
877pub mod doepmsk;
878#[doc = "DAINT register accessor: an alias for `Reg<DAINT_SPEC>`"]
879pub type DAINT = crate::Reg<daint::DAINT_SPEC>;
880#[doc = "Device All Endpoints Interrupt Register"]
881pub mod daint;
882#[doc = "DAINTMSK register accessor: an alias for `Reg<DAINTMSK_SPEC>`"]
883pub type DAINTMSK = crate::Reg<daintmsk::DAINTMSK_SPEC>;
884#[doc = "Device All Endpoints Interrupt Mask Register"]
885pub mod daintmsk;
886#[doc = "DVBUSDIS register accessor: an alias for `Reg<DVBUSDIS_SPEC>`"]
887pub type DVBUSDIS = crate::Reg<dvbusdis::DVBUSDIS_SPEC>;
888#[doc = "Device VBUS Discharge Time Register"]
889pub mod dvbusdis;
890#[doc = "DVBUSPULSE register accessor: an alias for `Reg<DVBUSPULSE_SPEC>`"]
891pub type DVBUSPULSE = crate::Reg<dvbuspulse::DVBUSPULSE_SPEC>;
892#[doc = "Device VBUS Pulsing Time Register"]
893pub mod dvbuspulse;
894#[doc = "DIEPEMPMSK register accessor: an alias for `Reg<DIEPEMPMSK_SPEC>`"]
895pub type DIEPEMPMSK = crate::Reg<diepempmsk::DIEPEMPMSK_SPEC>;
896#[doc = "Device IN Endpoint FIFO Empty Interrupt Mask Register"]
897pub mod diepempmsk;
898#[doc = "DIEP0CTL register accessor: an alias for `Reg<DIEP0CTL_SPEC>`"]
899pub type DIEP0CTL = crate::Reg<diep0ctl::DIEP0CTL_SPEC>;
900#[doc = "Device IN Endpoint 0 Control Register"]
901pub mod diep0ctl;
902#[doc = "DIEP0INT register accessor: an alias for `Reg<DIEP0INT_SPEC>`"]
903pub type DIEP0INT = crate::Reg<diep0int::DIEP0INT_SPEC>;
904#[doc = "Device IN Endpoint 0 Interrupt Register"]
905pub mod diep0int;
906#[doc = "DIEP0TSIZ register accessor: an alias for `Reg<DIEP0TSIZ_SPEC>`"]
907pub type DIEP0TSIZ = crate::Reg<diep0tsiz::DIEP0TSIZ_SPEC>;
908#[doc = "Device IN Endpoint 0 Transfer Size Register"]
909pub mod diep0tsiz;
910#[doc = "DIEP0DMAADDR register accessor: an alias for `Reg<DIEP0DMAADDR_SPEC>`"]
911pub type DIEP0DMAADDR = crate::Reg<diep0dmaaddr::DIEP0DMAADDR_SPEC>;
912#[doc = "Device IN Endpoint 0 DMA Address Register"]
913pub mod diep0dmaaddr;
914#[doc = "DIEP0TXFSTS register accessor: an alias for `Reg<DIEP0TXFSTS_SPEC>`"]
915pub type DIEP0TXFSTS = crate::Reg<diep0txfsts::DIEP0TXFSTS_SPEC>;
916#[doc = "Device IN Endpoint 0 Transmit FIFO Status Register"]
917pub mod diep0txfsts;
918#[doc = "DIEP0_CTL register accessor: an alias for `Reg<DIEP0_CTL_SPEC>`"]
919pub type DIEP0_CTL = crate::Reg<diep0_ctl::DIEP0_CTL_SPEC>;
920#[doc = "Device IN Endpoint x+1 Control Register"]
921pub mod diep0_ctl;
922#[doc = "DIEP0_INT register accessor: an alias for `Reg<DIEP0_INT_SPEC>`"]
923pub type DIEP0_INT = crate::Reg<diep0_int::DIEP0_INT_SPEC>;
924#[doc = "Device IN Endpoint x+1 Interrupt Register"]
925pub mod diep0_int;
926#[doc = "DIEP0_TSIZ register accessor: an alias for `Reg<DIEP0_TSIZ_SPEC>`"]
927pub type DIEP0_TSIZ = crate::Reg<diep0_tsiz::DIEP0_TSIZ_SPEC>;
928#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
929pub mod diep0_tsiz;
930#[doc = "DIEP0_DMAADDR register accessor: an alias for `Reg<DIEP0_DMAADDR_SPEC>`"]
931pub type DIEP0_DMAADDR = crate::Reg<diep0_dmaaddr::DIEP0_DMAADDR_SPEC>;
932#[doc = "Device IN Endpoint x+1 DMA Address Register"]
933pub mod diep0_dmaaddr;
934#[doc = "DIEP0_TXFSTS register accessor: an alias for `Reg<DIEP0_TXFSTS_SPEC>`"]
935pub type DIEP0_TXFSTS = crate::Reg<diep0_txfsts::DIEP0_TXFSTS_SPEC>;
936#[doc = "Device IN Endpoint x+1 Transmit FIFO Status Register"]
937pub mod diep0_txfsts;
938#[doc = "DIEP1_CTL register accessor: an alias for `Reg<DIEP1_CTL_SPEC>`"]
939pub type DIEP1_CTL = crate::Reg<diep1_ctl::DIEP1_CTL_SPEC>;
940#[doc = "Device IN Endpoint x+1 Control Register"]
941pub mod diep1_ctl;
942#[doc = "DIEP1_INT register accessor: an alias for `Reg<DIEP1_INT_SPEC>`"]
943pub type DIEP1_INT = crate::Reg<diep1_int::DIEP1_INT_SPEC>;
944#[doc = "Device IN Endpoint x+1 Interrupt Register"]
945pub mod diep1_int;
946#[doc = "DIEP1_TSIZ register accessor: an alias for `Reg<DIEP1_TSIZ_SPEC>`"]
947pub type DIEP1_TSIZ = crate::Reg<diep1_tsiz::DIEP1_TSIZ_SPEC>;
948#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
949pub mod diep1_tsiz;
950#[doc = "DIEP1_DMAADDR register accessor: an alias for `Reg<DIEP1_DMAADDR_SPEC>`"]
951pub type DIEP1_DMAADDR = crate::Reg<diep1_dmaaddr::DIEP1_DMAADDR_SPEC>;
952#[doc = "Device IN Endpoint x+1 DMA Address Register"]
953pub mod diep1_dmaaddr;
954#[doc = "DIEP1_TXFSTS register accessor: an alias for `Reg<DIEP1_TXFSTS_SPEC>`"]
955pub type DIEP1_TXFSTS = crate::Reg<diep1_txfsts::DIEP1_TXFSTS_SPEC>;
956#[doc = "Device IN Endpoint x+1 Transmit FIFO Status Register"]
957pub mod diep1_txfsts;
958#[doc = "DIEP2_CTL register accessor: an alias for `Reg<DIEP2_CTL_SPEC>`"]
959pub type DIEP2_CTL = crate::Reg<diep2_ctl::DIEP2_CTL_SPEC>;
960#[doc = "Device IN Endpoint x+1 Control Register"]
961pub mod diep2_ctl;
962#[doc = "DIEP2_INT register accessor: an alias for `Reg<DIEP2_INT_SPEC>`"]
963pub type DIEP2_INT = crate::Reg<diep2_int::DIEP2_INT_SPEC>;
964#[doc = "Device IN Endpoint x+1 Interrupt Register"]
965pub mod diep2_int;
966#[doc = "DIEP2_TSIZ register accessor: an alias for `Reg<DIEP2_TSIZ_SPEC>`"]
967pub type DIEP2_TSIZ = crate::Reg<diep2_tsiz::DIEP2_TSIZ_SPEC>;
968#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
969pub mod diep2_tsiz;
970#[doc = "DIEP2_DMAADDR register accessor: an alias for `Reg<DIEP2_DMAADDR_SPEC>`"]
971pub type DIEP2_DMAADDR = crate::Reg<diep2_dmaaddr::DIEP2_DMAADDR_SPEC>;
972#[doc = "Device IN Endpoint x+1 DMA Address Register"]
973pub mod diep2_dmaaddr;
974#[doc = "DIEP2_TXFSTS register accessor: an alias for `Reg<DIEP2_TXFSTS_SPEC>`"]
975pub type DIEP2_TXFSTS = crate::Reg<diep2_txfsts::DIEP2_TXFSTS_SPEC>;
976#[doc = "Device IN Endpoint x+1 Transmit FIFO Status Register"]
977pub mod diep2_txfsts;
978#[doc = "DIEP3_CTL register accessor: an alias for `Reg<DIEP3_CTL_SPEC>`"]
979pub type DIEP3_CTL = crate::Reg<diep3_ctl::DIEP3_CTL_SPEC>;
980#[doc = "Device IN Endpoint x+1 Control Register"]
981pub mod diep3_ctl;
982#[doc = "DIEP3_INT register accessor: an alias for `Reg<DIEP3_INT_SPEC>`"]
983pub type DIEP3_INT = crate::Reg<diep3_int::DIEP3_INT_SPEC>;
984#[doc = "Device IN Endpoint x+1 Interrupt Register"]
985pub mod diep3_int;
986#[doc = "DIEP3_TSIZ register accessor: an alias for `Reg<DIEP3_TSIZ_SPEC>`"]
987pub type DIEP3_TSIZ = crate::Reg<diep3_tsiz::DIEP3_TSIZ_SPEC>;
988#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
989pub mod diep3_tsiz;
990#[doc = "DIEP3_DMAADDR register accessor: an alias for `Reg<DIEP3_DMAADDR_SPEC>`"]
991pub type DIEP3_DMAADDR = crate::Reg<diep3_dmaaddr::DIEP3_DMAADDR_SPEC>;
992#[doc = "Device IN Endpoint x+1 DMA Address Register"]
993pub mod diep3_dmaaddr;
994#[doc = "DIEP3_TXFSTS register accessor: an alias for `Reg<DIEP3_TXFSTS_SPEC>`"]
995pub type DIEP3_TXFSTS = crate::Reg<diep3_txfsts::DIEP3_TXFSTS_SPEC>;
996#[doc = "Device IN Endpoint x+1 Transmit FIFO Status Register"]
997pub mod diep3_txfsts;
998#[doc = "DIEP4_CTL register accessor: an alias for `Reg<DIEP4_CTL_SPEC>`"]
999pub type DIEP4_CTL = crate::Reg<diep4_ctl::DIEP4_CTL_SPEC>;
1000#[doc = "Device IN Endpoint x+1 Control Register"]
1001pub mod diep4_ctl;
1002#[doc = "DIEP4_INT register accessor: an alias for `Reg<DIEP4_INT_SPEC>`"]
1003pub type DIEP4_INT = crate::Reg<diep4_int::DIEP4_INT_SPEC>;
1004#[doc = "Device IN Endpoint x+1 Interrupt Register"]
1005pub mod diep4_int;
1006#[doc = "DIEP4_TSIZ register accessor: an alias for `Reg<DIEP4_TSIZ_SPEC>`"]
1007pub type DIEP4_TSIZ = crate::Reg<diep4_tsiz::DIEP4_TSIZ_SPEC>;
1008#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
1009pub mod diep4_tsiz;
1010#[doc = "DIEP4_DMAADDR register accessor: an alias for `Reg<DIEP4_DMAADDR_SPEC>`"]
1011pub type DIEP4_DMAADDR = crate::Reg<diep4_dmaaddr::DIEP4_DMAADDR_SPEC>;
1012#[doc = "Device IN Endpoint x+1 DMA Address Register"]
1013pub mod diep4_dmaaddr;
1014#[doc = "DIEP4_TXFSTS register accessor: an alias for `Reg<DIEP4_TXFSTS_SPEC>`"]
1015pub type DIEP4_TXFSTS = crate::Reg<diep4_txfsts::DIEP4_TXFSTS_SPEC>;
1016#[doc = "Device IN Endpoint x+1 Transmit FIFO Status Register"]
1017pub mod diep4_txfsts;
1018#[doc = "DIEP5_CTL register accessor: an alias for `Reg<DIEP5_CTL_SPEC>`"]
1019pub type DIEP5_CTL = crate::Reg<diep5_ctl::DIEP5_CTL_SPEC>;
1020#[doc = "Device IN Endpoint x+1 Control Register"]
1021pub mod diep5_ctl;
1022#[doc = "DIEP5_INT register accessor: an alias for `Reg<DIEP5_INT_SPEC>`"]
1023pub type DIEP5_INT = crate::Reg<diep5_int::DIEP5_INT_SPEC>;
1024#[doc = "Device IN Endpoint x+1 Interrupt Register"]
1025pub mod diep5_int;
1026#[doc = "DIEP5_TSIZ register accessor: an alias for `Reg<DIEP5_TSIZ_SPEC>`"]
1027pub type DIEP5_TSIZ = crate::Reg<diep5_tsiz::DIEP5_TSIZ_SPEC>;
1028#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
1029pub mod diep5_tsiz;
1030#[doc = "DIEP5_DMAADDR register accessor: an alias for `Reg<DIEP5_DMAADDR_SPEC>`"]
1031pub type DIEP5_DMAADDR = crate::Reg<diep5_dmaaddr::DIEP5_DMAADDR_SPEC>;
1032#[doc = "Device IN Endpoint x+1 DMA Address Register"]
1033pub mod diep5_dmaaddr;
1034#[doc = "DIEP5_TXFSTS register accessor: an alias for `Reg<DIEP5_TXFSTS_SPEC>`"]
1035pub type DIEP5_TXFSTS = crate::Reg<diep5_txfsts::DIEP5_TXFSTS_SPEC>;
1036#[doc = "Device IN Endpoint x+1 Transmit FIFO Status Register"]
1037pub mod diep5_txfsts;
1038#[doc = "DOEP0CTL register accessor: an alias for `Reg<DOEP0CTL_SPEC>`"]
1039pub type DOEP0CTL = crate::Reg<doep0ctl::DOEP0CTL_SPEC>;
1040#[doc = "Device OUT Endpoint 0 Control Register"]
1041pub mod doep0ctl;
1042#[doc = "DOEP0INT register accessor: an alias for `Reg<DOEP0INT_SPEC>`"]
1043pub type DOEP0INT = crate::Reg<doep0int::DOEP0INT_SPEC>;
1044#[doc = "Device OUT Endpoint 0 Interrupt Register"]
1045pub mod doep0int;
1046#[doc = "DOEP0TSIZ register accessor: an alias for `Reg<DOEP0TSIZ_SPEC>`"]
1047pub type DOEP0TSIZ = crate::Reg<doep0tsiz::DOEP0TSIZ_SPEC>;
1048#[doc = "Device OUT Endpoint 0 Transfer Size Register"]
1049pub mod doep0tsiz;
1050#[doc = "DOEP0DMAADDR register accessor: an alias for `Reg<DOEP0DMAADDR_SPEC>`"]
1051pub type DOEP0DMAADDR = crate::Reg<doep0dmaaddr::DOEP0DMAADDR_SPEC>;
1052#[doc = "Device OUT Endpoint 0 DMA Address Register"]
1053pub mod doep0dmaaddr;
1054#[doc = "DOEP0_CTL register accessor: an alias for `Reg<DOEP0_CTL_SPEC>`"]
1055pub type DOEP0_CTL = crate::Reg<doep0_ctl::DOEP0_CTL_SPEC>;
1056#[doc = "Device OUT Endpoint x+1 Control Register"]
1057pub mod doep0_ctl;
1058#[doc = "DOEP0_INT register accessor: an alias for `Reg<DOEP0_INT_SPEC>`"]
1059pub type DOEP0_INT = crate::Reg<doep0_int::DOEP0_INT_SPEC>;
1060#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1061pub mod doep0_int;
1062#[doc = "DOEP0_TSIZ register accessor: an alias for `Reg<DOEP0_TSIZ_SPEC>`"]
1063pub type DOEP0_TSIZ = crate::Reg<doep0_tsiz::DOEP0_TSIZ_SPEC>;
1064#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1065pub mod doep0_tsiz;
1066#[doc = "DOEP0_DMAADDR register accessor: an alias for `Reg<DOEP0_DMAADDR_SPEC>`"]
1067pub type DOEP0_DMAADDR = crate::Reg<doep0_dmaaddr::DOEP0_DMAADDR_SPEC>;
1068#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1069pub mod doep0_dmaaddr;
1070#[doc = "DOEP1_CTL register accessor: an alias for `Reg<DOEP1_CTL_SPEC>`"]
1071pub type DOEP1_CTL = crate::Reg<doep1_ctl::DOEP1_CTL_SPEC>;
1072#[doc = "Device OUT Endpoint x+1 Control Register"]
1073pub mod doep1_ctl;
1074#[doc = "DOEP1_INT register accessor: an alias for `Reg<DOEP1_INT_SPEC>`"]
1075pub type DOEP1_INT = crate::Reg<doep1_int::DOEP1_INT_SPEC>;
1076#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1077pub mod doep1_int;
1078#[doc = "DOEP1_TSIZ register accessor: an alias for `Reg<DOEP1_TSIZ_SPEC>`"]
1079pub type DOEP1_TSIZ = crate::Reg<doep1_tsiz::DOEP1_TSIZ_SPEC>;
1080#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1081pub mod doep1_tsiz;
1082#[doc = "DOEP1_DMAADDR register accessor: an alias for `Reg<DOEP1_DMAADDR_SPEC>`"]
1083pub type DOEP1_DMAADDR = crate::Reg<doep1_dmaaddr::DOEP1_DMAADDR_SPEC>;
1084#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1085pub mod doep1_dmaaddr;
1086#[doc = "DOEP2_CTL register accessor: an alias for `Reg<DOEP2_CTL_SPEC>`"]
1087pub type DOEP2_CTL = crate::Reg<doep2_ctl::DOEP2_CTL_SPEC>;
1088#[doc = "Device OUT Endpoint x+1 Control Register"]
1089pub mod doep2_ctl;
1090#[doc = "DOEP2_INT register accessor: an alias for `Reg<DOEP2_INT_SPEC>`"]
1091pub type DOEP2_INT = crate::Reg<doep2_int::DOEP2_INT_SPEC>;
1092#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1093pub mod doep2_int;
1094#[doc = "DOEP2_TSIZ register accessor: an alias for `Reg<DOEP2_TSIZ_SPEC>`"]
1095pub type DOEP2_TSIZ = crate::Reg<doep2_tsiz::DOEP2_TSIZ_SPEC>;
1096#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1097pub mod doep2_tsiz;
1098#[doc = "DOEP2_DMAADDR register accessor: an alias for `Reg<DOEP2_DMAADDR_SPEC>`"]
1099pub type DOEP2_DMAADDR = crate::Reg<doep2_dmaaddr::DOEP2_DMAADDR_SPEC>;
1100#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1101pub mod doep2_dmaaddr;
1102#[doc = "DOEP3_CTL register accessor: an alias for `Reg<DOEP3_CTL_SPEC>`"]
1103pub type DOEP3_CTL = crate::Reg<doep3_ctl::DOEP3_CTL_SPEC>;
1104#[doc = "Device OUT Endpoint x+1 Control Register"]
1105pub mod doep3_ctl;
1106#[doc = "DOEP3_INT register accessor: an alias for `Reg<DOEP3_INT_SPEC>`"]
1107pub type DOEP3_INT = crate::Reg<doep3_int::DOEP3_INT_SPEC>;
1108#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1109pub mod doep3_int;
1110#[doc = "DOEP3_TSIZ register accessor: an alias for `Reg<DOEP3_TSIZ_SPEC>`"]
1111pub type DOEP3_TSIZ = crate::Reg<doep3_tsiz::DOEP3_TSIZ_SPEC>;
1112#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1113pub mod doep3_tsiz;
1114#[doc = "DOEP3_DMAADDR register accessor: an alias for `Reg<DOEP3_DMAADDR_SPEC>`"]
1115pub type DOEP3_DMAADDR = crate::Reg<doep3_dmaaddr::DOEP3_DMAADDR_SPEC>;
1116#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1117pub mod doep3_dmaaddr;
1118#[doc = "DOEP4_CTL register accessor: an alias for `Reg<DOEP4_CTL_SPEC>`"]
1119pub type DOEP4_CTL = crate::Reg<doep4_ctl::DOEP4_CTL_SPEC>;
1120#[doc = "Device OUT Endpoint x+1 Control Register"]
1121pub mod doep4_ctl;
1122#[doc = "DOEP4_INT register accessor: an alias for `Reg<DOEP4_INT_SPEC>`"]
1123pub type DOEP4_INT = crate::Reg<doep4_int::DOEP4_INT_SPEC>;
1124#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1125pub mod doep4_int;
1126#[doc = "DOEP4_TSIZ register accessor: an alias for `Reg<DOEP4_TSIZ_SPEC>`"]
1127pub type DOEP4_TSIZ = crate::Reg<doep4_tsiz::DOEP4_TSIZ_SPEC>;
1128#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1129pub mod doep4_tsiz;
1130#[doc = "DOEP4_DMAADDR register accessor: an alias for `Reg<DOEP4_DMAADDR_SPEC>`"]
1131pub type DOEP4_DMAADDR = crate::Reg<doep4_dmaaddr::DOEP4_DMAADDR_SPEC>;
1132#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1133pub mod doep4_dmaaddr;
1134#[doc = "DOEP5_CTL register accessor: an alias for `Reg<DOEP5_CTL_SPEC>`"]
1135pub type DOEP5_CTL = crate::Reg<doep5_ctl::DOEP5_CTL_SPEC>;
1136#[doc = "Device OUT Endpoint x+1 Control Register"]
1137pub mod doep5_ctl;
1138#[doc = "DOEP5_INT register accessor: an alias for `Reg<DOEP5_INT_SPEC>`"]
1139pub type DOEP5_INT = crate::Reg<doep5_int::DOEP5_INT_SPEC>;
1140#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1141pub mod doep5_int;
1142#[doc = "DOEP5_TSIZ register accessor: an alias for `Reg<DOEP5_TSIZ_SPEC>`"]
1143pub type DOEP5_TSIZ = crate::Reg<doep5_tsiz::DOEP5_TSIZ_SPEC>;
1144#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1145pub mod doep5_tsiz;
1146#[doc = "DOEP5_DMAADDR register accessor: an alias for `Reg<DOEP5_DMAADDR_SPEC>`"]
1147pub type DOEP5_DMAADDR = crate::Reg<doep5_dmaaddr::DOEP5_DMAADDR_SPEC>;
1148#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1149pub mod doep5_dmaaddr;
1150#[doc = "PCGCCTL register accessor: an alias for `Reg<PCGCCTL_SPEC>`"]
1151pub type PCGCCTL = crate::Reg<pcgcctl::PCGCCTL_SPEC>;
1152#[doc = "Power and Clock Gating Control Register"]
1153pub mod pcgcctl;