efm32wg360_pac/dma/
ch0_ctrl.rs1#[doc = "Register `CH0_CTRL` reader"]
2pub struct R(crate::R<CH0_CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CH0_CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CH0_CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CH0_CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CH0_CTRL` writer"]
17pub struct W(crate::W<CH0_CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CH0_CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CH0_CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CH0_CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH0_CTRL_SPEC, u8, u8, 4, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45 #[doc = "0: No source selected"]
46 NONE = 0,
47 #[doc = "8: Analog to Digital Converter 0"]
48 ADC0 = 8,
49 #[doc = "10: Digital to Analog Converter 0"]
50 DAC0 = 10,
51 #[doc = "12: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
52 USART0 = 12,
53 #[doc = "13: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
54 USART1 = 13,
55 #[doc = "14: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
56 USART2 = 14,
57 #[doc = "16: Low Energy UART 0"]
58 LEUART0 = 16,
59 #[doc = "17: Low Energy UART 1"]
60 LEUART1 = 17,
61 #[doc = "20: I2C 0"]
62 I2C0 = 20,
63 #[doc = "21: I2C 1"]
64 I2C1 = 21,
65 #[doc = "24: Timer 0"]
66 TIMER0 = 24,
67 #[doc = "25: Timer 1"]
68 TIMER1 = 25,
69 #[doc = "26: Timer 2"]
70 TIMER2 = 26,
71 #[doc = "27: Timer 3"]
72 TIMER3 = 27,
73 #[doc = "44: Universal Asynchronous Receiver/Transmitter 0"]
74 UART0 = 44,
75 #[doc = "45: Universal Asynchronous Receiver/Transmitter 1"]
76 UART1 = 45,
77 #[doc = "48: `110000`"]
78 MSC = 48,
79 #[doc = "49: Advanced Encryption Standard Accelerator"]
80 AES = 49,
81 #[doc = "50: Low Energy Sensor Interface"]
82 LESENSE = 50,
83}
84impl From<SOURCESEL_A> for u8 {
85 #[inline(always)]
86 fn from(variant: SOURCESEL_A) -> Self {
87 variant as _
88 }
89}
90#[doc = "Field `SOURCESEL` reader - Source Select"]
91pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
92impl SOURCESEL_R {
93 #[doc = "Get enumerated values variant"]
94 #[inline(always)]
95 pub fn variant(&self) -> Option<SOURCESEL_A> {
96 match self.bits {
97 0 => Some(SOURCESEL_A::NONE),
98 8 => Some(SOURCESEL_A::ADC0),
99 10 => Some(SOURCESEL_A::DAC0),
100 12 => Some(SOURCESEL_A::USART0),
101 13 => Some(SOURCESEL_A::USART1),
102 14 => Some(SOURCESEL_A::USART2),
103 16 => Some(SOURCESEL_A::LEUART0),
104 17 => Some(SOURCESEL_A::LEUART1),
105 20 => Some(SOURCESEL_A::I2C0),
106 21 => Some(SOURCESEL_A::I2C1),
107 24 => Some(SOURCESEL_A::TIMER0),
108 25 => Some(SOURCESEL_A::TIMER1),
109 26 => Some(SOURCESEL_A::TIMER2),
110 27 => Some(SOURCESEL_A::TIMER3),
111 44 => Some(SOURCESEL_A::UART0),
112 45 => Some(SOURCESEL_A::UART1),
113 48 => Some(SOURCESEL_A::MSC),
114 49 => Some(SOURCESEL_A::AES),
115 50 => Some(SOURCESEL_A::LESENSE),
116 _ => None,
117 }
118 }
119 #[doc = "Checks if the value of the field is `NONE`"]
120 #[inline(always)]
121 pub fn is_none(&self) -> bool {
122 *self == SOURCESEL_A::NONE
123 }
124 #[doc = "Checks if the value of the field is `ADC0`"]
125 #[inline(always)]
126 pub fn is_adc0(&self) -> bool {
127 *self == SOURCESEL_A::ADC0
128 }
129 #[doc = "Checks if the value of the field is `DAC0`"]
130 #[inline(always)]
131 pub fn is_dac0(&self) -> bool {
132 *self == SOURCESEL_A::DAC0
133 }
134 #[doc = "Checks if the value of the field is `USART0`"]
135 #[inline(always)]
136 pub fn is_usart0(&self) -> bool {
137 *self == SOURCESEL_A::USART0
138 }
139 #[doc = "Checks if the value of the field is `USART1`"]
140 #[inline(always)]
141 pub fn is_usart1(&self) -> bool {
142 *self == SOURCESEL_A::USART1
143 }
144 #[doc = "Checks if the value of the field is `USART2`"]
145 #[inline(always)]
146 pub fn is_usart2(&self) -> bool {
147 *self == SOURCESEL_A::USART2
148 }
149 #[doc = "Checks if the value of the field is `LEUART0`"]
150 #[inline(always)]
151 pub fn is_leuart0(&self) -> bool {
152 *self == SOURCESEL_A::LEUART0
153 }
154 #[doc = "Checks if the value of the field is `LEUART1`"]
155 #[inline(always)]
156 pub fn is_leuart1(&self) -> bool {
157 *self == SOURCESEL_A::LEUART1
158 }
159 #[doc = "Checks if the value of the field is `I2C0`"]
160 #[inline(always)]
161 pub fn is_i2c0(&self) -> bool {
162 *self == SOURCESEL_A::I2C0
163 }
164 #[doc = "Checks if the value of the field is `I2C1`"]
165 #[inline(always)]
166 pub fn is_i2c1(&self) -> bool {
167 *self == SOURCESEL_A::I2C1
168 }
169 #[doc = "Checks if the value of the field is `TIMER0`"]
170 #[inline(always)]
171 pub fn is_timer0(&self) -> bool {
172 *self == SOURCESEL_A::TIMER0
173 }
174 #[doc = "Checks if the value of the field is `TIMER1`"]
175 #[inline(always)]
176 pub fn is_timer1(&self) -> bool {
177 *self == SOURCESEL_A::TIMER1
178 }
179 #[doc = "Checks if the value of the field is `TIMER2`"]
180 #[inline(always)]
181 pub fn is_timer2(&self) -> bool {
182 *self == SOURCESEL_A::TIMER2
183 }
184 #[doc = "Checks if the value of the field is `TIMER3`"]
185 #[inline(always)]
186 pub fn is_timer3(&self) -> bool {
187 *self == SOURCESEL_A::TIMER3
188 }
189 #[doc = "Checks if the value of the field is `UART0`"]
190 #[inline(always)]
191 pub fn is_uart0(&self) -> bool {
192 *self == SOURCESEL_A::UART0
193 }
194 #[doc = "Checks if the value of the field is `UART1`"]
195 #[inline(always)]
196 pub fn is_uart1(&self) -> bool {
197 *self == SOURCESEL_A::UART1
198 }
199 #[doc = "Checks if the value of the field is `MSC`"]
200 #[inline(always)]
201 pub fn is_msc(&self) -> bool {
202 *self == SOURCESEL_A::MSC
203 }
204 #[doc = "Checks if the value of the field is `AES`"]
205 #[inline(always)]
206 pub fn is_aes(&self) -> bool {
207 *self == SOURCESEL_A::AES
208 }
209 #[doc = "Checks if the value of the field is `LESENSE`"]
210 #[inline(always)]
211 pub fn is_lesense(&self) -> bool {
212 *self == SOURCESEL_A::LESENSE
213 }
214}
215#[doc = "Field `SOURCESEL` writer - Source Select"]
216pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH0_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
217impl<'a> SOURCESEL_W<'a> {
218 #[doc = "No source selected"]
219 #[inline(always)]
220 pub fn none(self) -> &'a mut W {
221 self.variant(SOURCESEL_A::NONE)
222 }
223 #[doc = "Analog to Digital Converter 0"]
224 #[inline(always)]
225 pub fn adc0(self) -> &'a mut W {
226 self.variant(SOURCESEL_A::ADC0)
227 }
228 #[doc = "Digital to Analog Converter 0"]
229 #[inline(always)]
230 pub fn dac0(self) -> &'a mut W {
231 self.variant(SOURCESEL_A::DAC0)
232 }
233 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
234 #[inline(always)]
235 pub fn usart0(self) -> &'a mut W {
236 self.variant(SOURCESEL_A::USART0)
237 }
238 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
239 #[inline(always)]
240 pub fn usart1(self) -> &'a mut W {
241 self.variant(SOURCESEL_A::USART1)
242 }
243 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
244 #[inline(always)]
245 pub fn usart2(self) -> &'a mut W {
246 self.variant(SOURCESEL_A::USART2)
247 }
248 #[doc = "Low Energy UART 0"]
249 #[inline(always)]
250 pub fn leuart0(self) -> &'a mut W {
251 self.variant(SOURCESEL_A::LEUART0)
252 }
253 #[doc = "Low Energy UART 1"]
254 #[inline(always)]
255 pub fn leuart1(self) -> &'a mut W {
256 self.variant(SOURCESEL_A::LEUART1)
257 }
258 #[doc = "I2C 0"]
259 #[inline(always)]
260 pub fn i2c0(self) -> &'a mut W {
261 self.variant(SOURCESEL_A::I2C0)
262 }
263 #[doc = "I2C 1"]
264 #[inline(always)]
265 pub fn i2c1(self) -> &'a mut W {
266 self.variant(SOURCESEL_A::I2C1)
267 }
268 #[doc = "Timer 0"]
269 #[inline(always)]
270 pub fn timer0(self) -> &'a mut W {
271 self.variant(SOURCESEL_A::TIMER0)
272 }
273 #[doc = "Timer 1"]
274 #[inline(always)]
275 pub fn timer1(self) -> &'a mut W {
276 self.variant(SOURCESEL_A::TIMER1)
277 }
278 #[doc = "Timer 2"]
279 #[inline(always)]
280 pub fn timer2(self) -> &'a mut W {
281 self.variant(SOURCESEL_A::TIMER2)
282 }
283 #[doc = "Timer 3"]
284 #[inline(always)]
285 pub fn timer3(self) -> &'a mut W {
286 self.variant(SOURCESEL_A::TIMER3)
287 }
288 #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
289 #[inline(always)]
290 pub fn uart0(self) -> &'a mut W {
291 self.variant(SOURCESEL_A::UART0)
292 }
293 #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
294 #[inline(always)]
295 pub fn uart1(self) -> &'a mut W {
296 self.variant(SOURCESEL_A::UART1)
297 }
298 #[doc = "`110000`"]
299 #[inline(always)]
300 pub fn msc(self) -> &'a mut W {
301 self.variant(SOURCESEL_A::MSC)
302 }
303 #[doc = "Advanced Encryption Standard Accelerator"]
304 #[inline(always)]
305 pub fn aes(self) -> &'a mut W {
306 self.variant(SOURCESEL_A::AES)
307 }
308 #[doc = "Low Energy Sensor Interface"]
309 #[inline(always)]
310 pub fn lesense(self) -> &'a mut W {
311 self.variant(SOURCESEL_A::LESENSE)
312 }
313}
314impl R {
315 #[doc = "Bits 0:3 - Signal Select"]
316 #[inline(always)]
317 pub fn sigsel(&self) -> SIGSEL_R {
318 SIGSEL_R::new((self.bits & 0x0f) as u8)
319 }
320 #[doc = "Bits 16:21 - Source Select"]
321 #[inline(always)]
322 pub fn sourcesel(&self) -> SOURCESEL_R {
323 SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
324 }
325}
326impl W {
327 #[doc = "Bits 0:3 - Signal Select"]
328 #[inline(always)]
329 pub fn sigsel(&mut self) -> SIGSEL_W {
330 SIGSEL_W::new(self)
331 }
332 #[doc = "Bits 16:21 - Source Select"]
333 #[inline(always)]
334 pub fn sourcesel(&mut self) -> SOURCESEL_W {
335 SOURCESEL_W::new(self)
336 }
337 #[doc = "Writes raw bits to the register."]
338 #[inline(always)]
339 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
340 self.0.bits(bits);
341 self
342 }
343}
344#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch0_ctrl](index.html) module"]
345pub struct CH0_CTRL_SPEC;
346impl crate::RegisterSpec for CH0_CTRL_SPEC {
347 type Ux = u32;
348}
349#[doc = "`read()` method returns [ch0_ctrl::R](R) reader structure"]
350impl crate::Readable for CH0_CTRL_SPEC {
351 type Reader = R;
352}
353#[doc = "`write(|w| ..)` method takes [ch0_ctrl::W](W) writer structure"]
354impl crate::Writable for CH0_CTRL_SPEC {
355 type Writer = W;
356}
357#[doc = "`reset()` method sets CH0_CTRL to value 0"]
358impl crate::Resettable for CH0_CTRL_SPEC {
359 #[inline(always)]
360 fn reset_value() -> Self::Ux {
361 0
362 }
363}