efm32tg840_pac/dma/
ch1_ctrl.rs

1#[doc = "Register `CH1_CTRL` reader"]
2pub struct R(crate::R<CH1_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH1_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH1_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH1_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH1_CTRL` writer"]
17pub struct W(crate::W<CH1_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH1_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH1_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH1_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH1_CTRL_SPEC, u8, u8, 4, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "8: Analog to Digital Converter 0"]
48    ADC0 = 8,
49    #[doc = "10: Digital to Analog Converter 0"]
50    DAC0 = 10,
51    #[doc = "12: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
52    USART0 = 12,
53    #[doc = "13: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
54    USART1 = 13,
55    #[doc = "16: Low Energy UART 0"]
56    LEUART0 = 16,
57    #[doc = "20: I2C 0"]
58    I2C0 = 20,
59    #[doc = "24: Timer 0"]
60    TIMER0 = 24,
61    #[doc = "25: Timer 1"]
62    TIMER1 = 25,
63    #[doc = "48: `110000`"]
64    MSC = 48,
65    #[doc = "49: Advanced Encryption Standard Accelerator"]
66    AES = 49,
67    #[doc = "50: Low Energy Sensor Interface"]
68    LESENSE = 50,
69}
70impl From<SOURCESEL_A> for u8 {
71    #[inline(always)]
72    fn from(variant: SOURCESEL_A) -> Self {
73        variant as _
74    }
75}
76#[doc = "Field `SOURCESEL` reader - Source Select"]
77pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
78impl SOURCESEL_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub fn variant(&self) -> Option<SOURCESEL_A> {
82        match self.bits {
83            0 => Some(SOURCESEL_A::NONE),
84            8 => Some(SOURCESEL_A::ADC0),
85            10 => Some(SOURCESEL_A::DAC0),
86            12 => Some(SOURCESEL_A::USART0),
87            13 => Some(SOURCESEL_A::USART1),
88            16 => Some(SOURCESEL_A::LEUART0),
89            20 => Some(SOURCESEL_A::I2C0),
90            24 => Some(SOURCESEL_A::TIMER0),
91            25 => Some(SOURCESEL_A::TIMER1),
92            48 => Some(SOURCESEL_A::MSC),
93            49 => Some(SOURCESEL_A::AES),
94            50 => Some(SOURCESEL_A::LESENSE),
95            _ => None,
96        }
97    }
98    #[doc = "Checks if the value of the field is `NONE`"]
99    #[inline(always)]
100    pub fn is_none(&self) -> bool {
101        *self == SOURCESEL_A::NONE
102    }
103    #[doc = "Checks if the value of the field is `ADC0`"]
104    #[inline(always)]
105    pub fn is_adc0(&self) -> bool {
106        *self == SOURCESEL_A::ADC0
107    }
108    #[doc = "Checks if the value of the field is `DAC0`"]
109    #[inline(always)]
110    pub fn is_dac0(&self) -> bool {
111        *self == SOURCESEL_A::DAC0
112    }
113    #[doc = "Checks if the value of the field is `USART0`"]
114    #[inline(always)]
115    pub fn is_usart0(&self) -> bool {
116        *self == SOURCESEL_A::USART0
117    }
118    #[doc = "Checks if the value of the field is `USART1`"]
119    #[inline(always)]
120    pub fn is_usart1(&self) -> bool {
121        *self == SOURCESEL_A::USART1
122    }
123    #[doc = "Checks if the value of the field is `LEUART0`"]
124    #[inline(always)]
125    pub fn is_leuart0(&self) -> bool {
126        *self == SOURCESEL_A::LEUART0
127    }
128    #[doc = "Checks if the value of the field is `I2C0`"]
129    #[inline(always)]
130    pub fn is_i2c0(&self) -> bool {
131        *self == SOURCESEL_A::I2C0
132    }
133    #[doc = "Checks if the value of the field is `TIMER0`"]
134    #[inline(always)]
135    pub fn is_timer0(&self) -> bool {
136        *self == SOURCESEL_A::TIMER0
137    }
138    #[doc = "Checks if the value of the field is `TIMER1`"]
139    #[inline(always)]
140    pub fn is_timer1(&self) -> bool {
141        *self == SOURCESEL_A::TIMER1
142    }
143    #[doc = "Checks if the value of the field is `MSC`"]
144    #[inline(always)]
145    pub fn is_msc(&self) -> bool {
146        *self == SOURCESEL_A::MSC
147    }
148    #[doc = "Checks if the value of the field is `AES`"]
149    #[inline(always)]
150    pub fn is_aes(&self) -> bool {
151        *self == SOURCESEL_A::AES
152    }
153    #[doc = "Checks if the value of the field is `LESENSE`"]
154    #[inline(always)]
155    pub fn is_lesense(&self) -> bool {
156        *self == SOURCESEL_A::LESENSE
157    }
158}
159#[doc = "Field `SOURCESEL` writer - Source Select"]
160pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH1_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
161impl<'a> SOURCESEL_W<'a> {
162    #[doc = "No source selected"]
163    #[inline(always)]
164    pub fn none(self) -> &'a mut W {
165        self.variant(SOURCESEL_A::NONE)
166    }
167    #[doc = "Analog to Digital Converter 0"]
168    #[inline(always)]
169    pub fn adc0(self) -> &'a mut W {
170        self.variant(SOURCESEL_A::ADC0)
171    }
172    #[doc = "Digital to Analog Converter 0"]
173    #[inline(always)]
174    pub fn dac0(self) -> &'a mut W {
175        self.variant(SOURCESEL_A::DAC0)
176    }
177    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
178    #[inline(always)]
179    pub fn usart0(self) -> &'a mut W {
180        self.variant(SOURCESEL_A::USART0)
181    }
182    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
183    #[inline(always)]
184    pub fn usart1(self) -> &'a mut W {
185        self.variant(SOURCESEL_A::USART1)
186    }
187    #[doc = "Low Energy UART 0"]
188    #[inline(always)]
189    pub fn leuart0(self) -> &'a mut W {
190        self.variant(SOURCESEL_A::LEUART0)
191    }
192    #[doc = "I2C 0"]
193    #[inline(always)]
194    pub fn i2c0(self) -> &'a mut W {
195        self.variant(SOURCESEL_A::I2C0)
196    }
197    #[doc = "Timer 0"]
198    #[inline(always)]
199    pub fn timer0(self) -> &'a mut W {
200        self.variant(SOURCESEL_A::TIMER0)
201    }
202    #[doc = "Timer 1"]
203    #[inline(always)]
204    pub fn timer1(self) -> &'a mut W {
205        self.variant(SOURCESEL_A::TIMER1)
206    }
207    #[doc = "`110000`"]
208    #[inline(always)]
209    pub fn msc(self) -> &'a mut W {
210        self.variant(SOURCESEL_A::MSC)
211    }
212    #[doc = "Advanced Encryption Standard Accelerator"]
213    #[inline(always)]
214    pub fn aes(self) -> &'a mut W {
215        self.variant(SOURCESEL_A::AES)
216    }
217    #[doc = "Low Energy Sensor Interface"]
218    #[inline(always)]
219    pub fn lesense(self) -> &'a mut W {
220        self.variant(SOURCESEL_A::LESENSE)
221    }
222}
223impl R {
224    #[doc = "Bits 0:3 - Signal Select"]
225    #[inline(always)]
226    pub fn sigsel(&self) -> SIGSEL_R {
227        SIGSEL_R::new((self.bits & 0x0f) as u8)
228    }
229    #[doc = "Bits 16:21 - Source Select"]
230    #[inline(always)]
231    pub fn sourcesel(&self) -> SOURCESEL_R {
232        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
233    }
234}
235impl W {
236    #[doc = "Bits 0:3 - Signal Select"]
237    #[inline(always)]
238    pub fn sigsel(&mut self) -> SIGSEL_W {
239        SIGSEL_W::new(self)
240    }
241    #[doc = "Bits 16:21 - Source Select"]
242    #[inline(always)]
243    pub fn sourcesel(&mut self) -> SOURCESEL_W {
244        SOURCESEL_W::new(self)
245    }
246    #[doc = "Writes raw bits to the register."]
247    #[inline(always)]
248    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
249        self.0.bits(bits);
250        self
251    }
252}
253#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch1_ctrl](index.html) module"]
254pub struct CH1_CTRL_SPEC;
255impl crate::RegisterSpec for CH1_CTRL_SPEC {
256    type Ux = u32;
257}
258#[doc = "`read()` method returns [ch1_ctrl::R](R) reader structure"]
259impl crate::Readable for CH1_CTRL_SPEC {
260    type Reader = R;
261}
262#[doc = "`write(|w| ..)` method takes [ch1_ctrl::W](W) writer structure"]
263impl crate::Writable for CH1_CTRL_SPEC {
264    type Writer = W;
265}
266#[doc = "`reset()` method sets CH1_CTRL to value 0"]
267impl crate::Resettable for CH1_CTRL_SPEC {
268    #[inline(always)]
269    fn reset_value() -> Self::Ux {
270        0
271    }
272}
efm32tg840_pac/dma/ch1_ctrl.rs

efm32tg840_pac/dma/
ch1_ctrl.rs
