efm32tg11b140_pac/cmu/
hfperclken1.rs

1#[doc = "Register `HFPERCLKEN1` reader"]
2pub struct R(crate::R<HFPERCLKEN1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFPERCLKEN1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFPERCLKEN1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFPERCLKEN1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFPERCLKEN1` writer"]
17pub struct W(crate::W<HFPERCLKEN1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFPERCLKEN1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFPERCLKEN1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFPERCLKEN1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `UART0` reader - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
38pub type UART0_R = crate::BitReader<bool>;
39#[doc = "Field `UART0` writer - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
40pub type UART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 0>;
41#[doc = "Field `WTIMER0` reader - Wide Timer 0 Clock Enable"]
42pub type WTIMER0_R = crate::BitReader<bool>;
43#[doc = "Field `WTIMER0` writer - Wide Timer 0 Clock Enable"]
44pub type WTIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 1>;
45#[doc = "Field `WTIMER1` reader - Wide Timer 1 Clock Enable"]
46pub type WTIMER1_R = crate::BitReader<bool>;
47#[doc = "Field `WTIMER1` writer - Wide Timer 1 Clock Enable"]
48pub type WTIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 2>;
49#[doc = "Field `CAN0` reader - CAN 0 Clock Enable"]
50pub type CAN0_R = crate::BitReader<bool>;
51#[doc = "Field `CAN0` writer - CAN 0 Clock Enable"]
52pub type CAN0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 3>;
53#[doc = "Field `VDAC0` reader - Digital to Analog Converter 0 Clock Enable"]
54pub type VDAC0_R = crate::BitReader<bool>;
55#[doc = "Field `VDAC0` writer - Digital to Analog Converter 0 Clock Enable"]
56pub type VDAC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 4>;
57#[doc = "Field `CSEN` reader - Capacitive touch sense module Clock Enable"]
58pub type CSEN_R = crate::BitReader<bool>;
59#[doc = "Field `CSEN` writer - Capacitive touch sense module Clock Enable"]
60pub type CSEN_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 5>;
61impl R {
62    #[doc = "Bit 0 - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
63    #[inline(always)]
64    pub fn uart0(&self) -> UART0_R {
65        UART0_R::new((self.bits & 1) != 0)
66    }
67    #[doc = "Bit 1 - Wide Timer 0 Clock Enable"]
68    #[inline(always)]
69    pub fn wtimer0(&self) -> WTIMER0_R {
70        WTIMER0_R::new(((self.bits >> 1) & 1) != 0)
71    }
72    #[doc = "Bit 2 - Wide Timer 1 Clock Enable"]
73    #[inline(always)]
74    pub fn wtimer1(&self) -> WTIMER1_R {
75        WTIMER1_R::new(((self.bits >> 2) & 1) != 0)
76    }
77    #[doc = "Bit 3 - CAN 0 Clock Enable"]
78    #[inline(always)]
79    pub fn can0(&self) -> CAN0_R {
80        CAN0_R::new(((self.bits >> 3) & 1) != 0)
81    }
82    #[doc = "Bit 4 - Digital to Analog Converter 0 Clock Enable"]
83    #[inline(always)]
84    pub fn vdac0(&self) -> VDAC0_R {
85        VDAC0_R::new(((self.bits >> 4) & 1) != 0)
86    }
87    #[doc = "Bit 5 - Capacitive touch sense module Clock Enable"]
88    #[inline(always)]
89    pub fn csen(&self) -> CSEN_R {
90        CSEN_R::new(((self.bits >> 5) & 1) != 0)
91    }
92}
93impl W {
94    #[doc = "Bit 0 - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
95    #[inline(always)]
96    pub fn uart0(&mut self) -> UART0_W {
97        UART0_W::new(self)
98    }
99    #[doc = "Bit 1 - Wide Timer 0 Clock Enable"]
100    #[inline(always)]
101    pub fn wtimer0(&mut self) -> WTIMER0_W {
102        WTIMER0_W::new(self)
103    }
104    #[doc = "Bit 2 - Wide Timer 1 Clock Enable"]
105    #[inline(always)]
106    pub fn wtimer1(&mut self) -> WTIMER1_W {
107        WTIMER1_W::new(self)
108    }
109    #[doc = "Bit 3 - CAN 0 Clock Enable"]
110    #[inline(always)]
111    pub fn can0(&mut self) -> CAN0_W {
112        CAN0_W::new(self)
113    }
114    #[doc = "Bit 4 - Digital to Analog Converter 0 Clock Enable"]
115    #[inline(always)]
116    pub fn vdac0(&mut self) -> VDAC0_W {
117        VDAC0_W::new(self)
118    }
119    #[doc = "Bit 5 - Capacitive touch sense module Clock Enable"]
120    #[inline(always)]
121    pub fn csen(&mut self) -> CSEN_W {
122        CSEN_W::new(self)
123    }
124    #[doc = "Writes raw bits to the register."]
125    #[inline(always)]
126    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
127        self.0.bits(bits);
128        self
129    }
130}
131#[doc = "High Frequency Peripheral Clock Enable Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken1](index.html) module"]
132pub struct HFPERCLKEN1_SPEC;
133impl crate::RegisterSpec for HFPERCLKEN1_SPEC {
134    type Ux = u32;
135}
136#[doc = "`read()` method returns [hfperclken1::R](R) reader structure"]
137impl crate::Readable for HFPERCLKEN1_SPEC {
138    type Reader = R;
139}
140#[doc = "`write(|w| ..)` method takes [hfperclken1::W](W) writer structure"]
141impl crate::Writable for HFPERCLKEN1_SPEC {
142    type Writer = W;
143}
144#[doc = "`reset()` method sets HFPERCLKEN1 to value 0"]
145impl crate::Resettable for HFPERCLKEN1_SPEC {
146    #[inline(always)]
147    fn reset_value() -> Self::Ux {
148        0
149    }
150}
efm32tg11b140_pac/cmu/hfperclken1.rs

efm32tg11b140_pac/cmu/
hfperclken1.rs
