efm32tg11b120_pac/usart1/
status.rs

1#[doc = "Register `STATUS` reader"]
2pub struct R(crate::R<STATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<STATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<STATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<STATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `RXENS` reader - Receiver Enable Status"]
17pub type RXENS_R = crate::BitReader<bool>;
18#[doc = "Field `TXENS` reader - Transmitter Enable Status"]
19pub type TXENS_R = crate::BitReader<bool>;
20#[doc = "Field `MASTER` reader - SPI Master Mode"]
21pub type MASTER_R = crate::BitReader<bool>;
22#[doc = "Field `RXBLOCK` reader - Block Incoming Data"]
23pub type RXBLOCK_R = crate::BitReader<bool>;
24#[doc = "Field `TXTRI` reader - Transmitter Tristated"]
25pub type TXTRI_R = crate::BitReader<bool>;
26#[doc = "Field `TXC` reader - TX Complete"]
27pub type TXC_R = crate::BitReader<bool>;
28#[doc = "Field `TXBL` reader - TX Buffer Level"]
29pub type TXBL_R = crate::BitReader<bool>;
30#[doc = "Field `RXDATAV` reader - RX Data Valid"]
31pub type RXDATAV_R = crate::BitReader<bool>;
32#[doc = "Field `RXFULL` reader - RX FIFO Full"]
33pub type RXFULL_R = crate::BitReader<bool>;
34#[doc = "Field `TXBDRIGHT` reader - TX Buffer Expects Double Right Data"]
35pub type TXBDRIGHT_R = crate::BitReader<bool>;
36#[doc = "Field `TXBSRIGHT` reader - TX Buffer Expects Single Right Data"]
37pub type TXBSRIGHT_R = crate::BitReader<bool>;
38#[doc = "Field `RXDATAVRIGHT` reader - RX Data Right"]
39pub type RXDATAVRIGHT_R = crate::BitReader<bool>;
40#[doc = "Field `RXFULLRIGHT` reader - RX Full of Right Data"]
41pub type RXFULLRIGHT_R = crate::BitReader<bool>;
42#[doc = "Field `TXIDLE` reader - TX Idle"]
43pub type TXIDLE_R = crate::BitReader<bool>;
44#[doc = "Field `TIMERRESTARTED` reader - The USART Timer Restarted Itself"]
45pub type TIMERRESTARTED_R = crate::BitReader<bool>;
46#[doc = "Field `TXBUFCNT` reader - TX Buffer Count"]
47pub type TXBUFCNT_R = crate::FieldReader<u8, u8>;
48impl R {
49    #[doc = "Bit 0 - Receiver Enable Status"]
50    #[inline(always)]
51    pub fn rxens(&self) -> RXENS_R {
52        RXENS_R::new((self.bits & 1) != 0)
53    }
54    #[doc = "Bit 1 - Transmitter Enable Status"]
55    #[inline(always)]
56    pub fn txens(&self) -> TXENS_R {
57        TXENS_R::new(((self.bits >> 1) & 1) != 0)
58    }
59    #[doc = "Bit 2 - SPI Master Mode"]
60    #[inline(always)]
61    pub fn master(&self) -> MASTER_R {
62        MASTER_R::new(((self.bits >> 2) & 1) != 0)
63    }
64    #[doc = "Bit 3 - Block Incoming Data"]
65    #[inline(always)]
66    pub fn rxblock(&self) -> RXBLOCK_R {
67        RXBLOCK_R::new(((self.bits >> 3) & 1) != 0)
68    }
69    #[doc = "Bit 4 - Transmitter Tristated"]
70    #[inline(always)]
71    pub fn txtri(&self) -> TXTRI_R {
72        TXTRI_R::new(((self.bits >> 4) & 1) != 0)
73    }
74    #[doc = "Bit 5 - TX Complete"]
75    #[inline(always)]
76    pub fn txc(&self) -> TXC_R {
77        TXC_R::new(((self.bits >> 5) & 1) != 0)
78    }
79    #[doc = "Bit 6 - TX Buffer Level"]
80    #[inline(always)]
81    pub fn txbl(&self) -> TXBL_R {
82        TXBL_R::new(((self.bits >> 6) & 1) != 0)
83    }
84    #[doc = "Bit 7 - RX Data Valid"]
85    #[inline(always)]
86    pub fn rxdatav(&self) -> RXDATAV_R {
87        RXDATAV_R::new(((self.bits >> 7) & 1) != 0)
88    }
89    #[doc = "Bit 8 - RX FIFO Full"]
90    #[inline(always)]
91    pub fn rxfull(&self) -> RXFULL_R {
92        RXFULL_R::new(((self.bits >> 8) & 1) != 0)
93    }
94    #[doc = "Bit 9 - TX Buffer Expects Double Right Data"]
95    #[inline(always)]
96    pub fn txbdright(&self) -> TXBDRIGHT_R {
97        TXBDRIGHT_R::new(((self.bits >> 9) & 1) != 0)
98    }
99    #[doc = "Bit 10 - TX Buffer Expects Single Right Data"]
100    #[inline(always)]
101    pub fn txbsright(&self) -> TXBSRIGHT_R {
102        TXBSRIGHT_R::new(((self.bits >> 10) & 1) != 0)
103    }
104    #[doc = "Bit 11 - RX Data Right"]
105    #[inline(always)]
106    pub fn rxdatavright(&self) -> RXDATAVRIGHT_R {
107        RXDATAVRIGHT_R::new(((self.bits >> 11) & 1) != 0)
108    }
109    #[doc = "Bit 12 - RX Full of Right Data"]
110    #[inline(always)]
111    pub fn rxfullright(&self) -> RXFULLRIGHT_R {
112        RXFULLRIGHT_R::new(((self.bits >> 12) & 1) != 0)
113    }
114    #[doc = "Bit 13 - TX Idle"]
115    #[inline(always)]
116    pub fn txidle(&self) -> TXIDLE_R {
117        TXIDLE_R::new(((self.bits >> 13) & 1) != 0)
118    }
119    #[doc = "Bit 14 - The USART Timer Restarted Itself"]
120    #[inline(always)]
121    pub fn timerrestarted(&self) -> TIMERRESTARTED_R {
122        TIMERRESTARTED_R::new(((self.bits >> 14) & 1) != 0)
123    }
124    #[doc = "Bits 16:17 - TX Buffer Count"]
125    #[inline(always)]
126    pub fn txbufcnt(&self) -> TXBUFCNT_R {
127        TXBUFCNT_R::new(((self.bits >> 16) & 3) as u8)
128    }
129}
130#[doc = "USART Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
131pub struct STATUS_SPEC;
132impl crate::RegisterSpec for STATUS_SPEC {
133    type Ux = u32;
134}
135#[doc = "`read()` method returns [status::R](R) reader structure"]
136impl crate::Readable for STATUS_SPEC {
137    type Reader = R;
138}
139#[doc = "`reset()` method sets STATUS to value 0x2040"]
140impl crate::Resettable for STATUS_SPEC {
141    #[inline(always)]
142    fn reset_value() -> Self::Ux {
143        0x2040
144    }
145}
efm32tg11b120_pac/usart1/status.rs

efm32tg11b120_pac/usart1/
status.rs
