efm32pg1b_pac/letimer0/
ien.rs

1///Register `IEN` reader
2pub type R = crate::R<IENrs>;
3///Register `IEN` writer
4pub type W = crate::W<IENrs>;
5///Field `COMP0` reader - COMP0 Interrupt Enable
6pub type Comp0R = crate::BitReader;
7///Field `COMP0` writer - COMP0 Interrupt Enable
8pub type Comp0W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `COMP1` reader - COMP1 Interrupt Enable
10pub type Comp1R = crate::BitReader;
11///Field `COMP1` writer - COMP1 Interrupt Enable
12pub type Comp1W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `UF` reader - UF Interrupt Enable
14pub type UfR = crate::BitReader;
15///Field `UF` writer - UF Interrupt Enable
16pub type UfW<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `REP0` reader - REP0 Interrupt Enable
18pub type Rep0R = crate::BitReader;
19///Field `REP0` writer - REP0 Interrupt Enable
20pub type Rep0W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `REP1` reader - REP1 Interrupt Enable
22pub type Rep1R = crate::BitReader;
23///Field `REP1` writer - REP1 Interrupt Enable
24pub type Rep1W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    ///Bit 0 - COMP0 Interrupt Enable
27    #[inline(always)]
28    pub fn comp0(&self) -> Comp0R {
29        Comp0R::new((self.bits & 1) != 0)
30    }
31    ///Bit 1 - COMP1 Interrupt Enable
32    #[inline(always)]
33    pub fn comp1(&self) -> Comp1R {
34        Comp1R::new(((self.bits >> 1) & 1) != 0)
35    }
36    ///Bit 2 - UF Interrupt Enable
37    #[inline(always)]
38    pub fn uf(&self) -> UfR {
39        UfR::new(((self.bits >> 2) & 1) != 0)
40    }
41    ///Bit 3 - REP0 Interrupt Enable
42    #[inline(always)]
43    pub fn rep0(&self) -> Rep0R {
44        Rep0R::new(((self.bits >> 3) & 1) != 0)
45    }
46    ///Bit 4 - REP1 Interrupt Enable
47    #[inline(always)]
48    pub fn rep1(&self) -> Rep1R {
49        Rep1R::new(((self.bits >> 4) & 1) != 0)
50    }
51}
52impl core::fmt::Debug for R {
53    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
54        f.debug_struct("IEN")
55            .field("comp0", &self.comp0())
56            .field("comp1", &self.comp1())
57            .field("uf", &self.uf())
58            .field("rep0", &self.rep0())
59            .field("rep1", &self.rep1())
60            .finish()
61    }
62}
63impl W {
64    ///Bit 0 - COMP0 Interrupt Enable
65    #[inline(always)]
66    pub fn comp0(&mut self) -> Comp0W<'_, IENrs> {
67        Comp0W::new(self, 0)
68    }
69    ///Bit 1 - COMP1 Interrupt Enable
70    #[inline(always)]
71    pub fn comp1(&mut self) -> Comp1W<'_, IENrs> {
72        Comp1W::new(self, 1)
73    }
74    ///Bit 2 - UF Interrupt Enable
75    #[inline(always)]
76    pub fn uf(&mut self) -> UfW<'_, IENrs> {
77        UfW::new(self, 2)
78    }
79    ///Bit 3 - REP0 Interrupt Enable
80    #[inline(always)]
81    pub fn rep0(&mut self) -> Rep0W<'_, IENrs> {
82        Rep0W::new(self, 3)
83    }
84    ///Bit 4 - REP1 Interrupt Enable
85    #[inline(always)]
86    pub fn rep1(&mut self) -> Rep1W<'_, IENrs> {
87        Rep1W::new(self, 4)
88    }
89}
90///Interrupt Enable Register
91///
92///You can [`read`](crate::Reg::read) this register and get [`ien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
93pub struct IENrs;
94impl crate::RegisterSpec for IENrs {
95    type Ux = u32;
96}
97///`read()` method returns [`ien::R`](R) reader structure
98impl crate::Readable for IENrs {}
99///`write(|w| ..)` method takes [`ien::W`](W) writer structure
100impl crate::Writable for IENrs {
101    type Safety = crate::Unsafe;
102}
103///`reset()` method sets IEN to value 0
104impl crate::Resettable for IENrs {}
efm32pg1b_pac/letimer0/ien.rs

efm32pg1b_pac/letimer0/
ien.rs
