efm32pg1b_pac/emu/
dcdclpctrl.rs

1///Register `DCDCLPCTRL` reader
2pub type R = crate::R<DCDCLPCTRLrs>;
3///Register `DCDCLPCTRL` writer
4pub type W = crate::W<DCDCLPCTRLrs>;
5///Field `LPCMPHYSSEL` reader - LP Mode Hysteresis Selection
6pub type LpcmphysselR = crate::FieldReader;
7///Field `LPCMPHYSSEL` writer - LP Mode Hysteresis Selection
8pub type LpcmphysselW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9///Field `LPVREFDUTYEN` reader - LP Mode Duty Cycling Enable
10pub type LpvrefdutyenR = crate::BitReader;
11///Field `LPVREFDUTYEN` writer - LP Mode Duty Cycling Enable
12pub type LpvrefdutyenW<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `LPBLANK` reader - Reserved for internal use. Do not change.
14pub type LpblankR = crate::FieldReader;
15///Field `LPBLANK` writer - Reserved for internal use. Do not change.
16pub type LpblankW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17impl R {
18    ///Bits 12:15 - LP Mode Hysteresis Selection
19    #[inline(always)]
20    pub fn lpcmphyssel(&self) -> LpcmphysselR {
21        LpcmphysselR::new(((self.bits >> 12) & 0x0f) as u8)
22    }
23    ///Bit 24 - LP Mode Duty Cycling Enable
24    #[inline(always)]
25    pub fn lpvrefdutyen(&self) -> LpvrefdutyenR {
26        LpvrefdutyenR::new(((self.bits >> 24) & 1) != 0)
27    }
28    ///Bits 25:26 - Reserved for internal use. Do not change.
29    #[inline(always)]
30    pub fn lpblank(&self) -> LpblankR {
31        LpblankR::new(((self.bits >> 25) & 3) as u8)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("DCDCLPCTRL")
37            .field("lpcmphyssel", &self.lpcmphyssel())
38            .field("lpvrefdutyen", &self.lpvrefdutyen())
39            .field("lpblank", &self.lpblank())
40            .finish()
41    }
42}
43impl W {
44    ///Bits 12:15 - LP Mode Hysteresis Selection
45    #[inline(always)]
46    pub fn lpcmphyssel(&mut self) -> LpcmphysselW<'_, DCDCLPCTRLrs> {
47        LpcmphysselW::new(self, 12)
48    }
49    ///Bit 24 - LP Mode Duty Cycling Enable
50    #[inline(always)]
51    pub fn lpvrefdutyen(&mut self) -> LpvrefdutyenW<'_, DCDCLPCTRLrs> {
52        LpvrefdutyenW::new(self, 24)
53    }
54    ///Bits 25:26 - Reserved for internal use. Do not change.
55    #[inline(always)]
56    pub fn lpblank(&mut self) -> LpblankW<'_, DCDCLPCTRLrs> {
57        LpblankW::new(self, 25)
58    }
59}
60///DCDC Low Power Control Register
61///
62///You can [`read`](crate::Reg::read) this register and get [`dcdclpctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcdclpctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63pub struct DCDCLPCTRLrs;
64impl crate::RegisterSpec for DCDCLPCTRLrs {
65    type Ux = u32;
66}
67///`read()` method returns [`dcdclpctrl::R`](R) reader structure
68impl crate::Readable for DCDCLPCTRLrs {}
69///`write(|w| ..)` method takes [`dcdclpctrl::W`](W) writer structure
70impl crate::Writable for DCDCLPCTRLrs {
71    type Safety = crate::Unsafe;
72}
73///`reset()` method sets DCDCLPCTRL to value 0x7000
74impl crate::Resettable for DCDCLPCTRLrs {
75    const RESET_VALUE: u32 = 0x7000;
76}
efm32pg1b_pac/emu/dcdclpctrl.rs

efm32pg1b_pac/emu/
dcdclpctrl.rs
