efm32pg1b_pac/adc0/
singlectrl.rs

1///Register `SINGLECTRL` reader
2pub type R = crate::R<SINGLECTRLrs>;
3///Register `SINGLECTRL` writer
4pub type W = crate::W<SINGLECTRLrs>;
5///Field `REP` reader - Single Channel Repetitive Mode
6pub type RepR = crate::BitReader;
7///Field `REP` writer - Single Channel Repetitive Mode
8pub type RepW<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DIFF` reader - Single Channel Differential Mode
10pub type DiffR = crate::BitReader;
11///Field `DIFF` writer - Single Channel Differential Mode
12pub type DiffW<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `ADJ` reader - Single Channel Result Adjustment
14pub type AdjR = crate::BitReader;
15///Field `ADJ` writer - Single Channel Result Adjustment
16pub type AdjW<'a, REG> = crate::BitWriter<'a, REG>;
17///Single Channel Resolution Select
18///
19///Value on reset: 0
20#[cfg_attr(feature = "defmt", derive(defmt::Format))]
21#[derive(Clone, Copy, Debug, PartialEq, Eq)]
22#[repr(u8)]
23pub enum RES {
24    ///0: 12-bit resolution.
25    _12bit = 0,
26    ///1: 8-bit resolution.
27    _8bit = 1,
28    ///2: 6-bit resolution.
29    _6bit = 2,
30    ///3: Oversampling enabled. Oversampling rate is set in OVSRSEL.
31    Ovs = 3,
32}
33impl From<RES> for u8 {
34    #[inline(always)]
35    fn from(variant: RES) -> Self {
36        variant as _
37    }
38}
39impl crate::FieldSpec for RES {
40    type Ux = u8;
41}
42impl crate::IsEnum for RES {}
43///Field `RES` reader - Single Channel Resolution Select
44pub type ResR = crate::FieldReader<RES>;
45impl ResR {
46    ///Get enumerated values variant
47    #[inline(always)]
48    pub const fn variant(&self) -> RES {
49        match self.bits {
50            0 => RES::_12bit,
51            1 => RES::_8bit,
52            2 => RES::_6bit,
53            3 => RES::Ovs,
54            _ => unreachable!(),
55        }
56    }
57    ///12-bit resolution.
58    #[inline(always)]
59    pub fn is_12bit(&self) -> bool {
60        *self == RES::_12bit
61    }
62    ///8-bit resolution.
63    #[inline(always)]
64    pub fn is_8bit(&self) -> bool {
65        *self == RES::_8bit
66    }
67    ///6-bit resolution.
68    #[inline(always)]
69    pub fn is_6bit(&self) -> bool {
70        *self == RES::_6bit
71    }
72    ///Oversampling enabled. Oversampling rate is set in OVSRSEL.
73    #[inline(always)]
74    pub fn is_ovs(&self) -> bool {
75        *self == RES::Ovs
76    }
77}
78///Field `RES` writer - Single Channel Resolution Select
79pub type ResW<'a, REG> = crate::FieldWriter<'a, REG, 2, RES, crate::Safe>;
80impl<'a, REG> ResW<'a, REG>
81where
82    REG: crate::Writable + crate::RegisterSpec,
83    REG::Ux: From<u8>,
84{
85    ///12-bit resolution.
86    #[inline(always)]
87    pub fn _12bit(self) -> &'a mut crate::W<REG> {
88        self.variant(RES::_12bit)
89    }
90    ///8-bit resolution.
91    #[inline(always)]
92    pub fn _8bit(self) -> &'a mut crate::W<REG> {
93        self.variant(RES::_8bit)
94    }
95    ///6-bit resolution.
96    #[inline(always)]
97    pub fn _6bit(self) -> &'a mut crate::W<REG> {
98        self.variant(RES::_6bit)
99    }
100    ///Oversampling enabled. Oversampling rate is set in OVSRSEL.
101    #[inline(always)]
102    pub fn ovs(self) -> &'a mut crate::W<REG> {
103        self.variant(RES::Ovs)
104    }
105}
106///Single Channel Reference Selection
107///
108///Value on reset: 0
109#[cfg_attr(feature = "defmt", derive(defmt::Format))]
110#[derive(Clone, Copy, Debug, PartialEq, Eq)]
111#[repr(u8)]
112pub enum REF {
113    ///0: VFS = 1.25V with internal VBGR reference
114    _1v25 = 0,
115    ///1: VFS = 2.5V with internal VBGR reference
116    _2v5 = 1,
117    ///2: VFS = AVDD with AVDD as reference source
118    Vdd = 2,
119    ///3: VFS = 5V with internal VBGR reference
120    _5v = 3,
121    ///4: Single ended external reference
122    Extsingle = 4,
123    ///5: Differential external reference, 2x
124    _2xextdiff = 5,
125    ///6: VFS = 2xAVDD with AVDD as the reference source
126    _2xvdd = 6,
127    ///7: Use SINGLECTRLX to configure reference
128    Conf = 7,
129}
130impl From<REF> for u8 {
131    #[inline(always)]
132    fn from(variant: REF) -> Self {
133        variant as _
134    }
135}
136impl crate::FieldSpec for REF {
137    type Ux = u8;
138}
139impl crate::IsEnum for REF {}
140///Field `REF` reader - Single Channel Reference Selection
141pub type RefR = crate::FieldReader<REF>;
142impl RefR {
143    ///Get enumerated values variant
144    #[inline(always)]
145    pub const fn variant(&self) -> REF {
146        match self.bits {
147            0 => REF::_1v25,
148            1 => REF::_2v5,
149            2 => REF::Vdd,
150            3 => REF::_5v,
151            4 => REF::Extsingle,
152            5 => REF::_2xextdiff,
153            6 => REF::_2xvdd,
154            7 => REF::Conf,
155            _ => unreachable!(),
156        }
157    }
158    ///VFS = 1.25V with internal VBGR reference
159    #[inline(always)]
160    pub fn is_1v25(&self) -> bool {
161        *self == REF::_1v25
162    }
163    ///VFS = 2.5V with internal VBGR reference
164    #[inline(always)]
165    pub fn is_2v5(&self) -> bool {
166        *self == REF::_2v5
167    }
168    ///VFS = AVDD with AVDD as reference source
169    #[inline(always)]
170    pub fn is_vdd(&self) -> bool {
171        *self == REF::Vdd
172    }
173    ///VFS = 5V with internal VBGR reference
174    #[inline(always)]
175    pub fn is_5v(&self) -> bool {
176        *self == REF::_5v
177    }
178    ///Single ended external reference
179    #[inline(always)]
180    pub fn is_extsingle(&self) -> bool {
181        *self == REF::Extsingle
182    }
183    ///Differential external reference, 2x
184    #[inline(always)]
185    pub fn is_2xextdiff(&self) -> bool {
186        *self == REF::_2xextdiff
187    }
188    ///VFS = 2xAVDD with AVDD as the reference source
189    #[inline(always)]
190    pub fn is_2xvdd(&self) -> bool {
191        *self == REF::_2xvdd
192    }
193    ///Use SINGLECTRLX to configure reference
194    #[inline(always)]
195    pub fn is_conf(&self) -> bool {
196        *self == REF::Conf
197    }
198}
199///Field `REF` writer - Single Channel Reference Selection
200pub type RefW<'a, REG> = crate::FieldWriter<'a, REG, 3, REF, crate::Safe>;
201impl<'a, REG> RefW<'a, REG>
202where
203    REG: crate::Writable + crate::RegisterSpec,
204    REG::Ux: From<u8>,
205{
206    ///VFS = 1.25V with internal VBGR reference
207    #[inline(always)]
208    pub fn _1v25(self) -> &'a mut crate::W<REG> {
209        self.variant(REF::_1v25)
210    }
211    ///VFS = 2.5V with internal VBGR reference
212    #[inline(always)]
213    pub fn _2v5(self) -> &'a mut crate::W<REG> {
214        self.variant(REF::_2v5)
215    }
216    ///VFS = AVDD with AVDD as reference source
217    #[inline(always)]
218    pub fn vdd(self) -> &'a mut crate::W<REG> {
219        self.variant(REF::Vdd)
220    }
221    ///VFS = 5V with internal VBGR reference
222    #[inline(always)]
223    pub fn _5v(self) -> &'a mut crate::W<REG> {
224        self.variant(REF::_5v)
225    }
226    ///Single ended external reference
227    #[inline(always)]
228    pub fn extsingle(self) -> &'a mut crate::W<REG> {
229        self.variant(REF::Extsingle)
230    }
231    ///Differential external reference, 2x
232    #[inline(always)]
233    pub fn _2xextdiff(self) -> &'a mut crate::W<REG> {
234        self.variant(REF::_2xextdiff)
235    }
236    ///VFS = 2xAVDD with AVDD as the reference source
237    #[inline(always)]
238    pub fn _2xvdd(self) -> &'a mut crate::W<REG> {
239        self.variant(REF::_2xvdd)
240    }
241    ///Use SINGLECTRLX to configure reference
242    #[inline(always)]
243    pub fn conf(self) -> &'a mut crate::W<REG> {
244        self.variant(REF::Conf)
245    }
246}
247///Field `POSSEL` reader - Single Channel Positive Input Selection
248pub type PosselR = crate::FieldReader;
249///Field `POSSEL` writer - Single Channel Positive Input Selection
250pub type PosselW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
251///Field `NEGSEL` reader - Single Channel Negative Input Selection
252pub type NegselR = crate::FieldReader;
253///Field `NEGSEL` writer - Single Channel Negative Input Selection
254pub type NegselW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
255///Single Channel Acquisition Time
256///
257///Value on reset: 0
258#[cfg_attr(feature = "defmt", derive(defmt::Format))]
259#[derive(Clone, Copy, Debug, PartialEq, Eq)]
260#[repr(u8)]
261pub enum AT {
262    ///0: 1 conversion clock cycle acquisition time for single channel
263    _1cycle = 0,
264    ///1: 2 conversion clock cycles acquisition time for single channel
265    _2cycles = 1,
266    ///2: 3 conversion clock cycles acquisition time for single channel
267    _3cycles = 2,
268    ///3: 4 conversion clock cycles acquisition time for single channel
269    _4cycles = 3,
270    ///4: 8 conversion clock cycles acquisition time for single channel
271    _8cycles = 4,
272    ///5: 16 conversion clock cycles acquisition time for single channel
273    _16cycles = 5,
274    ///6: 32 conversion clock cycles acquisition time for single channel
275    _32cycles = 6,
276    ///7: 64 conversion clock cycles acquisition time for single channel
277    _64cycles = 7,
278    ///8: 128 conversion clock cycles acquisition time for single channel
279    _128cycles = 8,
280    ///9: 256 conversion clock cycles acquisition time for single channel
281    _256cycles = 9,
282}
283impl From<AT> for u8 {
284    #[inline(always)]
285    fn from(variant: AT) -> Self {
286        variant as _
287    }
288}
289impl crate::FieldSpec for AT {
290    type Ux = u8;
291}
292impl crate::IsEnum for AT {}
293///Field `AT` reader - Single Channel Acquisition Time
294pub type AtR = crate::FieldReader<AT>;
295impl AtR {
296    ///Get enumerated values variant
297    #[inline(always)]
298    pub const fn variant(&self) -> Option<AT> {
299        match self.bits {
300            0 => Some(AT::_1cycle),
301            1 => Some(AT::_2cycles),
302            2 => Some(AT::_3cycles),
303            3 => Some(AT::_4cycles),
304            4 => Some(AT::_8cycles),
305            5 => Some(AT::_16cycles),
306            6 => Some(AT::_32cycles),
307            7 => Some(AT::_64cycles),
308            8 => Some(AT::_128cycles),
309            9 => Some(AT::_256cycles),
310            _ => None,
311        }
312    }
313    ///1 conversion clock cycle acquisition time for single channel
314    #[inline(always)]
315    pub fn is_1cycle(&self) -> bool {
316        *self == AT::_1cycle
317    }
318    ///2 conversion clock cycles acquisition time for single channel
319    #[inline(always)]
320    pub fn is_2cycles(&self) -> bool {
321        *self == AT::_2cycles
322    }
323    ///3 conversion clock cycles acquisition time for single channel
324    #[inline(always)]
325    pub fn is_3cycles(&self) -> bool {
326        *self == AT::_3cycles
327    }
328    ///4 conversion clock cycles acquisition time for single channel
329    #[inline(always)]
330    pub fn is_4cycles(&self) -> bool {
331        *self == AT::_4cycles
332    }
333    ///8 conversion clock cycles acquisition time for single channel
334    #[inline(always)]
335    pub fn is_8cycles(&self) -> bool {
336        *self == AT::_8cycles
337    }
338    ///16 conversion clock cycles acquisition time for single channel
339    #[inline(always)]
340    pub fn is_16cycles(&self) -> bool {
341        *self == AT::_16cycles
342    }
343    ///32 conversion clock cycles acquisition time for single channel
344    #[inline(always)]
345    pub fn is_32cycles(&self) -> bool {
346        *self == AT::_32cycles
347    }
348    ///64 conversion clock cycles acquisition time for single channel
349    #[inline(always)]
350    pub fn is_64cycles(&self) -> bool {
351        *self == AT::_64cycles
352    }
353    ///128 conversion clock cycles acquisition time for single channel
354    #[inline(always)]
355    pub fn is_128cycles(&self) -> bool {
356        *self == AT::_128cycles
357    }
358    ///256 conversion clock cycles acquisition time for single channel
359    #[inline(always)]
360    pub fn is_256cycles(&self) -> bool {
361        *self == AT::_256cycles
362    }
363}
364///Field `AT` writer - Single Channel Acquisition Time
365pub type AtW<'a, REG> = crate::FieldWriter<'a, REG, 4, AT>;
366impl<'a, REG> AtW<'a, REG>
367where
368    REG: crate::Writable + crate::RegisterSpec,
369    REG::Ux: From<u8>,
370{
371    ///1 conversion clock cycle acquisition time for single channel
372    #[inline(always)]
373    pub fn _1cycle(self) -> &'a mut crate::W<REG> {
374        self.variant(AT::_1cycle)
375    }
376    ///2 conversion clock cycles acquisition time for single channel
377    #[inline(always)]
378    pub fn _2cycles(self) -> &'a mut crate::W<REG> {
379        self.variant(AT::_2cycles)
380    }
381    ///3 conversion clock cycles acquisition time for single channel
382    #[inline(always)]
383    pub fn _3cycles(self) -> &'a mut crate::W<REG> {
384        self.variant(AT::_3cycles)
385    }
386    ///4 conversion clock cycles acquisition time for single channel
387    #[inline(always)]
388    pub fn _4cycles(self) -> &'a mut crate::W<REG> {
389        self.variant(AT::_4cycles)
390    }
391    ///8 conversion clock cycles acquisition time for single channel
392    #[inline(always)]
393    pub fn _8cycles(self) -> &'a mut crate::W<REG> {
394        self.variant(AT::_8cycles)
395    }
396    ///16 conversion clock cycles acquisition time for single channel
397    #[inline(always)]
398    pub fn _16cycles(self) -> &'a mut crate::W<REG> {
399        self.variant(AT::_16cycles)
400    }
401    ///32 conversion clock cycles acquisition time for single channel
402    #[inline(always)]
403    pub fn _32cycles(self) -> &'a mut crate::W<REG> {
404        self.variant(AT::_32cycles)
405    }
406    ///64 conversion clock cycles acquisition time for single channel
407    #[inline(always)]
408    pub fn _64cycles(self) -> &'a mut crate::W<REG> {
409        self.variant(AT::_64cycles)
410    }
411    ///128 conversion clock cycles acquisition time for single channel
412    #[inline(always)]
413    pub fn _128cycles(self) -> &'a mut crate::W<REG> {
414        self.variant(AT::_128cycles)
415    }
416    ///256 conversion clock cycles acquisition time for single channel
417    #[inline(always)]
418    pub fn _256cycles(self) -> &'a mut crate::W<REG> {
419        self.variant(AT::_256cycles)
420    }
421}
422///Field `PRSEN` reader - Single Channel PRS Trigger Enable
423pub type PrsenR = crate::BitReader;
424///Field `PRSEN` writer - Single Channel PRS Trigger Enable
425pub type PrsenW<'a, REG> = crate::BitWriter<'a, REG>;
426///Field `CMPEN` reader - Compare Logic Enable for Single Channel
427pub type CmpenR = crate::BitReader;
428///Field `CMPEN` writer - Compare Logic Enable for Single Channel
429pub type CmpenW<'a, REG> = crate::BitWriter<'a, REG>;
430impl R {
431    ///Bit 0 - Single Channel Repetitive Mode
432    #[inline(always)]
433    pub fn rep(&self) -> RepR {
434        RepR::new((self.bits & 1) != 0)
435    }
436    ///Bit 1 - Single Channel Differential Mode
437    #[inline(always)]
438    pub fn diff(&self) -> DiffR {
439        DiffR::new(((self.bits >> 1) & 1) != 0)
440    }
441    ///Bit 2 - Single Channel Result Adjustment
442    #[inline(always)]
443    pub fn adj(&self) -> AdjR {
444        AdjR::new(((self.bits >> 2) & 1) != 0)
445    }
446    ///Bits 3:4 - Single Channel Resolution Select
447    #[inline(always)]
448    pub fn res(&self) -> ResR {
449        ResR::new(((self.bits >> 3) & 3) as u8)
450    }
451    ///Bits 5:7 - Single Channel Reference Selection
452    #[inline(always)]
453    pub fn ref_(&self) -> RefR {
454        RefR::new(((self.bits >> 5) & 7) as u8)
455    }
456    ///Bits 8:15 - Single Channel Positive Input Selection
457    #[inline(always)]
458    pub fn possel(&self) -> PosselR {
459        PosselR::new(((self.bits >> 8) & 0xff) as u8)
460    }
461    ///Bits 16:23 - Single Channel Negative Input Selection
462    #[inline(always)]
463    pub fn negsel(&self) -> NegselR {
464        NegselR::new(((self.bits >> 16) & 0xff) as u8)
465    }
466    ///Bits 24:27 - Single Channel Acquisition Time
467    #[inline(always)]
468    pub fn at(&self) -> AtR {
469        AtR::new(((self.bits >> 24) & 0x0f) as u8)
470    }
471    ///Bit 29 - Single Channel PRS Trigger Enable
472    #[inline(always)]
473    pub fn prsen(&self) -> PrsenR {
474        PrsenR::new(((self.bits >> 29) & 1) != 0)
475    }
476    ///Bit 31 - Compare Logic Enable for Single Channel
477    #[inline(always)]
478    pub fn cmpen(&self) -> CmpenR {
479        CmpenR::new(((self.bits >> 31) & 1) != 0)
480    }
481}
482impl core::fmt::Debug for R {
483    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
484        f.debug_struct("SINGLECTRL")
485            .field("rep", &self.rep())
486            .field("diff", &self.diff())
487            .field("adj", &self.adj())
488            .field("res", &self.res())
489            .field("ref_", &self.ref_())
490            .field("possel", &self.possel())
491            .field("negsel", &self.negsel())
492            .field("at", &self.at())
493            .field("prsen", &self.prsen())
494            .field("cmpen", &self.cmpen())
495            .finish()
496    }
497}
498impl W {
499    ///Bit 0 - Single Channel Repetitive Mode
500    #[inline(always)]
501    pub fn rep(&mut self) -> RepW<'_, SINGLECTRLrs> {
502        RepW::new(self, 0)
503    }
504    ///Bit 1 - Single Channel Differential Mode
505    #[inline(always)]
506    pub fn diff(&mut self) -> DiffW<'_, SINGLECTRLrs> {
507        DiffW::new(self, 1)
508    }
509    ///Bit 2 - Single Channel Result Adjustment
510    #[inline(always)]
511    pub fn adj(&mut self) -> AdjW<'_, SINGLECTRLrs> {
512        AdjW::new(self, 2)
513    }
514    ///Bits 3:4 - Single Channel Resolution Select
515    #[inline(always)]
516    pub fn res(&mut self) -> ResW<'_, SINGLECTRLrs> {
517        ResW::new(self, 3)
518    }
519    ///Bits 5:7 - Single Channel Reference Selection
520    #[inline(always)]
521    pub fn ref_(&mut self) -> RefW<'_, SINGLECTRLrs> {
522        RefW::new(self, 5)
523    }
524    ///Bits 8:15 - Single Channel Positive Input Selection
525    #[inline(always)]
526    pub fn possel(&mut self) -> PosselW<'_, SINGLECTRLrs> {
527        PosselW::new(self, 8)
528    }
529    ///Bits 16:23 - Single Channel Negative Input Selection
530    #[inline(always)]
531    pub fn negsel(&mut self) -> NegselW<'_, SINGLECTRLrs> {
532        NegselW::new(self, 16)
533    }
534    ///Bits 24:27 - Single Channel Acquisition Time
535    #[inline(always)]
536    pub fn at(&mut self) -> AtW<'_, SINGLECTRLrs> {
537        AtW::new(self, 24)
538    }
539    ///Bit 29 - Single Channel PRS Trigger Enable
540    #[inline(always)]
541    pub fn prsen(&mut self) -> PrsenW<'_, SINGLECTRLrs> {
542        PrsenW::new(self, 29)
543    }
544    ///Bit 31 - Compare Logic Enable for Single Channel
545    #[inline(always)]
546    pub fn cmpen(&mut self) -> CmpenW<'_, SINGLECTRLrs> {
547        CmpenW::new(self, 31)
548    }
549}
550///Single Channel Control Register
551///
552///You can [`read`](crate::Reg::read) this register and get [`singlectrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`singlectrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
553pub struct SINGLECTRLrs;
554impl crate::RegisterSpec for SINGLECTRLrs {
555    type Ux = u32;
556}
557///`read()` method returns [`singlectrl::R`](R) reader structure
558impl crate::Readable for SINGLECTRLrs {}
559///`write(|w| ..)` method takes [`singlectrl::W`](W) writer structure
560impl crate::Writable for SINGLECTRLrs {
561    type Safety = crate::Unsafe;
562}
563///`reset()` method sets SINGLECTRL to value 0x00ff_ff00
564impl crate::Resettable for SINGLECTRLrs {
565    const RESET_VALUE: u32 = 0x00ff_ff00;
566}
efm32pg1b_pac/adc0/singlectrl.rs

efm32pg1b_pac/adc0/
singlectrl.rs
