efm32pg1b-pac 0.4.3

Peripheral access API for Silicon Labs EFM32PG1B microcontrollers
Documentation 
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///Register `SWPULSE` writer
pub type W = crate::W<SWPULSErs>;
///Field `CH0PULSE` writer - Channel 0 Pulse Generation
pub type Ch0pulseW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CH1PULSE` writer - Channel 1 Pulse Generation
pub type Ch1pulseW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CH2PULSE` writer - Channel 2 Pulse Generation
pub type Ch2pulseW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CH3PULSE` writer - Channel 3 Pulse Generation
pub type Ch3pulseW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CH4PULSE` writer - Channel 4 Pulse Generation
pub type Ch4pulseW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CH5PULSE` writer - Channel 5 Pulse Generation
pub type Ch5pulseW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CH6PULSE` writer - Channel 6 Pulse Generation
pub type Ch6pulseW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CH7PULSE` writer - Channel 7 Pulse Generation
pub type Ch7pulseW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CH8PULSE` writer - Channel 8 Pulse Generation
pub type Ch8pulseW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CH9PULSE` writer - Channel 9 Pulse Generation
pub type Ch9pulseW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CH10PULSE` writer - Channel 10 Pulse Generation
pub type Ch10pulseW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CH11PULSE` writer - Channel 11 Pulse Generation
pub type Ch11pulseW<'a, REG> = crate::BitWriter<'a, REG>;
impl core::fmt::Debug for crate::generic::Reg<SWPULSErs> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        write!(f, "(not readable)")
    }
}
impl W {
    ///Bit 0 - Channel 0 Pulse Generation
    #[inline(always)]
    pub fn ch0pulse(&mut self) -> Ch0pulseW<'_, SWPULSErs> {
        Ch0pulseW::new(self, 0)
    }
    ///Bit 1 - Channel 1 Pulse Generation
    #[inline(always)]
    pub fn ch1pulse(&mut self) -> Ch1pulseW<'_, SWPULSErs> {
        Ch1pulseW::new(self, 1)
    }
    ///Bit 2 - Channel 2 Pulse Generation
    #[inline(always)]
    pub fn ch2pulse(&mut self) -> Ch2pulseW<'_, SWPULSErs> {
        Ch2pulseW::new(self, 2)
    }
    ///Bit 3 - Channel 3 Pulse Generation
    #[inline(always)]
    pub fn ch3pulse(&mut self) -> Ch3pulseW<'_, SWPULSErs> {
        Ch3pulseW::new(self, 3)
    }
    ///Bit 4 - Channel 4 Pulse Generation
    #[inline(always)]
    pub fn ch4pulse(&mut self) -> Ch4pulseW<'_, SWPULSErs> {
        Ch4pulseW::new(self, 4)
    }
    ///Bit 5 - Channel 5 Pulse Generation
    #[inline(always)]
    pub fn ch5pulse(&mut self) -> Ch5pulseW<'_, SWPULSErs> {
        Ch5pulseW::new(self, 5)
    }
    ///Bit 6 - Channel 6 Pulse Generation
    #[inline(always)]
    pub fn ch6pulse(&mut self) -> Ch6pulseW<'_, SWPULSErs> {
        Ch6pulseW::new(self, 6)
    }
    ///Bit 7 - Channel 7 Pulse Generation
    #[inline(always)]
    pub fn ch7pulse(&mut self) -> Ch7pulseW<'_, SWPULSErs> {
        Ch7pulseW::new(self, 7)
    }
    ///Bit 8 - Channel 8 Pulse Generation
    #[inline(always)]
    pub fn ch8pulse(&mut self) -> Ch8pulseW<'_, SWPULSErs> {
        Ch8pulseW::new(self, 8)
    }
    ///Bit 9 - Channel 9 Pulse Generation
    #[inline(always)]
    pub fn ch9pulse(&mut self) -> Ch9pulseW<'_, SWPULSErs> {
        Ch9pulseW::new(self, 9)
    }
    ///Bit 10 - Channel 10 Pulse Generation
    #[inline(always)]
    pub fn ch10pulse(&mut self) -> Ch10pulseW<'_, SWPULSErs> {
        Ch10pulseW::new(self, 10)
    }
    ///Bit 11 - Channel 11 Pulse Generation
    #[inline(always)]
    pub fn ch11pulse(&mut self) -> Ch11pulseW<'_, SWPULSErs> {
        Ch11pulseW::new(self, 11)
    }
}
///Software Pulse Register
///
///You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swpulse::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
pub struct SWPULSErs;
impl crate::RegisterSpec for SWPULSErs {
    type Ux = u32;
}
///`write(|w| ..)` method takes [`swpulse::W`](W) writer structure
impl crate::Writable for SWPULSErs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets SWPULSE to value 0
impl crate::Resettable for SWPULSErs {}