efm32pg1b-pac 0.4.3

//!Peripheral access API for EFM32PG1B microcontrollers (generated using svd2rust v0.37.1 ( ))
//!
//!You can find an overview of the generated API [here].
//!
//!API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
//!
//![here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api
//![next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
//![repository]: https://github.com/rust-embedded/svd2rust
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]
///Number available in the NVIC for configuring priority
pub const NVIC_PRIO_BITS: u8 = 3;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[allow(unused_imports)]
use generic::*;
///Common register and bit access and modify traits
pub mod generic;
#[cfg(feature = "rt")]
extern "C" {
    fn EMU();
    fn WDOG0();
    fn LDMA();
    fn GPIO_EVEN();
    fn TIMER0();
    fn USART0_RX();
    fn USART0_TX();
    fn ACMP0();
    fn ADC0();
    fn IDAC0();
    fn I2C0();
    fn GPIO_ODD();
    fn TIMER1();
    fn USART1_RX();
    fn USART1_TX();
    fn LEUART0();
    fn PCNT0();
    fn CMU();
    fn MSC();
    fn CRYPTO();
    fn LETIMER0();
    fn RTCC();
    fn CRYOTIMER();
    fn FPUEH();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
    _handler: unsafe extern "C" fn(),
    _reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 34] = [
    Vector { _handler: EMU },
    Vector { _reserved: 0 },
    Vector { _handler: WDOG0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: LDMA },
    Vector {
        _handler: GPIO_EVEN,
    },
    Vector { _handler: TIMER0 },
    Vector {
        _handler: USART0_RX,
    },
    Vector {
        _handler: USART0_TX,
    },
    Vector { _handler: ACMP0 },
    Vector { _handler: ADC0 },
    Vector { _handler: IDAC0 },
    Vector { _handler: I2C0 },
    Vector { _handler: GPIO_ODD },
    Vector { _handler: TIMER1 },
    Vector {
        _handler: USART1_RX,
    },
    Vector {
        _handler: USART1_TX,
    },
    Vector { _handler: LEUART0 },
    Vector { _handler: PCNT0 },
    Vector { _handler: CMU },
    Vector { _handler: MSC },
    Vector { _handler: CRYPTO },
    Vector { _handler: LETIMER0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: RTCC },
    Vector { _reserved: 0 },
    Vector {
        _handler: CRYOTIMER,
    },
    Vector { _reserved: 0 },
    Vector { _handler: FPUEH },
];
///Enumeration of all the interrupts.
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
    ///0 - EMU
    EMU = 0,
    ///2 - WDOG0
    WDOG0 = 2,
    ///8 - LDMA
    LDMA = 8,
    ///9 - GPIO_EVEN
    GPIO_EVEN = 9,
    ///10 - TIMER0
    TIMER0 = 10,
    ///11 - USART0_RX
    USART0_RX = 11,
    ///12 - USART0_TX
    USART0_TX = 12,
    ///13 - ACMP0
    ACMP0 = 13,
    ///14 - ADC0
    ADC0 = 14,
    ///15 - IDAC0
    IDAC0 = 15,
    ///16 - I2C0
    I2C0 = 16,
    ///17 - GPIO_ODD
    GPIO_ODD = 17,
    ///18 - TIMER1
    TIMER1 = 18,
    ///19 - USART1_RX
    USART1_RX = 19,
    ///20 - USART1_TX
    USART1_TX = 20,
    ///21 - LEUART0
    LEUART0 = 21,
    ///22 - PCNT0
    PCNT0 = 22,
    ///23 - CMU
    CMU = 23,
    ///24 - MSC
    MSC = 24,
    ///25 - CRYPTO
    CRYPTO = 25,
    ///26 - LETIMER0
    LETIMER0 = 26,
    ///29 - RTCC
    RTCC = 29,
    ///31 - CRYOTIMER
    CRYOTIMER = 31,
    ///33 - FPUEH
    FPUEH = 33,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
    #[inline(always)]
    fn number(self) -> u16 {
        self as u16
    }
}
///MSC
pub type Msc = crate::Periph<msc::RegisterBlock, 0x400e_0000>;
impl core::fmt::Debug for Msc {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Msc").finish()
    }
}
///MSC
pub mod msc;
///EMU
pub type Emu = crate::Periph<emu::RegisterBlock, 0x400e_3000>;
impl core::fmt::Debug for Emu {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Emu").finish()
    }
}
///EMU
pub mod emu;
///RMU
pub type Rmu = crate::Periph<rmu::RegisterBlock, 0x400e_5000>;
impl core::fmt::Debug for Rmu {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Rmu").finish()
    }
}
///RMU
pub mod rmu;
///CMU
pub type Cmu = crate::Periph<cmu::RegisterBlock, 0x400e_4000>;
impl core::fmt::Debug for Cmu {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Cmu").finish()
    }
}
///CMU
pub mod cmu;
///CRYPTO
pub type Crypto = crate::Periph<crypto::RegisterBlock, 0x400f_0000>;
impl core::fmt::Debug for Crypto {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Crypto").finish()
    }
}
///CRYPTO
pub mod crypto;
///GPIO
pub type Gpio = crate::Periph<gpio::RegisterBlock, 0x4000_a000>;
impl core::fmt::Debug for Gpio {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Gpio").finish()
    }
}
///GPIO
pub mod gpio;
///PRS
pub type Prs = crate::Periph<prs::RegisterBlock, 0x400e_6000>;
impl core::fmt::Debug for Prs {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Prs").finish()
    }
}
///PRS
pub mod prs;
///Linked Direct Memory Access
pub type Ldma = crate::Periph<ldma::RegisterBlock, 0x400e_2000>;
impl core::fmt::Debug for Ldma {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Ldma").finish()
    }
}
///Linked Direct Memory Access
pub mod ldma;
///FPUEH
pub type Fpueh = crate::Periph<fpueh::RegisterBlock, 0x400e_1000>;
impl core::fmt::Debug for Fpueh {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Fpueh").finish()
    }
}
///FPUEH
pub mod fpueh;
///General Purpose Cyclic Redundancy Check
pub type Gpcrc = crate::Periph<gpcrc::RegisterBlock, 0x4001_c000>;
impl core::fmt::Debug for Gpcrc {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Gpcrc").finish()
    }
}
///General Purpose Cyclic Redundancy Check
pub mod gpcrc;
///TIMER0
pub type Timer0 = crate::Periph<timer0::RegisterBlock, 0x4001_8000>;
impl core::fmt::Debug for Timer0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Timer0").finish()
    }
}
///TIMER0
pub mod timer0;
///TIMER1
pub type Timer1 = crate::Periph<timer0::RegisterBlock, 0x4001_8400>;
impl core::fmt::Debug for Timer1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Timer1").finish()
    }
}
///TIMER1
pub use self::timer0 as timer1;
///USART0
pub type Usart0 = crate::Periph<usart0::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for Usart0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Usart0").finish()
    }
}
///USART0
pub mod usart0;
///USART1
pub type Usart1 = crate::Periph<usart0::RegisterBlock, 0x4001_0400>;
impl core::fmt::Debug for Usart1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Usart1").finish()
    }
}
///USART1
pub use self::usart0 as usart1;
///LEUART0
pub type Leuart0 = crate::Periph<leuart0::RegisterBlock, 0x4004_a000>;
impl core::fmt::Debug for Leuart0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Leuart0").finish()
    }
}
///LEUART0
pub mod leuart0;
///LETIMER0
pub type Letimer0 = crate::Periph<letimer0::RegisterBlock, 0x4004_6000>;
impl core::fmt::Debug for Letimer0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Letimer0").finish()
    }
}
///LETIMER0
pub mod letimer0;
///CRYOTIMER
pub type Cryotimer = crate::Periph<cryotimer::RegisterBlock, 0x4001_e000>;
impl core::fmt::Debug for Cryotimer {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Cryotimer").finish()
    }
}
///CRYOTIMER
pub mod cryotimer;
///Pulse Counter
pub type Pcnt0 = crate::Periph<pcnt0::RegisterBlock, 0x4004_e000>;
impl core::fmt::Debug for Pcnt0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Pcnt0").finish()
    }
}
///Pulse Counter
pub mod pcnt0;
///I2C0
pub type I2c0 = crate::Periph<i2c0::RegisterBlock, 0x4000_c000>;
impl core::fmt::Debug for I2c0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2c0").finish()
    }
}
///I2C0
pub mod i2c0;
///ADC0
pub type Adc0 = crate::Periph<adc0::RegisterBlock, 0x4000_2000>;
impl core::fmt::Debug for Adc0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Adc0").finish()
    }
}
///ADC0
pub mod adc0;
///ACMP0
pub type Acmp0 = crate::Periph<acmp0::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for Acmp0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Acmp0").finish()
    }
}
///ACMP0
pub mod acmp0;
///ACMP1
pub type Acmp1 = crate::Periph<acmp1::RegisterBlock, 0x4000_0400>;
impl core::fmt::Debug for Acmp1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Acmp1").finish()
    }
}
///ACMP1
pub mod acmp1;
///IDAC0
pub type Idac0 = crate::Periph<idac0::RegisterBlock, 0x4000_6000>;
impl core::fmt::Debug for Idac0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Idac0").finish()
    }
}
///IDAC0
pub mod idac0;
///RTCC
pub type Rtcc = crate::Periph<rtcc::RegisterBlock, 0x4004_2000>;
impl core::fmt::Debug for Rtcc {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Rtcc").finish()
    }
}
///RTCC
pub mod rtcc;
///WDOG0
pub type Wdog0 = crate::Periph<wdog0::RegisterBlock, 0x4005_2000>;
impl core::fmt::Debug for Wdog0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Wdog0").finish()
    }
}
///WDOG0
pub mod wdog0;
///Device Information
pub type Di = crate::Periph<di::RegisterBlock, 0x0fe0_81b0>;
impl core::fmt::Debug for Di {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Di").finish()
    }
}
///Device Information
pub mod di;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
/// All the peripherals.
#[allow(non_snake_case)]
pub struct Peripherals {
    ///MSC
    pub msc: Msc,
    ///EMU
    pub emu: Emu,
    ///RMU
    pub rmu: Rmu,
    ///CMU
    pub cmu: Cmu,
    ///CRYPTO
    pub crypto: Crypto,
    ///GPIO
    pub gpio: Gpio,
    ///PRS
    pub prs: Prs,
    ///LDMA
    pub ldma: Ldma,
    ///FPUEH
    pub fpueh: Fpueh,
    ///GPCRC
    pub gpcrc: Gpcrc,
    ///TIMER0
    pub timer0: Timer0,
    ///TIMER1
    pub timer1: Timer1,
    ///USART0
    pub usart0: Usart0,
    ///USART1
    pub usart1: Usart1,
    ///LEUART0
    pub leuart0: Leuart0,
    ///LETIMER0
    pub letimer0: Letimer0,
    ///CRYOTIMER
    pub cryotimer: Cryotimer,
    ///PCNT0
    pub pcnt0: Pcnt0,
    ///I2C0
    pub i2c0: I2c0,
    ///ADC0
    pub adc0: Adc0,
    ///ACMP0
    pub acmp0: Acmp0,
    ///ACMP1
    pub acmp1: Acmp1,
    ///IDAC0
    pub idac0: Idac0,
    ///RTCC
    pub rtcc: Rtcc,
    ///WDOG0
    pub wdog0: Wdog0,
    ///DI
    pub di: Di,
}
impl Peripherals {
    /// Returns all the peripherals *once*.
    #[cfg(feature = "critical-section")]
    #[inline]
    pub fn take() -> Option<Self> {
        critical_section::with(|_| {
            if unsafe { DEVICE_PERIPHERALS } {
                return None;
            }
            Some(unsafe { Peripherals::steal() })
        })
    }
    /// Unchecked version of `Peripherals::take`.
    ///
    /// # Safety
    ///
    /// Each of the returned peripherals must be used at most once.
    #[inline]
    pub unsafe fn steal() -> Self {
        DEVICE_PERIPHERALS = true;
        Peripherals {
            msc: Msc::steal(),
            emu: Emu::steal(),
            rmu: Rmu::steal(),
            cmu: Cmu::steal(),
            crypto: Crypto::steal(),
            gpio: Gpio::steal(),
            prs: Prs::steal(),
            ldma: Ldma::steal(),
            fpueh: Fpueh::steal(),
            gpcrc: Gpcrc::steal(),
            timer0: Timer0::steal(),
            timer1: Timer1::steal(),
            usart0: Usart0::steal(),
            usart1: Usart1::steal(),
            leuart0: Leuart0::steal(),
            letimer0: Letimer0::steal(),
            cryotimer: Cryotimer::steal(),
            pcnt0: Pcnt0::steal(),
            i2c0: I2c0::steal(),
            adc0: Adc0::steal(),
            acmp0: Acmp0::steal(),
            acmp1: Acmp1::steal(),
            idac0: Idac0::steal(),
            rtcc: Rtcc::steal(),
            wdog0: Wdog0::steal(),
            di: Di::steal(),
        }
    }
}