efm32pg1b-pac 0.4.3

Peripheral access API for Silicon Labs EFM32PG1B microcontrollers
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

///Register `IFC` writer
pub type W = crate::W<IFCrs>;
///Field `FPIOC` writer - Clear FPIOC Interrupt Flag
pub type FpiocW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `FPDZC` writer - Clear FPDZC Interrupt Flag
pub type FpdzcW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `FPUFC` writer - Clear FPUFC Interrupt Flag
pub type FpufcW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `FPOFC` writer - Clear FPOFC Interrupt Flag
pub type FpofcW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `FPIDC` writer - Clear FPIDC Interrupt Flag
pub type FpidcW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `FPIXC` writer - Clear FPIXC Interrupt Flag
pub type FpixcW<'a, REG> = crate::BitWriter<'a, REG>;
impl core::fmt::Debug for crate::generic::Reg<IFCrs> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        write!(f, "(not readable)")
    }
}
impl W {
    ///Bit 0 - Clear FPIOC Interrupt Flag
    #[inline(always)]
    pub fn fpioc(&mut self) -> FpiocW<'_, IFCrs> {
        FpiocW::new(self, 0)
    }
    ///Bit 1 - Clear FPDZC Interrupt Flag
    #[inline(always)]
    pub fn fpdzc(&mut self) -> FpdzcW<'_, IFCrs> {
        FpdzcW::new(self, 1)
    }
    ///Bit 2 - Clear FPUFC Interrupt Flag
    #[inline(always)]
    pub fn fpufc(&mut self) -> FpufcW<'_, IFCrs> {
        FpufcW::new(self, 2)
    }
    ///Bit 3 - Clear FPOFC Interrupt Flag
    #[inline(always)]
    pub fn fpofc(&mut self) -> FpofcW<'_, IFCrs> {
        FpofcW::new(self, 3)
    }
    ///Bit 4 - Clear FPIDC Interrupt Flag
    #[inline(always)]
    pub fn fpidc(&mut self) -> FpidcW<'_, IFCrs> {
        FpidcW::new(self, 4)
    }
    ///Bit 5 - Clear FPIXC Interrupt Flag
    #[inline(always)]
    pub fn fpixc(&mut self) -> FpixcW<'_, IFCrs> {
        FpixcW::new(self, 5)
    }
}
///Interrupt Flag Clear Register
///
///You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ifc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
pub struct IFCrs;
impl crate::RegisterSpec for IFCrs {
    type Ux = u32;
}
///`write(|w| ..)` method takes [`ifc::W`](W) writer structure
impl crate::Writable for IFCrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets IFC to value 0
impl crate::Resettable for IFCrs {}