efm32pg1b-pac 0.4.3

Peripheral access API for Silicon Labs EFM32PG1B microcontrollers
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

///Register `ROUTEPEN` reader
pub type R = crate::R<ROUTEPENrs>;
///Register `ROUTEPEN` writer
pub type W = crate::W<ROUTEPENrs>;
///Field `OUTPEN` reader - ACMP Output Pin Enable
pub type OutpenR = crate::BitReader;
///Field `OUTPEN` writer - ACMP Output Pin Enable
pub type OutpenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - ACMP Output Pin Enable
    #[inline(always)]
    pub fn outpen(&self) -> OutpenR {
        OutpenR::new((self.bits & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ROUTEPEN")
            .field("outpen", &self.outpen())
            .finish()
    }
}
impl W {
    ///Bit 0 - ACMP Output Pin Enable
    #[inline(always)]
    pub fn outpen(&mut self) -> OutpenW<'_, ROUTEPENrs> {
        OutpenW::new(self, 0)
    }
}
///I/O Routing Pine Enable Register
///
///You can [`read`](crate::Reg::read) this register and get [`routepen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`routepen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
pub struct ROUTEPENrs;
impl crate::RegisterSpec for ROUTEPENrs {
    type Ux = u32;
}
///`read()` method returns [`routepen::R`](R) reader structure
impl crate::Readable for ROUTEPENrs {}
///`write(|w| ..)` method takes [`routepen::W`](W) writer structure
impl crate::Writable for ROUTEPENrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets ROUTEPEN to value 0
impl crate::Resettable for ROUTEPENrs {}