efm32pg1b_pac/pcnt0/
ien.rs

1///Register `IEN` reader
2pub type R = crate::R<IENrs>;
3///Register `IEN` writer
4pub type W = crate::W<IENrs>;
5///Field `UF` reader - UF Interrupt Enable
6pub type UfR = crate::BitReader;
7///Field `UF` writer - UF Interrupt Enable
8pub type UfW<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `OF` reader - OF Interrupt Enable
10pub type OfR = crate::BitReader;
11///Field `OF` writer - OF Interrupt Enable
12pub type OfW<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `DIRCNG` reader - DIRCNG Interrupt Enable
14pub type DircngR = crate::BitReader;
15///Field `DIRCNG` writer - DIRCNG Interrupt Enable
16pub type DircngW<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `AUXOF` reader - AUXOF Interrupt Enable
18pub type AuxofR = crate::BitReader;
19///Field `AUXOF` writer - AUXOF Interrupt Enable
20pub type AuxofW<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `TCC` reader - TCC Interrupt Enable
22pub type TccR = crate::BitReader;
23///Field `TCC` writer - TCC Interrupt Enable
24pub type TccW<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `OQSTERR` reader - OQSTERR Interrupt Enable
26pub type OqsterrR = crate::BitReader;
27///Field `OQSTERR` writer - OQSTERR Interrupt Enable
28pub type OqsterrW<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    ///Bit 0 - UF Interrupt Enable
31    #[inline(always)]
32    pub fn uf(&self) -> UfR {
33        UfR::new((self.bits & 1) != 0)
34    }
35    ///Bit 1 - OF Interrupt Enable
36    #[inline(always)]
37    pub fn of(&self) -> OfR {
38        OfR::new(((self.bits >> 1) & 1) != 0)
39    }
40    ///Bit 2 - DIRCNG Interrupt Enable
41    #[inline(always)]
42    pub fn dircng(&self) -> DircngR {
43        DircngR::new(((self.bits >> 2) & 1) != 0)
44    }
45    ///Bit 3 - AUXOF Interrupt Enable
46    #[inline(always)]
47    pub fn auxof(&self) -> AuxofR {
48        AuxofR::new(((self.bits >> 3) & 1) != 0)
49    }
50    ///Bit 4 - TCC Interrupt Enable
51    #[inline(always)]
52    pub fn tcc(&self) -> TccR {
53        TccR::new(((self.bits >> 4) & 1) != 0)
54    }
55    ///Bit 5 - OQSTERR Interrupt Enable
56    #[inline(always)]
57    pub fn oqsterr(&self) -> OqsterrR {
58        OqsterrR::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61impl core::fmt::Debug for R {
62    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
63        f.debug_struct("IEN")
64            .field("uf", &self.uf())
65            .field("of", &self.of())
66            .field("dircng", &self.dircng())
67            .field("auxof", &self.auxof())
68            .field("tcc", &self.tcc())
69            .field("oqsterr", &self.oqsterr())
70            .finish()
71    }
72}
73impl W {
74    ///Bit 0 - UF Interrupt Enable
75    #[inline(always)]
76    pub fn uf(&mut self) -> UfW<'_, IENrs> {
77        UfW::new(self, 0)
78    }
79    ///Bit 1 - OF Interrupt Enable
80    #[inline(always)]
81    pub fn of(&mut self) -> OfW<'_, IENrs> {
82        OfW::new(self, 1)
83    }
84    ///Bit 2 - DIRCNG Interrupt Enable
85    #[inline(always)]
86    pub fn dircng(&mut self) -> DircngW<'_, IENrs> {
87        DircngW::new(self, 2)
88    }
89    ///Bit 3 - AUXOF Interrupt Enable
90    #[inline(always)]
91    pub fn auxof(&mut self) -> AuxofW<'_, IENrs> {
92        AuxofW::new(self, 3)
93    }
94    ///Bit 4 - TCC Interrupt Enable
95    #[inline(always)]
96    pub fn tcc(&mut self) -> TccW<'_, IENrs> {
97        TccW::new(self, 4)
98    }
99    ///Bit 5 - OQSTERR Interrupt Enable
100    #[inline(always)]
101    pub fn oqsterr(&mut self) -> OqsterrW<'_, IENrs> {
102        OqsterrW::new(self, 5)
103    }
104}
105///Interrupt Enable Register
106///
107///You can [`read`](crate::Reg::read) this register and get [`ien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
108pub struct IENrs;
109impl crate::RegisterSpec for IENrs {
110    type Ux = u32;
111}
112///`read()` method returns [`ien::R`](R) reader structure
113impl crate::Readable for IENrs {}
114///`write(|w| ..)` method takes [`ien::W`](W) writer structure
115impl crate::Writable for IENrs {
116    type Safety = crate::Unsafe;
117}
118///`reset()` method sets IEN to value 0
119impl crate::Resettable for IENrs {}
efm32pg1b_pac/pcnt0/ien.rs

efm32pg1b_pac/pcnt0/
ien.rs
