efm32pg1b_pac/leuart0/
pulsectrl.rs

1///Register `PULSECTRL` reader
2pub type R = crate::R<PULSECTRLrs>;
3///Register `PULSECTRL` writer
4pub type W = crate::W<PULSECTRLrs>;
5///Field `PULSEW` reader - Pulse Width
6pub type PulsewR = crate::FieldReader;
7///Field `PULSEW` writer - Pulse Width
8pub type PulsewW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9///Field `PULSEEN` reader - Pulse Generator/Extender Enable
10pub type PulseenR = crate::BitReader;
11///Field `PULSEEN` writer - Pulse Generator/Extender Enable
12pub type PulseenW<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `PULSEFILT` reader - Pulse Filter
14pub type PulsefiltR = crate::BitReader;
15///Field `PULSEFILT` writer - Pulse Filter
16pub type PulsefiltW<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    ///Bits 0:3 - Pulse Width
19    #[inline(always)]
20    pub fn pulsew(&self) -> PulsewR {
21        PulsewR::new((self.bits & 0x0f) as u8)
22    }
23    ///Bit 4 - Pulse Generator/Extender Enable
24    #[inline(always)]
25    pub fn pulseen(&self) -> PulseenR {
26        PulseenR::new(((self.bits >> 4) & 1) != 0)
27    }
28    ///Bit 5 - Pulse Filter
29    #[inline(always)]
30    pub fn pulsefilt(&self) -> PulsefiltR {
31        PulsefiltR::new(((self.bits >> 5) & 1) != 0)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("PULSECTRL")
37            .field("pulsew", &self.pulsew())
38            .field("pulseen", &self.pulseen())
39            .field("pulsefilt", &self.pulsefilt())
40            .finish()
41    }
42}
43impl W {
44    ///Bits 0:3 - Pulse Width
45    #[inline(always)]
46    pub fn pulsew(&mut self) -> PulsewW<'_, PULSECTRLrs> {
47        PulsewW::new(self, 0)
48    }
49    ///Bit 4 - Pulse Generator/Extender Enable
50    #[inline(always)]
51    pub fn pulseen(&mut self) -> PulseenW<'_, PULSECTRLrs> {
52        PulseenW::new(self, 4)
53    }
54    ///Bit 5 - Pulse Filter
55    #[inline(always)]
56    pub fn pulsefilt(&mut self) -> PulsefiltW<'_, PULSECTRLrs> {
57        PulsefiltW::new(self, 5)
58    }
59}
60///Pulse Control Register
61///
62///You can [`read`](crate::Reg::read) this register and get [`pulsectrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pulsectrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63pub struct PULSECTRLrs;
64impl crate::RegisterSpec for PULSECTRLrs {
65    type Ux = u32;
66}
67///`read()` method returns [`pulsectrl::R`](R) reader structure
68impl crate::Readable for PULSECTRLrs {}
69///`write(|w| ..)` method takes [`pulsectrl::W`](W) writer structure
70impl crate::Writable for PULSECTRLrs {
71    type Safety = crate::Unsafe;
72}
73///`reset()` method sets PULSECTRL to value 0
74impl crate::Resettable for PULSECTRLrs {}
efm32pg1b_pac/leuart0/pulsectrl.rs

efm32pg1b_pac/leuart0/
pulsectrl.rs
