efm32hg322_pac/dma/
chenc.rs

1#[doc = "Register `CHENC` writer"]
2pub struct W(crate::W<CHENC_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHENC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHENC_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHENC_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CH0ENC` writer - Channel 0 Enable Clear"]
23pub type CH0ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 0>;
24#[doc = "Field `CH1ENC` writer - Channel 1 Enable Clear"]
25pub type CH1ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 1>;
26#[doc = "Field `CH2ENC` writer - Channel 2 Enable Clear"]
27pub type CH2ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 2>;
28#[doc = "Field `CH3ENC` writer - Channel 3 Enable Clear"]
29pub type CH3ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 3>;
30#[doc = "Field `CH4ENC` writer - Channel 4 Enable Clear"]
31pub type CH4ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 4>;
32#[doc = "Field `CH5ENC` writer - Channel 5 Enable Clear"]
33pub type CH5ENC_W<'a> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, 5>;
34impl W {
35    #[doc = "Bit 0 - Channel 0 Enable Clear"]
36    #[inline(always)]
37    pub fn ch0enc(&mut self) -> CH0ENC_W {
38        CH0ENC_W::new(self)
39    }
40    #[doc = "Bit 1 - Channel 1 Enable Clear"]
41    #[inline(always)]
42    pub fn ch1enc(&mut self) -> CH1ENC_W {
43        CH1ENC_W::new(self)
44    }
45    #[doc = "Bit 2 - Channel 2 Enable Clear"]
46    #[inline(always)]
47    pub fn ch2enc(&mut self) -> CH2ENC_W {
48        CH2ENC_W::new(self)
49    }
50    #[doc = "Bit 3 - Channel 3 Enable Clear"]
51    #[inline(always)]
52    pub fn ch3enc(&mut self) -> CH3ENC_W {
53        CH3ENC_W::new(self)
54    }
55    #[doc = "Bit 4 - Channel 4 Enable Clear"]
56    #[inline(always)]
57    pub fn ch4enc(&mut self) -> CH4ENC_W {
58        CH4ENC_W::new(self)
59    }
60    #[doc = "Bit 5 - Channel 5 Enable Clear"]
61    #[inline(always)]
62    pub fn ch5enc(&mut self) -> CH5ENC_W {
63        CH5ENC_W::new(self)
64    }
65    #[doc = "Writes raw bits to the register."]
66    #[inline(always)]
67    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
68        self.0.bits(bits);
69        self
70    }
71}
72#[doc = "Channel Enable Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chenc](index.html) module"]
73pub struct CHENC_SPEC;
74impl crate::RegisterSpec for CHENC_SPEC {
75    type Ux = u32;
76}
77#[doc = "`write(|w| ..)` method takes [chenc::W](W) writer structure"]
78impl crate::Writable for CHENC_SPEC {
79    type Writer = W;
80}
81#[doc = "`reset()` method sets CHENC to value 0"]
82impl crate::Resettable for CHENC_SPEC {
83    #[inline(always)]
84    fn reset_value() -> Self::Ux {
85        0
86    }
87}
efm32hg322_pac/dma/chenc.rs

efm32hg322_pac/dma/
chenc.rs
