1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - System Control Register"]
5 pub ctrl: crate::Reg<ctrl::CTRL_SPEC>,
6 #[doc = "0x04 - System Status Register"]
7 pub status: crate::Reg<status::STATUS_SPEC>,
8 #[doc = "0x08 - Interrupt Flag Register"]
9 pub if_: crate::Reg<if_::IF_SPEC>,
10 #[doc = "0x0c - Interrupt Flag Set Register"]
11 pub ifs: crate::Reg<ifs::IFS_SPEC>,
12 #[doc = "0x10 - Interrupt Flag Clear Register"]
13 pub ifc: crate::Reg<ifc::IFC_SPEC>,
14 #[doc = "0x14 - Interrupt Enable Register"]
15 pub ien: crate::Reg<ien::IEN_SPEC>,
16 #[doc = "0x18 - I/O Routing Register"]
17 pub route: crate::Reg<route::ROUTE_SPEC>,
18 _reserved7: [u8; 0x0003_bfec],
19 #[doc = "0x3c008 - AHB Configuration Register"]
20 pub gahbcfg: crate::Reg<gahbcfg::GAHBCFG_SPEC>,
21 #[doc = "0x3c00c - USB Configuration Register"]
22 pub gusbcfg: crate::Reg<gusbcfg::GUSBCFG_SPEC>,
23 #[doc = "0x3c010 - Reset Register"]
24 pub grstctl: crate::Reg<grstctl::GRSTCTL_SPEC>,
25 #[doc = "0x3c014 - Interrupt Register"]
26 pub gintsts: crate::Reg<gintsts::GINTSTS_SPEC>,
27 #[doc = "0x3c018 - Interrupt Mask Register"]
28 pub gintmsk: crate::Reg<gintmsk::GINTMSK_SPEC>,
29 #[doc = "0x3c01c - Receive Status Debug Read Register"]
30 pub grxstsr: crate::Reg<grxstsr::GRXSTSR_SPEC>,
31 #[doc = "0x3c020 - Receive Status Read and Pop Register"]
32 pub grxstsp: crate::Reg<grxstsp::GRXSTSP_SPEC>,
33 #[doc = "0x3c024 - Receive FIFO Size Register"]
34 pub grxfsiz: crate::Reg<grxfsiz::GRXFSIZ_SPEC>,
35 #[doc = "0x3c028 - Non-periodic Transmit FIFO Size Register"]
36 pub gnptxfsiz: crate::Reg<gnptxfsiz::GNPTXFSIZ_SPEC>,
37 _reserved16: [u8; 0x30],
38 #[doc = "0x3c05c - Global DFIFO Configuration Register"]
39 pub gdfifocfg: crate::Reg<gdfifocfg::GDFIFOCFG_SPEC>,
40 _reserved17: [u8; 0xa4],
41 #[doc = "0x3c104 - Device IN Endpoint Transmit FIFO 1 Size Register"]
42 pub dieptxf1: crate::Reg<dieptxf1::DIEPTXF1_SPEC>,
43 #[doc = "0x3c108 - Device IN Endpoint Transmit FIFO 2 Size Register"]
44 pub dieptxf2: crate::Reg<dieptxf2::DIEPTXF2_SPEC>,
45 #[doc = "0x3c10c - Device IN Endpoint Transmit FIFO 3 Size Register"]
46 pub dieptxf3: crate::Reg<dieptxf3::DIEPTXF3_SPEC>,
47 _reserved20: [u8; 0x06f0],
48 #[doc = "0x3c800 - Device Configuration Register"]
49 pub dcfg: crate::Reg<dcfg::DCFG_SPEC>,
50 #[doc = "0x3c804 - Device Control Register"]
51 pub dctl: crate::Reg<dctl::DCTL_SPEC>,
52 #[doc = "0x3c808 - Device Status Register"]
53 pub dsts: crate::Reg<dsts::DSTS_SPEC>,
54 _reserved23: [u8; 0x04],
55 #[doc = "0x3c810 - Device IN Endpoint Common Interrupt Mask Register"]
56 pub diepmsk: crate::Reg<diepmsk::DIEPMSK_SPEC>,
57 #[doc = "0x3c814 - Device OUT Endpoint Common Interrupt Mask Register"]
58 pub doepmsk: crate::Reg<doepmsk::DOEPMSK_SPEC>,
59 #[doc = "0x3c818 - Device All Endpoints Interrupt Register"]
60 pub daint: crate::Reg<daint::DAINT_SPEC>,
61 #[doc = "0x3c81c - Device All Endpoints Interrupt Mask Register"]
62 pub daintmsk: crate::Reg<daintmsk::DAINTMSK_SPEC>,
63 _reserved27: [u8; 0x14],
64 #[doc = "0x3c834 - Device IN Endpoint FIFO Empty Interrupt Mask Register"]
65 pub diepempmsk: crate::Reg<diepempmsk::DIEPEMPMSK_SPEC>,
66 _reserved28: [u8; 0xc8],
67 #[doc = "0x3c900 - Device IN Endpoint 0 Control Register"]
68 pub diep0ctl: crate::Reg<diep0ctl::DIEP0CTL_SPEC>,
69 _reserved29: [u8; 0x04],
70 #[doc = "0x3c908 - Device IN Endpoint 0 Interrupt Register"]
71 pub diep0int: crate::Reg<diep0int::DIEP0INT_SPEC>,
72 _reserved30: [u8; 0x04],
73 #[doc = "0x3c910 - Device IN Endpoint 0 Transfer Size Register"]
74 pub diep0tsiz: crate::Reg<diep0tsiz::DIEP0TSIZ_SPEC>,
75 #[doc = "0x3c914 - Device IN Endpoint 0 DMA Address Register"]
76 pub diep0dmaaddr: crate::Reg<diep0dmaaddr::DIEP0DMAADDR_SPEC>,
77 #[doc = "0x3c918 - Device IN Endpoint 0 Transmit FIFO Status Register"]
78 pub diep0txfsts: crate::Reg<diep0txfsts::DIEP0TXFSTS_SPEC>,
79 _reserved33: [u8; 0x04],
80 #[doc = "0x3c920 - Device IN Endpoint x+1 Control Register"]
81 pub diep0_ctl: crate::Reg<diep0_ctl::DIEP0_CTL_SPEC>,
82 _reserved34: [u8; 0x04],
83 #[doc = "0x3c928 - Device IN Endpoint x+1 Interrupt Register"]
84 pub diep0_int: crate::Reg<diep0_int::DIEP0_INT_SPEC>,
85 _reserved35: [u8; 0x04],
86 #[doc = "0x3c930 - Device IN Endpoint x+1 Transfer Size Register"]
87 pub diep0_tsiz: crate::Reg<diep0_tsiz::DIEP0_TSIZ_SPEC>,
88 #[doc = "0x3c934 - Device IN Endpoint x+1 DMA Address Register"]
89 pub diep0_dmaaddr: crate::Reg<diep0_dmaaddr::DIEP0_DMAADDR_SPEC>,
90 #[doc = "0x3c938 - Device IN Endpoint x+1 Transmit FIFO Status Register"]
91 pub diep0_txfsts: crate::Reg<diep0_txfsts::DIEP0_TXFSTS_SPEC>,
92 _reserved38: [u8; 0x04],
93 #[doc = "0x3c940 - Device IN Endpoint x+1 Control Register"]
94 pub diep1_ctl: crate::Reg<diep1_ctl::DIEP1_CTL_SPEC>,
95 _reserved39: [u8; 0x04],
96 #[doc = "0x3c948 - Device IN Endpoint x+1 Interrupt Register"]
97 pub diep1_int: crate::Reg<diep1_int::DIEP1_INT_SPEC>,
98 _reserved40: [u8; 0x04],
99 #[doc = "0x3c950 - Device IN Endpoint x+1 Transfer Size Register"]
100 pub diep1_tsiz: crate::Reg<diep1_tsiz::DIEP1_TSIZ_SPEC>,
101 #[doc = "0x3c954 - Device IN Endpoint x+1 DMA Address Register"]
102 pub diep1_dmaaddr: crate::Reg<diep1_dmaaddr::DIEP1_DMAADDR_SPEC>,
103 #[doc = "0x3c958 - Device IN Endpoint x+1 Transmit FIFO Status Register"]
104 pub diep1_txfsts: crate::Reg<diep1_txfsts::DIEP1_TXFSTS_SPEC>,
105 _reserved43: [u8; 0x04],
106 #[doc = "0x3c960 - Device IN Endpoint x+1 Control Register"]
107 pub diep2_ctl: crate::Reg<diep2_ctl::DIEP2_CTL_SPEC>,
108 _reserved44: [u8; 0x04],
109 #[doc = "0x3c968 - Device IN Endpoint x+1 Interrupt Register"]
110 pub diep2_int: crate::Reg<diep2_int::DIEP2_INT_SPEC>,
111 _reserved45: [u8; 0x04],
112 #[doc = "0x3c970 - Device IN Endpoint x+1 Transfer Size Register"]
113 pub diep2_tsiz: crate::Reg<diep2_tsiz::DIEP2_TSIZ_SPEC>,
114 #[doc = "0x3c974 - Device IN Endpoint x+1 DMA Address Register"]
115 pub diep2_dmaaddr: crate::Reg<diep2_dmaaddr::DIEP2_DMAADDR_SPEC>,
116 #[doc = "0x3c978 - Device IN Endpoint x+1 Transmit FIFO Status Register"]
117 pub diep2_txfsts: crate::Reg<diep2_txfsts::DIEP2_TXFSTS_SPEC>,
118 _reserved48: [u8; 0x0184],
119 #[doc = "0x3cb00 - Device OUT Endpoint 0 Control Register"]
120 pub doep0ctl: crate::Reg<doep0ctl::DOEP0CTL_SPEC>,
121 _reserved49: [u8; 0x04],
122 #[doc = "0x3cb08 - Device OUT Endpoint 0 Interrupt Register"]
123 pub doep0int: crate::Reg<doep0int::DOEP0INT_SPEC>,
124 _reserved50: [u8; 0x04],
125 #[doc = "0x3cb10 - Device OUT Endpoint 0 Transfer Size Register"]
126 pub doep0tsiz: crate::Reg<doep0tsiz::DOEP0TSIZ_SPEC>,
127 #[doc = "0x3cb14 - Device OUT Endpoint 0 DMA Address Register"]
128 pub doep0dmaaddr: crate::Reg<doep0dmaaddr::DOEP0DMAADDR_SPEC>,
129 _reserved52: [u8; 0x08],
130 #[doc = "0x3cb20 - Device OUT Endpoint x+1 Control Register"]
131 pub doep0_ctl: crate::Reg<doep0_ctl::DOEP0_CTL_SPEC>,
132 _reserved53: [u8; 0x04],
133 #[doc = "0x3cb28 - Device OUT Endpoint x+1 Interrupt Register"]
134 pub doep0_int: crate::Reg<doep0_int::DOEP0_INT_SPEC>,
135 _reserved54: [u8; 0x04],
136 #[doc = "0x3cb30 - Device OUT Endpoint x+1 Transfer Size Register"]
137 pub doep0_tsiz: crate::Reg<doep0_tsiz::DOEP0_TSIZ_SPEC>,
138 #[doc = "0x3cb34 - Device OUT Endpoint x+1 DMA Address Register"]
139 pub doep0_dmaaddr: crate::Reg<doep0_dmaaddr::DOEP0_DMAADDR_SPEC>,
140 _reserved56: [u8; 0x08],
141 #[doc = "0x3cb40 - Device OUT Endpoint x+1 Control Register"]
142 pub doep1_ctl: crate::Reg<doep1_ctl::DOEP1_CTL_SPEC>,
143 _reserved57: [u8; 0x04],
144 #[doc = "0x3cb48 - Device OUT Endpoint x+1 Interrupt Register"]
145 pub doep1_int: crate::Reg<doep1_int::DOEP1_INT_SPEC>,
146 _reserved58: [u8; 0x04],
147 #[doc = "0x3cb50 - Device OUT Endpoint x+1 Transfer Size Register"]
148 pub doep1_tsiz: crate::Reg<doep1_tsiz::DOEP1_TSIZ_SPEC>,
149 #[doc = "0x3cb54 - Device OUT Endpoint x+1 DMA Address Register"]
150 pub doep1_dmaaddr: crate::Reg<doep1_dmaaddr::DOEP1_DMAADDR_SPEC>,
151 _reserved60: [u8; 0x08],
152 #[doc = "0x3cb60 - Device OUT Endpoint x+1 Control Register"]
153 pub doep2_ctl: crate::Reg<doep2_ctl::DOEP2_CTL_SPEC>,
154 _reserved61: [u8; 0x04],
155 #[doc = "0x3cb68 - Device OUT Endpoint x+1 Interrupt Register"]
156 pub doep2_int: crate::Reg<doep2_int::DOEP2_INT_SPEC>,
157 _reserved62: [u8; 0x04],
158 #[doc = "0x3cb70 - Device OUT Endpoint x+1 Transfer Size Register"]
159 pub doep2_tsiz: crate::Reg<doep2_tsiz::DOEP2_TSIZ_SPEC>,
160 #[doc = "0x3cb74 - Device OUT Endpoint x+1 DMA Address Register"]
161 pub doep2_dmaaddr: crate::Reg<doep2_dmaaddr::DOEP2_DMAADDR_SPEC>,
162 _reserved64: [u8; 0x0288],
163 #[doc = "0x3ce00 - Power and Clock Gating Control Register"]
164 pub pcgcctl: crate::Reg<pcgcctl::PCGCCTL_SPEC>,
165}
166#[doc = "CTRL register accessor: an alias for `Reg<CTRL_SPEC>`"]
167pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
168#[doc = "System Control Register"]
169pub mod ctrl;
170#[doc = "STATUS register accessor: an alias for `Reg<STATUS_SPEC>`"]
171pub type STATUS = crate::Reg<status::STATUS_SPEC>;
172#[doc = "System Status Register"]
173pub mod status;
174#[doc = "IF register accessor: an alias for `Reg<IF_SPEC>`"]
175pub type IF = crate::Reg<if_::IF_SPEC>;
176#[doc = "Interrupt Flag Register"]
177pub mod if_;
178#[doc = "IFS register accessor: an alias for `Reg<IFS_SPEC>`"]
179pub type IFS = crate::Reg<ifs::IFS_SPEC>;
180#[doc = "Interrupt Flag Set Register"]
181pub mod ifs;
182#[doc = "IFC register accessor: an alias for `Reg<IFC_SPEC>`"]
183pub type IFC = crate::Reg<ifc::IFC_SPEC>;
184#[doc = "Interrupt Flag Clear Register"]
185pub mod ifc;
186#[doc = "IEN register accessor: an alias for `Reg<IEN_SPEC>`"]
187pub type IEN = crate::Reg<ien::IEN_SPEC>;
188#[doc = "Interrupt Enable Register"]
189pub mod ien;
190#[doc = "ROUTE register accessor: an alias for `Reg<ROUTE_SPEC>`"]
191pub type ROUTE = crate::Reg<route::ROUTE_SPEC>;
192#[doc = "I/O Routing Register"]
193pub mod route;
194#[doc = "GAHBCFG register accessor: an alias for `Reg<GAHBCFG_SPEC>`"]
195pub type GAHBCFG = crate::Reg<gahbcfg::GAHBCFG_SPEC>;
196#[doc = "AHB Configuration Register"]
197pub mod gahbcfg;
198#[doc = "GUSBCFG register accessor: an alias for `Reg<GUSBCFG_SPEC>`"]
199pub type GUSBCFG = crate::Reg<gusbcfg::GUSBCFG_SPEC>;
200#[doc = "USB Configuration Register"]
201pub mod gusbcfg;
202#[doc = "GRSTCTL register accessor: an alias for `Reg<GRSTCTL_SPEC>`"]
203pub type GRSTCTL = crate::Reg<grstctl::GRSTCTL_SPEC>;
204#[doc = "Reset Register"]
205pub mod grstctl;
206#[doc = "GINTSTS register accessor: an alias for `Reg<GINTSTS_SPEC>`"]
207pub type GINTSTS = crate::Reg<gintsts::GINTSTS_SPEC>;
208#[doc = "Interrupt Register"]
209pub mod gintsts;
210#[doc = "GINTMSK register accessor: an alias for `Reg<GINTMSK_SPEC>`"]
211pub type GINTMSK = crate::Reg<gintmsk::GINTMSK_SPEC>;
212#[doc = "Interrupt Mask Register"]
213pub mod gintmsk;
214#[doc = "GRXSTSR register accessor: an alias for `Reg<GRXSTSR_SPEC>`"]
215pub type GRXSTSR = crate::Reg<grxstsr::GRXSTSR_SPEC>;
216#[doc = "Receive Status Debug Read Register"]
217pub mod grxstsr;
218#[doc = "GRXSTSP register accessor: an alias for `Reg<GRXSTSP_SPEC>`"]
219pub type GRXSTSP = crate::Reg<grxstsp::GRXSTSP_SPEC>;
220#[doc = "Receive Status Read and Pop Register"]
221pub mod grxstsp;
222#[doc = "GRXFSIZ register accessor: an alias for `Reg<GRXFSIZ_SPEC>`"]
223pub type GRXFSIZ = crate::Reg<grxfsiz::GRXFSIZ_SPEC>;
224#[doc = "Receive FIFO Size Register"]
225pub mod grxfsiz;
226#[doc = "GNPTXFSIZ register accessor: an alias for `Reg<GNPTXFSIZ_SPEC>`"]
227pub type GNPTXFSIZ = crate::Reg<gnptxfsiz::GNPTXFSIZ_SPEC>;
228#[doc = "Non-periodic Transmit FIFO Size Register"]
229pub mod gnptxfsiz;
230#[doc = "GDFIFOCFG register accessor: an alias for `Reg<GDFIFOCFG_SPEC>`"]
231pub type GDFIFOCFG = crate::Reg<gdfifocfg::GDFIFOCFG_SPEC>;
232#[doc = "Global DFIFO Configuration Register"]
233pub mod gdfifocfg;
234#[doc = "DIEPTXF1 register accessor: an alias for `Reg<DIEPTXF1_SPEC>`"]
235pub type DIEPTXF1 = crate::Reg<dieptxf1::DIEPTXF1_SPEC>;
236#[doc = "Device IN Endpoint Transmit FIFO 1 Size Register"]
237pub mod dieptxf1;
238#[doc = "DIEPTXF2 register accessor: an alias for `Reg<DIEPTXF2_SPEC>`"]
239pub type DIEPTXF2 = crate::Reg<dieptxf2::DIEPTXF2_SPEC>;
240#[doc = "Device IN Endpoint Transmit FIFO 2 Size Register"]
241pub mod dieptxf2;
242#[doc = "DIEPTXF3 register accessor: an alias for `Reg<DIEPTXF3_SPEC>`"]
243pub type DIEPTXF3 = crate::Reg<dieptxf3::DIEPTXF3_SPEC>;
244#[doc = "Device IN Endpoint Transmit FIFO 3 Size Register"]
245pub mod dieptxf3;
246#[doc = "DCFG register accessor: an alias for `Reg<DCFG_SPEC>`"]
247pub type DCFG = crate::Reg<dcfg::DCFG_SPEC>;
248#[doc = "Device Configuration Register"]
249pub mod dcfg;
250#[doc = "DCTL register accessor: an alias for `Reg<DCTL_SPEC>`"]
251pub type DCTL = crate::Reg<dctl::DCTL_SPEC>;
252#[doc = "Device Control Register"]
253pub mod dctl;
254#[doc = "DSTS register accessor: an alias for `Reg<DSTS_SPEC>`"]
255pub type DSTS = crate::Reg<dsts::DSTS_SPEC>;
256#[doc = "Device Status Register"]
257pub mod dsts;
258#[doc = "DIEPMSK register accessor: an alias for `Reg<DIEPMSK_SPEC>`"]
259pub type DIEPMSK = crate::Reg<diepmsk::DIEPMSK_SPEC>;
260#[doc = "Device IN Endpoint Common Interrupt Mask Register"]
261pub mod diepmsk;
262#[doc = "DOEPMSK register accessor: an alias for `Reg<DOEPMSK_SPEC>`"]
263pub type DOEPMSK = crate::Reg<doepmsk::DOEPMSK_SPEC>;
264#[doc = "Device OUT Endpoint Common Interrupt Mask Register"]
265pub mod doepmsk;
266#[doc = "DAINT register accessor: an alias for `Reg<DAINT_SPEC>`"]
267pub type DAINT = crate::Reg<daint::DAINT_SPEC>;
268#[doc = "Device All Endpoints Interrupt Register"]
269pub mod daint;
270#[doc = "DAINTMSK register accessor: an alias for `Reg<DAINTMSK_SPEC>`"]
271pub type DAINTMSK = crate::Reg<daintmsk::DAINTMSK_SPEC>;
272#[doc = "Device All Endpoints Interrupt Mask Register"]
273pub mod daintmsk;
274#[doc = "DIEPEMPMSK register accessor: an alias for `Reg<DIEPEMPMSK_SPEC>`"]
275pub type DIEPEMPMSK = crate::Reg<diepempmsk::DIEPEMPMSK_SPEC>;
276#[doc = "Device IN Endpoint FIFO Empty Interrupt Mask Register"]
277pub mod diepempmsk;
278#[doc = "DIEP0CTL register accessor: an alias for `Reg<DIEP0CTL_SPEC>`"]
279pub type DIEP0CTL = crate::Reg<diep0ctl::DIEP0CTL_SPEC>;
280#[doc = "Device IN Endpoint 0 Control Register"]
281pub mod diep0ctl;
282#[doc = "DIEP0INT register accessor: an alias for `Reg<DIEP0INT_SPEC>`"]
283pub type DIEP0INT = crate::Reg<diep0int::DIEP0INT_SPEC>;
284#[doc = "Device IN Endpoint 0 Interrupt Register"]
285pub mod diep0int;
286#[doc = "DIEP0TSIZ register accessor: an alias for `Reg<DIEP0TSIZ_SPEC>`"]
287pub type DIEP0TSIZ = crate::Reg<diep0tsiz::DIEP0TSIZ_SPEC>;
288#[doc = "Device IN Endpoint 0 Transfer Size Register"]
289pub mod diep0tsiz;
290#[doc = "DIEP0DMAADDR register accessor: an alias for `Reg<DIEP0DMAADDR_SPEC>`"]
291pub type DIEP0DMAADDR = crate::Reg<diep0dmaaddr::DIEP0DMAADDR_SPEC>;
292#[doc = "Device IN Endpoint 0 DMA Address Register"]
293pub mod diep0dmaaddr;
294#[doc = "DIEP0TXFSTS register accessor: an alias for `Reg<DIEP0TXFSTS_SPEC>`"]
295pub type DIEP0TXFSTS = crate::Reg<diep0txfsts::DIEP0TXFSTS_SPEC>;
296#[doc = "Device IN Endpoint 0 Transmit FIFO Status Register"]
297pub mod diep0txfsts;
298#[doc = "DIEP0_CTL register accessor: an alias for `Reg<DIEP0_CTL_SPEC>`"]
299pub type DIEP0_CTL = crate::Reg<diep0_ctl::DIEP0_CTL_SPEC>;
300#[doc = "Device IN Endpoint x+1 Control Register"]
301pub mod diep0_ctl;
302#[doc = "DIEP0_INT register accessor: an alias for `Reg<DIEP0_INT_SPEC>`"]
303pub type DIEP0_INT = crate::Reg<diep0_int::DIEP0_INT_SPEC>;
304#[doc = "Device IN Endpoint x+1 Interrupt Register"]
305pub mod diep0_int;
306#[doc = "DIEP0_TSIZ register accessor: an alias for `Reg<DIEP0_TSIZ_SPEC>`"]
307pub type DIEP0_TSIZ = crate::Reg<diep0_tsiz::DIEP0_TSIZ_SPEC>;
308#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
309pub mod diep0_tsiz;
310#[doc = "DIEP0_DMAADDR register accessor: an alias for `Reg<DIEP0_DMAADDR_SPEC>`"]
311pub type DIEP0_DMAADDR = crate::Reg<diep0_dmaaddr::DIEP0_DMAADDR_SPEC>;
312#[doc = "Device IN Endpoint x+1 DMA Address Register"]
313pub mod diep0_dmaaddr;
314#[doc = "DIEP0_TXFSTS register accessor: an alias for `Reg<DIEP0_TXFSTS_SPEC>`"]
315pub type DIEP0_TXFSTS = crate::Reg<diep0_txfsts::DIEP0_TXFSTS_SPEC>;
316#[doc = "Device IN Endpoint x+1 Transmit FIFO Status Register"]
317pub mod diep0_txfsts;
318#[doc = "DIEP1_CTL register accessor: an alias for `Reg<DIEP1_CTL_SPEC>`"]
319pub type DIEP1_CTL = crate::Reg<diep1_ctl::DIEP1_CTL_SPEC>;
320#[doc = "Device IN Endpoint x+1 Control Register"]
321pub mod diep1_ctl;
322#[doc = "DIEP1_INT register accessor: an alias for `Reg<DIEP1_INT_SPEC>`"]
323pub type DIEP1_INT = crate::Reg<diep1_int::DIEP1_INT_SPEC>;
324#[doc = "Device IN Endpoint x+1 Interrupt Register"]
325pub mod diep1_int;
326#[doc = "DIEP1_TSIZ register accessor: an alias for `Reg<DIEP1_TSIZ_SPEC>`"]
327pub type DIEP1_TSIZ = crate::Reg<diep1_tsiz::DIEP1_TSIZ_SPEC>;
328#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
329pub mod diep1_tsiz;
330#[doc = "DIEP1_DMAADDR register accessor: an alias for `Reg<DIEP1_DMAADDR_SPEC>`"]
331pub type DIEP1_DMAADDR = crate::Reg<diep1_dmaaddr::DIEP1_DMAADDR_SPEC>;
332#[doc = "Device IN Endpoint x+1 DMA Address Register"]
333pub mod diep1_dmaaddr;
334#[doc = "DIEP1_TXFSTS register accessor: an alias for `Reg<DIEP1_TXFSTS_SPEC>`"]
335pub type DIEP1_TXFSTS = crate::Reg<diep1_txfsts::DIEP1_TXFSTS_SPEC>;
336#[doc = "Device IN Endpoint x+1 Transmit FIFO Status Register"]
337pub mod diep1_txfsts;
338#[doc = "DIEP2_CTL register accessor: an alias for `Reg<DIEP2_CTL_SPEC>`"]
339pub type DIEP2_CTL = crate::Reg<diep2_ctl::DIEP2_CTL_SPEC>;
340#[doc = "Device IN Endpoint x+1 Control Register"]
341pub mod diep2_ctl;
342#[doc = "DIEP2_INT register accessor: an alias for `Reg<DIEP2_INT_SPEC>`"]
343pub type DIEP2_INT = crate::Reg<diep2_int::DIEP2_INT_SPEC>;
344#[doc = "Device IN Endpoint x+1 Interrupt Register"]
345pub mod diep2_int;
346#[doc = "DIEP2_TSIZ register accessor: an alias for `Reg<DIEP2_TSIZ_SPEC>`"]
347pub type DIEP2_TSIZ = crate::Reg<diep2_tsiz::DIEP2_TSIZ_SPEC>;
348#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
349pub mod diep2_tsiz;
350#[doc = "DIEP2_DMAADDR register accessor: an alias for `Reg<DIEP2_DMAADDR_SPEC>`"]
351pub type DIEP2_DMAADDR = crate::Reg<diep2_dmaaddr::DIEP2_DMAADDR_SPEC>;
352#[doc = "Device IN Endpoint x+1 DMA Address Register"]
353pub mod diep2_dmaaddr;
354#[doc = "DIEP2_TXFSTS register accessor: an alias for `Reg<DIEP2_TXFSTS_SPEC>`"]
355pub type DIEP2_TXFSTS = crate::Reg<diep2_txfsts::DIEP2_TXFSTS_SPEC>;
356#[doc = "Device IN Endpoint x+1 Transmit FIFO Status Register"]
357pub mod diep2_txfsts;
358#[doc = "DOEP0CTL register accessor: an alias for `Reg<DOEP0CTL_SPEC>`"]
359pub type DOEP0CTL = crate::Reg<doep0ctl::DOEP0CTL_SPEC>;
360#[doc = "Device OUT Endpoint 0 Control Register"]
361pub mod doep0ctl;
362#[doc = "DOEP0INT register accessor: an alias for `Reg<DOEP0INT_SPEC>`"]
363pub type DOEP0INT = crate::Reg<doep0int::DOEP0INT_SPEC>;
364#[doc = "Device OUT Endpoint 0 Interrupt Register"]
365pub mod doep0int;
366#[doc = "DOEP0TSIZ register accessor: an alias for `Reg<DOEP0TSIZ_SPEC>`"]
367pub type DOEP0TSIZ = crate::Reg<doep0tsiz::DOEP0TSIZ_SPEC>;
368#[doc = "Device OUT Endpoint 0 Transfer Size Register"]
369pub mod doep0tsiz;
370#[doc = "DOEP0DMAADDR register accessor: an alias for `Reg<DOEP0DMAADDR_SPEC>`"]
371pub type DOEP0DMAADDR = crate::Reg<doep0dmaaddr::DOEP0DMAADDR_SPEC>;
372#[doc = "Device OUT Endpoint 0 DMA Address Register"]
373pub mod doep0dmaaddr;
374#[doc = "DOEP0_CTL register accessor: an alias for `Reg<DOEP0_CTL_SPEC>`"]
375pub type DOEP0_CTL = crate::Reg<doep0_ctl::DOEP0_CTL_SPEC>;
376#[doc = "Device OUT Endpoint x+1 Control Register"]
377pub mod doep0_ctl;
378#[doc = "DOEP0_INT register accessor: an alias for `Reg<DOEP0_INT_SPEC>`"]
379pub type DOEP0_INT = crate::Reg<doep0_int::DOEP0_INT_SPEC>;
380#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
381pub mod doep0_int;
382#[doc = "DOEP0_TSIZ register accessor: an alias for `Reg<DOEP0_TSIZ_SPEC>`"]
383pub type DOEP0_TSIZ = crate::Reg<doep0_tsiz::DOEP0_TSIZ_SPEC>;
384#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
385pub mod doep0_tsiz;
386#[doc = "DOEP0_DMAADDR register accessor: an alias for `Reg<DOEP0_DMAADDR_SPEC>`"]
387pub type DOEP0_DMAADDR = crate::Reg<doep0_dmaaddr::DOEP0_DMAADDR_SPEC>;
388#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
389pub mod doep0_dmaaddr;
390#[doc = "DOEP1_CTL register accessor: an alias for `Reg<DOEP1_CTL_SPEC>`"]
391pub type DOEP1_CTL = crate::Reg<doep1_ctl::DOEP1_CTL_SPEC>;
392#[doc = "Device OUT Endpoint x+1 Control Register"]
393pub mod doep1_ctl;
394#[doc = "DOEP1_INT register accessor: an alias for `Reg<DOEP1_INT_SPEC>`"]
395pub type DOEP1_INT = crate::Reg<doep1_int::DOEP1_INT_SPEC>;
396#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
397pub mod doep1_int;
398#[doc = "DOEP1_TSIZ register accessor: an alias for `Reg<DOEP1_TSIZ_SPEC>`"]
399pub type DOEP1_TSIZ = crate::Reg<doep1_tsiz::DOEP1_TSIZ_SPEC>;
400#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
401pub mod doep1_tsiz;
402#[doc = "DOEP1_DMAADDR register accessor: an alias for `Reg<DOEP1_DMAADDR_SPEC>`"]
403pub type DOEP1_DMAADDR = crate::Reg<doep1_dmaaddr::DOEP1_DMAADDR_SPEC>;
404#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
405pub mod doep1_dmaaddr;
406#[doc = "DOEP2_CTL register accessor: an alias for `Reg<DOEP2_CTL_SPEC>`"]
407pub type DOEP2_CTL = crate::Reg<doep2_ctl::DOEP2_CTL_SPEC>;
408#[doc = "Device OUT Endpoint x+1 Control Register"]
409pub mod doep2_ctl;
410#[doc = "DOEP2_INT register accessor: an alias for `Reg<DOEP2_INT_SPEC>`"]
411pub type DOEP2_INT = crate::Reg<doep2_int::DOEP2_INT_SPEC>;
412#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
413pub mod doep2_int;
414#[doc = "DOEP2_TSIZ register accessor: an alias for `Reg<DOEP2_TSIZ_SPEC>`"]
415pub type DOEP2_TSIZ = crate::Reg<doep2_tsiz::DOEP2_TSIZ_SPEC>;
416#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
417pub mod doep2_tsiz;
418#[doc = "DOEP2_DMAADDR register accessor: an alias for `Reg<DOEP2_DMAADDR_SPEC>`"]
419pub type DOEP2_DMAADDR = crate::Reg<doep2_dmaaddr::DOEP2_DMAADDR_SPEC>;
420#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
421pub mod doep2_dmaaddr;
422#[doc = "PCGCCTL register accessor: an alias for `Reg<PCGCCTL_SPEC>`"]
423pub type PCGCCTL = crate::Reg<pcgcctl::PCGCCTL_SPEC>;
424#[doc = "Power and Clock Gating Control Register"]
425pub mod pcgcctl;