efm32gg995_pac/usb/
hc2_intmsk.rs1#[doc = "Register `HC2_INTMSK` reader"]
2pub struct R(crate::R<HC2_INTMSK_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HC2_INTMSK_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HC2_INTMSK_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HC2_INTMSK_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HC2_INTMSK` writer"]
17pub struct W(crate::W<HC2_INTMSK_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HC2_INTMSK_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HC2_INTMSK_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HC2_INTMSK_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `XFERCOMPLMSK` reader - Transfer Completed Mask"]
38pub type XFERCOMPLMSK_R = crate::BitReader<bool>;
39#[doc = "Field `XFERCOMPLMSK` writer - Transfer Completed Mask"]
40pub type XFERCOMPLMSK_W<'a> = crate::BitWriter<'a, u32, HC2_INTMSK_SPEC, bool, 0>;
41#[doc = "Field `CHHLTDMSK` reader - Channel Halted Mask"]
42pub type CHHLTDMSK_R = crate::BitReader<bool>;
43#[doc = "Field `CHHLTDMSK` writer - Channel Halted Mask"]
44pub type CHHLTDMSK_W<'a> = crate::BitWriter<'a, u32, HC2_INTMSK_SPEC, bool, 1>;
45#[doc = "Field `AHBERRMSK` reader - AHB Error Mask"]
46pub type AHBERRMSK_R = crate::BitReader<bool>;
47#[doc = "Field `AHBERRMSK` writer - AHB Error Mask"]
48pub type AHBERRMSK_W<'a> = crate::BitWriter<'a, u32, HC2_INTMSK_SPEC, bool, 2>;
49#[doc = "Field `STALLMSK` reader - STALL Response Received Interrupt Mask"]
50pub type STALLMSK_R = crate::BitReader<bool>;
51#[doc = "Field `STALLMSK` writer - STALL Response Received Interrupt Mask"]
52pub type STALLMSK_W<'a> = crate::BitWriter<'a, u32, HC2_INTMSK_SPEC, bool, 3>;
53#[doc = "Field `NAKMSK` reader - NAK Response Received Interrupt Mask"]
54pub type NAKMSK_R = crate::BitReader<bool>;
55#[doc = "Field `NAKMSK` writer - NAK Response Received Interrupt Mask"]
56pub type NAKMSK_W<'a> = crate::BitWriter<'a, u32, HC2_INTMSK_SPEC, bool, 4>;
57#[doc = "Field `ACKMSK` reader - ACK Response Received/Transmitted Interrupt Mask"]
58pub type ACKMSK_R = crate::BitReader<bool>;
59#[doc = "Field `ACKMSK` writer - ACK Response Received/Transmitted Interrupt Mask"]
60pub type ACKMSK_W<'a> = crate::BitWriter<'a, u32, HC2_INTMSK_SPEC, bool, 5>;
61#[doc = "Field `XACTERRMSK` reader - Transaction Error Mask"]
62pub type XACTERRMSK_R = crate::BitReader<bool>;
63#[doc = "Field `XACTERRMSK` writer - Transaction Error Mask"]
64pub type XACTERRMSK_W<'a> = crate::BitWriter<'a, u32, HC2_INTMSK_SPEC, bool, 7>;
65#[doc = "Field `BBLERRMSK` reader - Babble Error Mask"]
66pub type BBLERRMSK_R = crate::BitReader<bool>;
67#[doc = "Field `BBLERRMSK` writer - Babble Error Mask"]
68pub type BBLERRMSK_W<'a> = crate::BitWriter<'a, u32, HC2_INTMSK_SPEC, bool, 8>;
69#[doc = "Field `FRMOVRUNMSK` reader - Frame Overrun Mask"]
70pub type FRMOVRUNMSK_R = crate::BitReader<bool>;
71#[doc = "Field `FRMOVRUNMSK` writer - Frame Overrun Mask"]
72pub type FRMOVRUNMSK_W<'a> = crate::BitWriter<'a, u32, HC2_INTMSK_SPEC, bool, 9>;
73#[doc = "Field `DATATGLERRMSK` reader - Data Toggle Error Mask"]
74pub type DATATGLERRMSK_R = crate::BitReader<bool>;
75#[doc = "Field `DATATGLERRMSK` writer - Data Toggle Error Mask"]
76pub type DATATGLERRMSK_W<'a> = crate::BitWriter<'a, u32, HC2_INTMSK_SPEC, bool, 10>;
77impl R {
78 #[doc = "Bit 0 - Transfer Completed Mask"]
79 #[inline(always)]
80 pub fn xfercomplmsk(&self) -> XFERCOMPLMSK_R {
81 XFERCOMPLMSK_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 1 - Channel Halted Mask"]
84 #[inline(always)]
85 pub fn chhltdmsk(&self) -> CHHLTDMSK_R {
86 CHHLTDMSK_R::new(((self.bits >> 1) & 1) != 0)
87 }
88 #[doc = "Bit 2 - AHB Error Mask"]
89 #[inline(always)]
90 pub fn ahberrmsk(&self) -> AHBERRMSK_R {
91 AHBERRMSK_R::new(((self.bits >> 2) & 1) != 0)
92 }
93 #[doc = "Bit 3 - STALL Response Received Interrupt Mask"]
94 #[inline(always)]
95 pub fn stallmsk(&self) -> STALLMSK_R {
96 STALLMSK_R::new(((self.bits >> 3) & 1) != 0)
97 }
98 #[doc = "Bit 4 - NAK Response Received Interrupt Mask"]
99 #[inline(always)]
100 pub fn nakmsk(&self) -> NAKMSK_R {
101 NAKMSK_R::new(((self.bits >> 4) & 1) != 0)
102 }
103 #[doc = "Bit 5 - ACK Response Received/Transmitted Interrupt Mask"]
104 #[inline(always)]
105 pub fn ackmsk(&self) -> ACKMSK_R {
106 ACKMSK_R::new(((self.bits >> 5) & 1) != 0)
107 }
108 #[doc = "Bit 7 - Transaction Error Mask"]
109 #[inline(always)]
110 pub fn xacterrmsk(&self) -> XACTERRMSK_R {
111 XACTERRMSK_R::new(((self.bits >> 7) & 1) != 0)
112 }
113 #[doc = "Bit 8 - Babble Error Mask"]
114 #[inline(always)]
115 pub fn bblerrmsk(&self) -> BBLERRMSK_R {
116 BBLERRMSK_R::new(((self.bits >> 8) & 1) != 0)
117 }
118 #[doc = "Bit 9 - Frame Overrun Mask"]
119 #[inline(always)]
120 pub fn frmovrunmsk(&self) -> FRMOVRUNMSK_R {
121 FRMOVRUNMSK_R::new(((self.bits >> 9) & 1) != 0)
122 }
123 #[doc = "Bit 10 - Data Toggle Error Mask"]
124 #[inline(always)]
125 pub fn datatglerrmsk(&self) -> DATATGLERRMSK_R {
126 DATATGLERRMSK_R::new(((self.bits >> 10) & 1) != 0)
127 }
128}
129impl W {
130 #[doc = "Bit 0 - Transfer Completed Mask"]
131 #[inline(always)]
132 pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W {
133 XFERCOMPLMSK_W::new(self)
134 }
135 #[doc = "Bit 1 - Channel Halted Mask"]
136 #[inline(always)]
137 pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W {
138 CHHLTDMSK_W::new(self)
139 }
140 #[doc = "Bit 2 - AHB Error Mask"]
141 #[inline(always)]
142 pub fn ahberrmsk(&mut self) -> AHBERRMSK_W {
143 AHBERRMSK_W::new(self)
144 }
145 #[doc = "Bit 3 - STALL Response Received Interrupt Mask"]
146 #[inline(always)]
147 pub fn stallmsk(&mut self) -> STALLMSK_W {
148 STALLMSK_W::new(self)
149 }
150 #[doc = "Bit 4 - NAK Response Received Interrupt Mask"]
151 #[inline(always)]
152 pub fn nakmsk(&mut self) -> NAKMSK_W {
153 NAKMSK_W::new(self)
154 }
155 #[doc = "Bit 5 - ACK Response Received/Transmitted Interrupt Mask"]
156 #[inline(always)]
157 pub fn ackmsk(&mut self) -> ACKMSK_W {
158 ACKMSK_W::new(self)
159 }
160 #[doc = "Bit 7 - Transaction Error Mask"]
161 #[inline(always)]
162 pub fn xacterrmsk(&mut self) -> XACTERRMSK_W {
163 XACTERRMSK_W::new(self)
164 }
165 #[doc = "Bit 8 - Babble Error Mask"]
166 #[inline(always)]
167 pub fn bblerrmsk(&mut self) -> BBLERRMSK_W {
168 BBLERRMSK_W::new(self)
169 }
170 #[doc = "Bit 9 - Frame Overrun Mask"]
171 #[inline(always)]
172 pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W {
173 FRMOVRUNMSK_W::new(self)
174 }
175 #[doc = "Bit 10 - Data Toggle Error Mask"]
176 #[inline(always)]
177 pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W {
178 DATATGLERRMSK_W::new(self)
179 }
180 #[doc = "Writes raw bits to the register."]
181 #[inline(always)]
182 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
183 self.0.bits(bits);
184 self
185 }
186}
187#[doc = "Host Channel x Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc2_intmsk](index.html) module"]
188pub struct HC2_INTMSK_SPEC;
189impl crate::RegisterSpec for HC2_INTMSK_SPEC {
190 type Ux = u32;
191}
192#[doc = "`read()` method returns [hc2_intmsk::R](R) reader structure"]
193impl crate::Readable for HC2_INTMSK_SPEC {
194 type Reader = R;
195}
196#[doc = "`write(|w| ..)` method takes [hc2_intmsk::W](W) writer structure"]
197impl crate::Writable for HC2_INTMSK_SPEC {
198 type Writer = W;
199}
200#[doc = "`reset()` method sets HC2_INTMSK to value 0"]
201impl crate::Resettable for HC2_INTMSK_SPEC {
202 #[inline(always)]
203 fn reset_value() -> Self::Ux {
204 0
205 }
206}