efm32gg942_pac/prs/
ch7_ctrl.rs

1#[doc = "Register `CH7_CTRL` reader"]
2pub struct R(crate::R<CH7_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH7_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH7_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH7_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH7_CTRL` writer"]
17pub struct W(crate::W<CH7_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH7_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH7_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH7_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "3: Analog Comparator 1"]
52    ACMP1 = 3,
53    #[doc = "6: Digital to Analog Converter 0"]
54    DAC0 = 6,
55    #[doc = "8: Analog to Digital Converter 0"]
56    ADC0 = 8,
57    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
58    USART0 = 16,
59    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
60    USART1 = 17,
61    #[doc = "18: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
62    USART2 = 18,
63    #[doc = "28: Timer 0"]
64    TIMER0 = 28,
65    #[doc = "29: Timer 1"]
66    TIMER1 = 29,
67    #[doc = "30: Timer 2"]
68    TIMER2 = 30,
69    #[doc = "31: Timer 3"]
70    TIMER3 = 31,
71    #[doc = "36: Universal Serial Bus Interface"]
72    USB = 36,
73    #[doc = "40: Real-Time Counter"]
74    RTC = 40,
75    #[doc = "48: General purpose Input/Output"]
76    GPIOL = 48,
77    #[doc = "49: General purpose Input/Output"]
78    GPIOH = 49,
79    #[doc = "52: Low Energy Timer 0"]
80    LETIMER0 = 52,
81    #[doc = "55: Backup RTC"]
82    BURTC = 55,
83    #[doc = "57: Low Energy Sensor Interface"]
84    LESENSEL = 57,
85    #[doc = "58: Low Energy Sensor Interface"]
86    LESENSEH = 58,
87    #[doc = "59: Low Energy Sensor Interface"]
88    LESENSED = 59,
89}
90impl From<SOURCESEL_A> for u8 {
91    #[inline(always)]
92    fn from(variant: SOURCESEL_A) -> Self {
93        variant as _
94    }
95}
96#[doc = "Field `SOURCESEL` reader - Source Select"]
97pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
98impl SOURCESEL_R {
99    #[doc = "Get enumerated values variant"]
100    #[inline(always)]
101    pub fn variant(&self) -> Option<SOURCESEL_A> {
102        match self.bits {
103            0 => Some(SOURCESEL_A::NONE),
104            1 => Some(SOURCESEL_A::VCMP),
105            2 => Some(SOURCESEL_A::ACMP0),
106            3 => Some(SOURCESEL_A::ACMP1),
107            6 => Some(SOURCESEL_A::DAC0),
108            8 => Some(SOURCESEL_A::ADC0),
109            16 => Some(SOURCESEL_A::USART0),
110            17 => Some(SOURCESEL_A::USART1),
111            18 => Some(SOURCESEL_A::USART2),
112            28 => Some(SOURCESEL_A::TIMER0),
113            29 => Some(SOURCESEL_A::TIMER1),
114            30 => Some(SOURCESEL_A::TIMER2),
115            31 => Some(SOURCESEL_A::TIMER3),
116            36 => Some(SOURCESEL_A::USB),
117            40 => Some(SOURCESEL_A::RTC),
118            48 => Some(SOURCESEL_A::GPIOL),
119            49 => Some(SOURCESEL_A::GPIOH),
120            52 => Some(SOURCESEL_A::LETIMER0),
121            55 => Some(SOURCESEL_A::BURTC),
122            57 => Some(SOURCESEL_A::LESENSEL),
123            58 => Some(SOURCESEL_A::LESENSEH),
124            59 => Some(SOURCESEL_A::LESENSED),
125            _ => None,
126        }
127    }
128    #[doc = "Checks if the value of the field is `NONE`"]
129    #[inline(always)]
130    pub fn is_none(&self) -> bool {
131        *self == SOURCESEL_A::NONE
132    }
133    #[doc = "Checks if the value of the field is `VCMP`"]
134    #[inline(always)]
135    pub fn is_vcmp(&self) -> bool {
136        *self == SOURCESEL_A::VCMP
137    }
138    #[doc = "Checks if the value of the field is `ACMP0`"]
139    #[inline(always)]
140    pub fn is_acmp0(&self) -> bool {
141        *self == SOURCESEL_A::ACMP0
142    }
143    #[doc = "Checks if the value of the field is `ACMP1`"]
144    #[inline(always)]
145    pub fn is_acmp1(&self) -> bool {
146        *self == SOURCESEL_A::ACMP1
147    }
148    #[doc = "Checks if the value of the field is `DAC0`"]
149    #[inline(always)]
150    pub fn is_dac0(&self) -> bool {
151        *self == SOURCESEL_A::DAC0
152    }
153    #[doc = "Checks if the value of the field is `ADC0`"]
154    #[inline(always)]
155    pub fn is_adc0(&self) -> bool {
156        *self == SOURCESEL_A::ADC0
157    }
158    #[doc = "Checks if the value of the field is `USART0`"]
159    #[inline(always)]
160    pub fn is_usart0(&self) -> bool {
161        *self == SOURCESEL_A::USART0
162    }
163    #[doc = "Checks if the value of the field is `USART1`"]
164    #[inline(always)]
165    pub fn is_usart1(&self) -> bool {
166        *self == SOURCESEL_A::USART1
167    }
168    #[doc = "Checks if the value of the field is `USART2`"]
169    #[inline(always)]
170    pub fn is_usart2(&self) -> bool {
171        *self == SOURCESEL_A::USART2
172    }
173    #[doc = "Checks if the value of the field is `TIMER0`"]
174    #[inline(always)]
175    pub fn is_timer0(&self) -> bool {
176        *self == SOURCESEL_A::TIMER0
177    }
178    #[doc = "Checks if the value of the field is `TIMER1`"]
179    #[inline(always)]
180    pub fn is_timer1(&self) -> bool {
181        *self == SOURCESEL_A::TIMER1
182    }
183    #[doc = "Checks if the value of the field is `TIMER2`"]
184    #[inline(always)]
185    pub fn is_timer2(&self) -> bool {
186        *self == SOURCESEL_A::TIMER2
187    }
188    #[doc = "Checks if the value of the field is `TIMER3`"]
189    #[inline(always)]
190    pub fn is_timer3(&self) -> bool {
191        *self == SOURCESEL_A::TIMER3
192    }
193    #[doc = "Checks if the value of the field is `USB`"]
194    #[inline(always)]
195    pub fn is_usb(&self) -> bool {
196        *self == SOURCESEL_A::USB
197    }
198    #[doc = "Checks if the value of the field is `RTC`"]
199    #[inline(always)]
200    pub fn is_rtc(&self) -> bool {
201        *self == SOURCESEL_A::RTC
202    }
203    #[doc = "Checks if the value of the field is `GPIOL`"]
204    #[inline(always)]
205    pub fn is_gpiol(&self) -> bool {
206        *self == SOURCESEL_A::GPIOL
207    }
208    #[doc = "Checks if the value of the field is `GPIOH`"]
209    #[inline(always)]
210    pub fn is_gpioh(&self) -> bool {
211        *self == SOURCESEL_A::GPIOH
212    }
213    #[doc = "Checks if the value of the field is `LETIMER0`"]
214    #[inline(always)]
215    pub fn is_letimer0(&self) -> bool {
216        *self == SOURCESEL_A::LETIMER0
217    }
218    #[doc = "Checks if the value of the field is `BURTC`"]
219    #[inline(always)]
220    pub fn is_burtc(&self) -> bool {
221        *self == SOURCESEL_A::BURTC
222    }
223    #[doc = "Checks if the value of the field is `LESENSEL`"]
224    #[inline(always)]
225    pub fn is_lesensel(&self) -> bool {
226        *self == SOURCESEL_A::LESENSEL
227    }
228    #[doc = "Checks if the value of the field is `LESENSEH`"]
229    #[inline(always)]
230    pub fn is_lesenseh(&self) -> bool {
231        *self == SOURCESEL_A::LESENSEH
232    }
233    #[doc = "Checks if the value of the field is `LESENSED`"]
234    #[inline(always)]
235    pub fn is_lesensed(&self) -> bool {
236        *self == SOURCESEL_A::LESENSED
237    }
238}
239#[doc = "Field `SOURCESEL` writer - Source Select"]
240pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
241impl<'a> SOURCESEL_W<'a> {
242    #[doc = "No source selected"]
243    #[inline(always)]
244    pub fn none(self) -> &'a mut W {
245        self.variant(SOURCESEL_A::NONE)
246    }
247    #[doc = "Voltage Comparator"]
248    #[inline(always)]
249    pub fn vcmp(self) -> &'a mut W {
250        self.variant(SOURCESEL_A::VCMP)
251    }
252    #[doc = "Analog Comparator 0"]
253    #[inline(always)]
254    pub fn acmp0(self) -> &'a mut W {
255        self.variant(SOURCESEL_A::ACMP0)
256    }
257    #[doc = "Analog Comparator 1"]
258    #[inline(always)]
259    pub fn acmp1(self) -> &'a mut W {
260        self.variant(SOURCESEL_A::ACMP1)
261    }
262    #[doc = "Digital to Analog Converter 0"]
263    #[inline(always)]
264    pub fn dac0(self) -> &'a mut W {
265        self.variant(SOURCESEL_A::DAC0)
266    }
267    #[doc = "Analog to Digital Converter 0"]
268    #[inline(always)]
269    pub fn adc0(self) -> &'a mut W {
270        self.variant(SOURCESEL_A::ADC0)
271    }
272    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
273    #[inline(always)]
274    pub fn usart0(self) -> &'a mut W {
275        self.variant(SOURCESEL_A::USART0)
276    }
277    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
278    #[inline(always)]
279    pub fn usart1(self) -> &'a mut W {
280        self.variant(SOURCESEL_A::USART1)
281    }
282    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
283    #[inline(always)]
284    pub fn usart2(self) -> &'a mut W {
285        self.variant(SOURCESEL_A::USART2)
286    }
287    #[doc = "Timer 0"]
288    #[inline(always)]
289    pub fn timer0(self) -> &'a mut W {
290        self.variant(SOURCESEL_A::TIMER0)
291    }
292    #[doc = "Timer 1"]
293    #[inline(always)]
294    pub fn timer1(self) -> &'a mut W {
295        self.variant(SOURCESEL_A::TIMER1)
296    }
297    #[doc = "Timer 2"]
298    #[inline(always)]
299    pub fn timer2(self) -> &'a mut W {
300        self.variant(SOURCESEL_A::TIMER2)
301    }
302    #[doc = "Timer 3"]
303    #[inline(always)]
304    pub fn timer3(self) -> &'a mut W {
305        self.variant(SOURCESEL_A::TIMER3)
306    }
307    #[doc = "Universal Serial Bus Interface"]
308    #[inline(always)]
309    pub fn usb(self) -> &'a mut W {
310        self.variant(SOURCESEL_A::USB)
311    }
312    #[doc = "Real-Time Counter"]
313    #[inline(always)]
314    pub fn rtc(self) -> &'a mut W {
315        self.variant(SOURCESEL_A::RTC)
316    }
317    #[doc = "General purpose Input/Output"]
318    #[inline(always)]
319    pub fn gpiol(self) -> &'a mut W {
320        self.variant(SOURCESEL_A::GPIOL)
321    }
322    #[doc = "General purpose Input/Output"]
323    #[inline(always)]
324    pub fn gpioh(self) -> &'a mut W {
325        self.variant(SOURCESEL_A::GPIOH)
326    }
327    #[doc = "Low Energy Timer 0"]
328    #[inline(always)]
329    pub fn letimer0(self) -> &'a mut W {
330        self.variant(SOURCESEL_A::LETIMER0)
331    }
332    #[doc = "Backup RTC"]
333    #[inline(always)]
334    pub fn burtc(self) -> &'a mut W {
335        self.variant(SOURCESEL_A::BURTC)
336    }
337    #[doc = "Low Energy Sensor Interface"]
338    #[inline(always)]
339    pub fn lesensel(self) -> &'a mut W {
340        self.variant(SOURCESEL_A::LESENSEL)
341    }
342    #[doc = "Low Energy Sensor Interface"]
343    #[inline(always)]
344    pub fn lesenseh(self) -> &'a mut W {
345        self.variant(SOURCESEL_A::LESENSEH)
346    }
347    #[doc = "Low Energy Sensor Interface"]
348    #[inline(always)]
349    pub fn lesensed(self) -> &'a mut W {
350        self.variant(SOURCESEL_A::LESENSED)
351    }
352}
353#[doc = "Edge Detect Select\n\nValue on reset: 0"]
354#[derive(Clone, Copy, Debug, PartialEq)]
355#[repr(u8)]
356pub enum EDSEL_A {
357    #[doc = "0: Signal is left as it is"]
358    OFF = 0,
359    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
360    POSEDGE = 1,
361    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
362    NEGEDGE = 2,
363    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
364    BOTHEDGES = 3,
365}
366impl From<EDSEL_A> for u8 {
367    #[inline(always)]
368    fn from(variant: EDSEL_A) -> Self {
369        variant as _
370    }
371}
372#[doc = "Field `EDSEL` reader - Edge Detect Select"]
373pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
374impl EDSEL_R {
375    #[doc = "Get enumerated values variant"]
376    #[inline(always)]
377    pub fn variant(&self) -> EDSEL_A {
378        match self.bits {
379            0 => EDSEL_A::OFF,
380            1 => EDSEL_A::POSEDGE,
381            2 => EDSEL_A::NEGEDGE,
382            3 => EDSEL_A::BOTHEDGES,
383            _ => unreachable!(),
384        }
385    }
386    #[doc = "Checks if the value of the field is `OFF`"]
387    #[inline(always)]
388    pub fn is_off(&self) -> bool {
389        *self == EDSEL_A::OFF
390    }
391    #[doc = "Checks if the value of the field is `POSEDGE`"]
392    #[inline(always)]
393    pub fn is_posedge(&self) -> bool {
394        *self == EDSEL_A::POSEDGE
395    }
396    #[doc = "Checks if the value of the field is `NEGEDGE`"]
397    #[inline(always)]
398    pub fn is_negedge(&self) -> bool {
399        *self == EDSEL_A::NEGEDGE
400    }
401    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
402    #[inline(always)]
403    pub fn is_bothedges(&self) -> bool {
404        *self == EDSEL_A::BOTHEDGES
405    }
406}
407#[doc = "Field `EDSEL` writer - Edge Detect Select"]
408pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH7_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
409impl<'a> EDSEL_W<'a> {
410    #[doc = "Signal is left as it is"]
411    #[inline(always)]
412    pub fn off(self) -> &'a mut W {
413        self.variant(EDSEL_A::OFF)
414    }
415    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
416    #[inline(always)]
417    pub fn posedge(self) -> &'a mut W {
418        self.variant(EDSEL_A::POSEDGE)
419    }
420    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
421    #[inline(always)]
422    pub fn negedge(self) -> &'a mut W {
423        self.variant(EDSEL_A::NEGEDGE)
424    }
425    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
426    #[inline(always)]
427    pub fn bothedges(self) -> &'a mut W {
428        self.variant(EDSEL_A::BOTHEDGES)
429    }
430}
431#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
432pub type ASYNC_R = crate::BitReader<bool>;
433#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
434pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, 28>;
435impl R {
436    #[doc = "Bits 0:2 - Signal Select"]
437    #[inline(always)]
438    pub fn sigsel(&self) -> SIGSEL_R {
439        SIGSEL_R::new((self.bits & 7) as u8)
440    }
441    #[doc = "Bits 16:21 - Source Select"]
442    #[inline(always)]
443    pub fn sourcesel(&self) -> SOURCESEL_R {
444        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
445    }
446    #[doc = "Bits 24:25 - Edge Detect Select"]
447    #[inline(always)]
448    pub fn edsel(&self) -> EDSEL_R {
449        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
450    }
451    #[doc = "Bit 28 - Asynchronous reflex"]
452    #[inline(always)]
453    pub fn async_(&self) -> ASYNC_R {
454        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
455    }
456}
457impl W {
458    #[doc = "Bits 0:2 - Signal Select"]
459    #[inline(always)]
460    pub fn sigsel(&mut self) -> SIGSEL_W {
461        SIGSEL_W::new(self)
462    }
463    #[doc = "Bits 16:21 - Source Select"]
464    #[inline(always)]
465    pub fn sourcesel(&mut self) -> SOURCESEL_W {
466        SOURCESEL_W::new(self)
467    }
468    #[doc = "Bits 24:25 - Edge Detect Select"]
469    #[inline(always)]
470    pub fn edsel(&mut self) -> EDSEL_W {
471        EDSEL_W::new(self)
472    }
473    #[doc = "Bit 28 - Asynchronous reflex"]
474    #[inline(always)]
475    pub fn async_(&mut self) -> ASYNC_W {
476        ASYNC_W::new(self)
477    }
478    #[doc = "Writes raw bits to the register."]
479    #[inline(always)]
480    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
481        self.0.bits(bits);
482        self
483    }
484}
485#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch7_ctrl](index.html) module"]
486pub struct CH7_CTRL_SPEC;
487impl crate::RegisterSpec for CH7_CTRL_SPEC {
488    type Ux = u32;
489}
490#[doc = "`read()` method returns [ch7_ctrl::R](R) reader structure"]
491impl crate::Readable for CH7_CTRL_SPEC {
492    type Reader = R;
493}
494#[doc = "`write(|w| ..)` method takes [ch7_ctrl::W](W) writer structure"]
495impl crate::Writable for CH7_CTRL_SPEC {
496    type Writer = W;
497}
498#[doc = "`reset()` method sets CH7_CTRL to value 0"]
499impl crate::Resettable for CH7_CTRL_SPEC {
500    #[inline(always)]
501    fn reset_value() -> Self::Ux {
502        0
503    }
504}
efm32gg942_pac/prs/ch7_ctrl.rs

efm32gg942_pac/prs/
ch7_ctrl.rs
