efm32gg942-pac 0.1.0

Peripheral access API for EFM32GG942 MCU (generated using svd2rust)
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108

#[doc = "Register `DIEP3_TSIZ` reader"]
pub struct R(crate::R<DIEP3_TSIZ_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<DIEP3_TSIZ_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<DIEP3_TSIZ_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<DIEP3_TSIZ_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `DIEP3_TSIZ` writer"]
pub struct W(crate::W<DIEP3_TSIZ_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<DIEP3_TSIZ_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<DIEP3_TSIZ_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<DIEP3_TSIZ_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `XFERSIZE` reader - Transfer Size"]
pub type XFERSIZE_R = crate::FieldReader<u32, u32>;
#[doc = "Field `XFERSIZE` writer - Transfer Size"]
pub type XFERSIZE_W<'a> = crate::FieldWriter<'a, u32, DIEP3_TSIZ_SPEC, u32, u32, 19, 0>;
#[doc = "Field `PKTCNT` reader - Packet Count"]
pub type PKTCNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `PKTCNT` writer - Packet Count"]
pub type PKTCNT_W<'a> = crate::FieldWriter<'a, u32, DIEP3_TSIZ_SPEC, u16, u16, 10, 19>;
#[doc = "Field `MC` reader - Multi Count"]
pub type MC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MC` writer - Multi Count"]
pub type MC_W<'a> = crate::FieldWriter<'a, u32, DIEP3_TSIZ_SPEC, u8, u8, 2, 29>;
impl R {
    #[doc = "Bits 0:18 - Transfer Size"]
    #[inline(always)]
    pub fn xfersize(&self) -> XFERSIZE_R {
        XFERSIZE_R::new((self.bits & 0x0007_ffff) as u32)
    }
    #[doc = "Bits 19:28 - Packet Count"]
    #[inline(always)]
    pub fn pktcnt(&self) -> PKTCNT_R {
        PKTCNT_R::new(((self.bits >> 19) & 0x03ff) as u16)
    }
    #[doc = "Bits 29:30 - Multi Count"]
    #[inline(always)]
    pub fn mc(&self) -> MC_R {
        MC_R::new(((self.bits >> 29) & 3) as u8)
    }
}
impl W {
    #[doc = "Bits 0:18 - Transfer Size"]
    #[inline(always)]
    pub fn xfersize(&mut self) -> XFERSIZE_W {
        XFERSIZE_W::new(self)
    }
    #[doc = "Bits 19:28 - Packet Count"]
    #[inline(always)]
    pub fn pktcnt(&mut self) -> PKTCNT_W {
        PKTCNT_W::new(self)
    }
    #[doc = "Bits 29:30 - Multi Count"]
    #[inline(always)]
    pub fn mc(&mut self) -> MC_W {
        MC_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "Device IN Endpoint x+1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep3_tsiz](index.html) module"]
pub struct DIEP3_TSIZ_SPEC;
impl crate::RegisterSpec for DIEP3_TSIZ_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [diep3_tsiz::R](R) reader structure"]
impl crate::Readable for DIEP3_TSIZ_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [diep3_tsiz::W](W) writer structure"]
impl crate::Writable for DIEP3_TSIZ_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets DIEP3_TSIZ to value 0"]
impl crate::Resettable for DIEP3_TSIZ_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}