1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `SYNC` reader - USART Synchronous Mode"]
38pub type SYNC_R = crate::BitReader<bool>;
39#[doc = "Field `SYNC` writer - USART Synchronous Mode"]
40pub type SYNC_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `LOOPBK` reader - Loopback Enable"]
42pub type LOOPBK_R = crate::BitReader<bool>;
43#[doc = "Field `LOOPBK` writer - Loopback Enable"]
44pub type LOOPBK_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 1>;
45#[doc = "Field `CCEN` reader - Collision Check Enable"]
46pub type CCEN_R = crate::BitReader<bool>;
47#[doc = "Field `CCEN` writer - Collision Check Enable"]
48pub type CCEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
49#[doc = "Field `MPM` reader - Multi-Processor Mode"]
50pub type MPM_R = crate::BitReader<bool>;
51#[doc = "Field `MPM` writer - Multi-Processor Mode"]
52pub type MPM_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
53#[doc = "Field `MPAB` reader - Multi-Processor Address-Bit"]
54pub type MPAB_R = crate::BitReader<bool>;
55#[doc = "Field `MPAB` writer - Multi-Processor Address-Bit"]
56pub type MPAB_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 4>;
57#[doc = "Oversampling\n\nValue on reset: 0"]
58#[derive(Clone, Copy, Debug, PartialEq)]
59#[repr(u8)]
60pub enum OVS_A {
61 #[doc = "0: Regular UART mode with 16X oversampling in asynchronous mode"]
62 X16 = 0,
63 #[doc = "1: Double speed with 8X oversampling in asynchronous mode"]
64 X8 = 1,
65 #[doc = "2: 6X oversampling in asynchronous mode"]
66 X6 = 2,
67 #[doc = "3: Quadruple speed with 4X oversampling in asynchronous mode"]
68 X4 = 3,
69}
70impl From<OVS_A> for u8 {
71 #[inline(always)]
72 fn from(variant: OVS_A) -> Self {
73 variant as _
74 }
75}
76#[doc = "Field `OVS` reader - Oversampling"]
77pub type OVS_R = crate::FieldReader<u8, OVS_A>;
78impl OVS_R {
79 #[doc = "Get enumerated values variant"]
80 #[inline(always)]
81 pub fn variant(&self) -> OVS_A {
82 match self.bits {
83 0 => OVS_A::X16,
84 1 => OVS_A::X8,
85 2 => OVS_A::X6,
86 3 => OVS_A::X4,
87 _ => unreachable!(),
88 }
89 }
90 #[doc = "Checks if the value of the field is `X16`"]
91 #[inline(always)]
92 pub fn is_x16(&self) -> bool {
93 *self == OVS_A::X16
94 }
95 #[doc = "Checks if the value of the field is `X8`"]
96 #[inline(always)]
97 pub fn is_x8(&self) -> bool {
98 *self == OVS_A::X8
99 }
100 #[doc = "Checks if the value of the field is `X6`"]
101 #[inline(always)]
102 pub fn is_x6(&self) -> bool {
103 *self == OVS_A::X6
104 }
105 #[doc = "Checks if the value of the field is `X4`"]
106 #[inline(always)]
107 pub fn is_x4(&self) -> bool {
108 *self == OVS_A::X4
109 }
110}
111#[doc = "Field `OVS` writer - Oversampling"]
112pub type OVS_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, OVS_A, 2, 5>;
113impl<'a> OVS_W<'a> {
114 #[doc = "Regular UART mode with 16X oversampling in asynchronous mode"]
115 #[inline(always)]
116 pub fn x16(self) -> &'a mut W {
117 self.variant(OVS_A::X16)
118 }
119 #[doc = "Double speed with 8X oversampling in asynchronous mode"]
120 #[inline(always)]
121 pub fn x8(self) -> &'a mut W {
122 self.variant(OVS_A::X8)
123 }
124 #[doc = "6X oversampling in asynchronous mode"]
125 #[inline(always)]
126 pub fn x6(self) -> &'a mut W {
127 self.variant(OVS_A::X6)
128 }
129 #[doc = "Quadruple speed with 4X oversampling in asynchronous mode"]
130 #[inline(always)]
131 pub fn x4(self) -> &'a mut W {
132 self.variant(OVS_A::X4)
133 }
134}
135#[doc = "Field `CLKPOL` reader - Clock Polarity"]
136pub type CLKPOL_R = crate::BitReader<bool>;
137#[doc = "Field `CLKPOL` writer - Clock Polarity"]
138pub type CLKPOL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 8>;
139#[doc = "Field `CLKPHA` reader - Clock Edge For Setup/Sample"]
140pub type CLKPHA_R = crate::BitReader<bool>;
141#[doc = "Field `CLKPHA` writer - Clock Edge For Setup/Sample"]
142pub type CLKPHA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 9>;
143#[doc = "Field `MSBF` reader - Most Significant Bit First"]
144pub type MSBF_R = crate::BitReader<bool>;
145#[doc = "Field `MSBF` writer - Most Significant Bit First"]
146pub type MSBF_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 10>;
147#[doc = "Field `CSMA` reader - Action On Slave-Select In Master Mode"]
148pub type CSMA_R = crate::BitReader<bool>;
149#[doc = "Field `CSMA` writer - Action On Slave-Select In Master Mode"]
150pub type CSMA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 11>;
151#[doc = "Field `TXBIL` reader - TX Buffer Interrupt Level"]
152pub type TXBIL_R = crate::BitReader<bool>;
153#[doc = "Field `TXBIL` writer - TX Buffer Interrupt Level"]
154pub type TXBIL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 12>;
155#[doc = "Field `RXINV` reader - Receiver Input Invert"]
156pub type RXINV_R = crate::BitReader<bool>;
157#[doc = "Field `RXINV` writer - Receiver Input Invert"]
158pub type RXINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 13>;
159#[doc = "Field `TXINV` reader - Transmitter output Invert"]
160pub type TXINV_R = crate::BitReader<bool>;
161#[doc = "Field `TXINV` writer - Transmitter output Invert"]
162pub type TXINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 14>;
163#[doc = "Field `CSINV` reader - Chip Select Invert"]
164pub type CSINV_R = crate::BitReader<bool>;
165#[doc = "Field `CSINV` writer - Chip Select Invert"]
166pub type CSINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 15>;
167#[doc = "Field `AUTOCS` reader - Automatic Chip Select"]
168pub type AUTOCS_R = crate::BitReader<bool>;
169#[doc = "Field `AUTOCS` writer - Automatic Chip Select"]
170pub type AUTOCS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 16>;
171#[doc = "Field `AUTOTRI` reader - Automatic TX Tristate"]
172pub type AUTOTRI_R = crate::BitReader<bool>;
173#[doc = "Field `AUTOTRI` writer - Automatic TX Tristate"]
174pub type AUTOTRI_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 17>;
175#[doc = "Field `SCMODE` reader - SmartCard Mode"]
176pub type SCMODE_R = crate::BitReader<bool>;
177#[doc = "Field `SCMODE` writer - SmartCard Mode"]
178pub type SCMODE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 18>;
179#[doc = "Field `SCRETRANS` reader - SmartCard Retransmit"]
180pub type SCRETRANS_R = crate::BitReader<bool>;
181#[doc = "Field `SCRETRANS` writer - SmartCard Retransmit"]
182pub type SCRETRANS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 19>;
183#[doc = "Field `SKIPPERRF` reader - Skip Parity Error Frames"]
184pub type SKIPPERRF_R = crate::BitReader<bool>;
185#[doc = "Field `SKIPPERRF` writer - Skip Parity Error Frames"]
186pub type SKIPPERRF_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 20>;
187#[doc = "Field `BIT8DV` reader - Bit 8 Default Value"]
188pub type BIT8DV_R = crate::BitReader<bool>;
189#[doc = "Field `BIT8DV` writer - Bit 8 Default Value"]
190pub type BIT8DV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 21>;
191#[doc = "Field `ERRSDMA` reader - Halt DMA On Error"]
192pub type ERRSDMA_R = crate::BitReader<bool>;
193#[doc = "Field `ERRSDMA` writer - Halt DMA On Error"]
194pub type ERRSDMA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 22>;
195#[doc = "Field `ERRSRX` reader - Disable RX On Error"]
196pub type ERRSRX_R = crate::BitReader<bool>;
197#[doc = "Field `ERRSRX` writer - Disable RX On Error"]
198pub type ERRSRX_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 23>;
199#[doc = "Field `ERRSTX` reader - Disable TX On Error"]
200pub type ERRSTX_R = crate::BitReader<bool>;
201#[doc = "Field `ERRSTX` writer - Disable TX On Error"]
202pub type ERRSTX_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 24>;
203#[doc = "TX Delay Transmission\n\nValue on reset: 0"]
204#[derive(Clone, Copy, Debug, PartialEq)]
205#[repr(u8)]
206pub enum TXDELAY_A {
207 #[doc = "0: Frames are transmitted immediately"]
208 NONE = 0,
209 #[doc = "1: Transmission of new frames are delayed by a single baud period"]
210 SINGLE = 1,
211 #[doc = "2: Transmission of new frames are delayed by two baud periods"]
212 DOUBLE = 2,
213 #[doc = "3: Transmission of new frames are delayed by three baud periods"]
214 TRIPLE = 3,
215}
216impl From<TXDELAY_A> for u8 {
217 #[inline(always)]
218 fn from(variant: TXDELAY_A) -> Self {
219 variant as _
220 }
221}
222#[doc = "Field `TXDELAY` reader - TX Delay Transmission"]
223pub type TXDELAY_R = crate::FieldReader<u8, TXDELAY_A>;
224impl TXDELAY_R {
225 #[doc = "Get enumerated values variant"]
226 #[inline(always)]
227 pub fn variant(&self) -> TXDELAY_A {
228 match self.bits {
229 0 => TXDELAY_A::NONE,
230 1 => TXDELAY_A::SINGLE,
231 2 => TXDELAY_A::DOUBLE,
232 3 => TXDELAY_A::TRIPLE,
233 _ => unreachable!(),
234 }
235 }
236 #[doc = "Checks if the value of the field is `NONE`"]
237 #[inline(always)]
238 pub fn is_none(&self) -> bool {
239 *self == TXDELAY_A::NONE
240 }
241 #[doc = "Checks if the value of the field is `SINGLE`"]
242 #[inline(always)]
243 pub fn is_single(&self) -> bool {
244 *self == TXDELAY_A::SINGLE
245 }
246 #[doc = "Checks if the value of the field is `DOUBLE`"]
247 #[inline(always)]
248 pub fn is_double(&self) -> bool {
249 *self == TXDELAY_A::DOUBLE
250 }
251 #[doc = "Checks if the value of the field is `TRIPLE`"]
252 #[inline(always)]
253 pub fn is_triple(&self) -> bool {
254 *self == TXDELAY_A::TRIPLE
255 }
256}
257#[doc = "Field `TXDELAY` writer - TX Delay Transmission"]
258pub type TXDELAY_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, TXDELAY_A, 2, 26>;
259impl<'a> TXDELAY_W<'a> {
260 #[doc = "Frames are transmitted immediately"]
261 #[inline(always)]
262 pub fn none(self) -> &'a mut W {
263 self.variant(TXDELAY_A::NONE)
264 }
265 #[doc = "Transmission of new frames are delayed by a single baud period"]
266 #[inline(always)]
267 pub fn single(self) -> &'a mut W {
268 self.variant(TXDELAY_A::SINGLE)
269 }
270 #[doc = "Transmission of new frames are delayed by two baud periods"]
271 #[inline(always)]
272 pub fn double(self) -> &'a mut W {
273 self.variant(TXDELAY_A::DOUBLE)
274 }
275 #[doc = "Transmission of new frames are delayed by three baud periods"]
276 #[inline(always)]
277 pub fn triple(self) -> &'a mut W {
278 self.variant(TXDELAY_A::TRIPLE)
279 }
280}
281#[doc = "Field `BYTESWAP` reader - Byteswap In Double Accesses"]
282pub type BYTESWAP_R = crate::BitReader<bool>;
283#[doc = "Field `BYTESWAP` writer - Byteswap In Double Accesses"]
284pub type BYTESWAP_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 28>;
285#[doc = "Field `AUTOTX` reader - Always Transmit When RX Not Full"]
286pub type AUTOTX_R = crate::BitReader<bool>;
287#[doc = "Field `AUTOTX` writer - Always Transmit When RX Not Full"]
288pub type AUTOTX_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 29>;
289#[doc = "Field `MVDIS` reader - Majority Vote Disable"]
290pub type MVDIS_R = crate::BitReader<bool>;
291#[doc = "Field `MVDIS` writer - Majority Vote Disable"]
292pub type MVDIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 30>;
293impl R {
294 #[doc = "Bit 0 - USART Synchronous Mode"]
295 #[inline(always)]
296 pub fn sync(&self) -> SYNC_R {
297 SYNC_R::new((self.bits & 1) != 0)
298 }
299 #[doc = "Bit 1 - Loopback Enable"]
300 #[inline(always)]
301 pub fn loopbk(&self) -> LOOPBK_R {
302 LOOPBK_R::new(((self.bits >> 1) & 1) != 0)
303 }
304 #[doc = "Bit 2 - Collision Check Enable"]
305 #[inline(always)]
306 pub fn ccen(&self) -> CCEN_R {
307 CCEN_R::new(((self.bits >> 2) & 1) != 0)
308 }
309 #[doc = "Bit 3 - Multi-Processor Mode"]
310 #[inline(always)]
311 pub fn mpm(&self) -> MPM_R {
312 MPM_R::new(((self.bits >> 3) & 1) != 0)
313 }
314 #[doc = "Bit 4 - Multi-Processor Address-Bit"]
315 #[inline(always)]
316 pub fn mpab(&self) -> MPAB_R {
317 MPAB_R::new(((self.bits >> 4) & 1) != 0)
318 }
319 #[doc = "Bits 5:6 - Oversampling"]
320 #[inline(always)]
321 pub fn ovs(&self) -> OVS_R {
322 OVS_R::new(((self.bits >> 5) & 3) as u8)
323 }
324 #[doc = "Bit 8 - Clock Polarity"]
325 #[inline(always)]
326 pub fn clkpol(&self) -> CLKPOL_R {
327 CLKPOL_R::new(((self.bits >> 8) & 1) != 0)
328 }
329 #[doc = "Bit 9 - Clock Edge For Setup/Sample"]
330 #[inline(always)]
331 pub fn clkpha(&self) -> CLKPHA_R {
332 CLKPHA_R::new(((self.bits >> 9) & 1) != 0)
333 }
334 #[doc = "Bit 10 - Most Significant Bit First"]
335 #[inline(always)]
336 pub fn msbf(&self) -> MSBF_R {
337 MSBF_R::new(((self.bits >> 10) & 1) != 0)
338 }
339 #[doc = "Bit 11 - Action On Slave-Select In Master Mode"]
340 #[inline(always)]
341 pub fn csma(&self) -> CSMA_R {
342 CSMA_R::new(((self.bits >> 11) & 1) != 0)
343 }
344 #[doc = "Bit 12 - TX Buffer Interrupt Level"]
345 #[inline(always)]
346 pub fn txbil(&self) -> TXBIL_R {
347 TXBIL_R::new(((self.bits >> 12) & 1) != 0)
348 }
349 #[doc = "Bit 13 - Receiver Input Invert"]
350 #[inline(always)]
351 pub fn rxinv(&self) -> RXINV_R {
352 RXINV_R::new(((self.bits >> 13) & 1) != 0)
353 }
354 #[doc = "Bit 14 - Transmitter output Invert"]
355 #[inline(always)]
356 pub fn txinv(&self) -> TXINV_R {
357 TXINV_R::new(((self.bits >> 14) & 1) != 0)
358 }
359 #[doc = "Bit 15 - Chip Select Invert"]
360 #[inline(always)]
361 pub fn csinv(&self) -> CSINV_R {
362 CSINV_R::new(((self.bits >> 15) & 1) != 0)
363 }
364 #[doc = "Bit 16 - Automatic Chip Select"]
365 #[inline(always)]
366 pub fn autocs(&self) -> AUTOCS_R {
367 AUTOCS_R::new(((self.bits >> 16) & 1) != 0)
368 }
369 #[doc = "Bit 17 - Automatic TX Tristate"]
370 #[inline(always)]
371 pub fn autotri(&self) -> AUTOTRI_R {
372 AUTOTRI_R::new(((self.bits >> 17) & 1) != 0)
373 }
374 #[doc = "Bit 18 - SmartCard Mode"]
375 #[inline(always)]
376 pub fn scmode(&self) -> SCMODE_R {
377 SCMODE_R::new(((self.bits >> 18) & 1) != 0)
378 }
379 #[doc = "Bit 19 - SmartCard Retransmit"]
380 #[inline(always)]
381 pub fn scretrans(&self) -> SCRETRANS_R {
382 SCRETRANS_R::new(((self.bits >> 19) & 1) != 0)
383 }
384 #[doc = "Bit 20 - Skip Parity Error Frames"]
385 #[inline(always)]
386 pub fn skipperrf(&self) -> SKIPPERRF_R {
387 SKIPPERRF_R::new(((self.bits >> 20) & 1) != 0)
388 }
389 #[doc = "Bit 21 - Bit 8 Default Value"]
390 #[inline(always)]
391 pub fn bit8dv(&self) -> BIT8DV_R {
392 BIT8DV_R::new(((self.bits >> 21) & 1) != 0)
393 }
394 #[doc = "Bit 22 - Halt DMA On Error"]
395 #[inline(always)]
396 pub fn errsdma(&self) -> ERRSDMA_R {
397 ERRSDMA_R::new(((self.bits >> 22) & 1) != 0)
398 }
399 #[doc = "Bit 23 - Disable RX On Error"]
400 #[inline(always)]
401 pub fn errsrx(&self) -> ERRSRX_R {
402 ERRSRX_R::new(((self.bits >> 23) & 1) != 0)
403 }
404 #[doc = "Bit 24 - Disable TX On Error"]
405 #[inline(always)]
406 pub fn errstx(&self) -> ERRSTX_R {
407 ERRSTX_R::new(((self.bits >> 24) & 1) != 0)
408 }
409 #[doc = "Bits 26:27 - TX Delay Transmission"]
410 #[inline(always)]
411 pub fn txdelay(&self) -> TXDELAY_R {
412 TXDELAY_R::new(((self.bits >> 26) & 3) as u8)
413 }
414 #[doc = "Bit 28 - Byteswap In Double Accesses"]
415 #[inline(always)]
416 pub fn byteswap(&self) -> BYTESWAP_R {
417 BYTESWAP_R::new(((self.bits >> 28) & 1) != 0)
418 }
419 #[doc = "Bit 29 - Always Transmit When RX Not Full"]
420 #[inline(always)]
421 pub fn autotx(&self) -> AUTOTX_R {
422 AUTOTX_R::new(((self.bits >> 29) & 1) != 0)
423 }
424 #[doc = "Bit 30 - Majority Vote Disable"]
425 #[inline(always)]
426 pub fn mvdis(&self) -> MVDIS_R {
427 MVDIS_R::new(((self.bits >> 30) & 1) != 0)
428 }
429}
430impl W {
431 #[doc = "Bit 0 - USART Synchronous Mode"]
432 #[inline(always)]
433 pub fn sync(&mut self) -> SYNC_W {
434 SYNC_W::new(self)
435 }
436 #[doc = "Bit 1 - Loopback Enable"]
437 #[inline(always)]
438 pub fn loopbk(&mut self) -> LOOPBK_W {
439 LOOPBK_W::new(self)
440 }
441 #[doc = "Bit 2 - Collision Check Enable"]
442 #[inline(always)]
443 pub fn ccen(&mut self) -> CCEN_W {
444 CCEN_W::new(self)
445 }
446 #[doc = "Bit 3 - Multi-Processor Mode"]
447 #[inline(always)]
448 pub fn mpm(&mut self) -> MPM_W {
449 MPM_W::new(self)
450 }
451 #[doc = "Bit 4 - Multi-Processor Address-Bit"]
452 #[inline(always)]
453 pub fn mpab(&mut self) -> MPAB_W {
454 MPAB_W::new(self)
455 }
456 #[doc = "Bits 5:6 - Oversampling"]
457 #[inline(always)]
458 pub fn ovs(&mut self) -> OVS_W {
459 OVS_W::new(self)
460 }
461 #[doc = "Bit 8 - Clock Polarity"]
462 #[inline(always)]
463 pub fn clkpol(&mut self) -> CLKPOL_W {
464 CLKPOL_W::new(self)
465 }
466 #[doc = "Bit 9 - Clock Edge For Setup/Sample"]
467 #[inline(always)]
468 pub fn clkpha(&mut self) -> CLKPHA_W {
469 CLKPHA_W::new(self)
470 }
471 #[doc = "Bit 10 - Most Significant Bit First"]
472 #[inline(always)]
473 pub fn msbf(&mut self) -> MSBF_W {
474 MSBF_W::new(self)
475 }
476 #[doc = "Bit 11 - Action On Slave-Select In Master Mode"]
477 #[inline(always)]
478 pub fn csma(&mut self) -> CSMA_W {
479 CSMA_W::new(self)
480 }
481 #[doc = "Bit 12 - TX Buffer Interrupt Level"]
482 #[inline(always)]
483 pub fn txbil(&mut self) -> TXBIL_W {
484 TXBIL_W::new(self)
485 }
486 #[doc = "Bit 13 - Receiver Input Invert"]
487 #[inline(always)]
488 pub fn rxinv(&mut self) -> RXINV_W {
489 RXINV_W::new(self)
490 }
491 #[doc = "Bit 14 - Transmitter output Invert"]
492 #[inline(always)]
493 pub fn txinv(&mut self) -> TXINV_W {
494 TXINV_W::new(self)
495 }
496 #[doc = "Bit 15 - Chip Select Invert"]
497 #[inline(always)]
498 pub fn csinv(&mut self) -> CSINV_W {
499 CSINV_W::new(self)
500 }
501 #[doc = "Bit 16 - Automatic Chip Select"]
502 #[inline(always)]
503 pub fn autocs(&mut self) -> AUTOCS_W {
504 AUTOCS_W::new(self)
505 }
506 #[doc = "Bit 17 - Automatic TX Tristate"]
507 #[inline(always)]
508 pub fn autotri(&mut self) -> AUTOTRI_W {
509 AUTOTRI_W::new(self)
510 }
511 #[doc = "Bit 18 - SmartCard Mode"]
512 #[inline(always)]
513 pub fn scmode(&mut self) -> SCMODE_W {
514 SCMODE_W::new(self)
515 }
516 #[doc = "Bit 19 - SmartCard Retransmit"]
517 #[inline(always)]
518 pub fn scretrans(&mut self) -> SCRETRANS_W {
519 SCRETRANS_W::new(self)
520 }
521 #[doc = "Bit 20 - Skip Parity Error Frames"]
522 #[inline(always)]
523 pub fn skipperrf(&mut self) -> SKIPPERRF_W {
524 SKIPPERRF_W::new(self)
525 }
526 #[doc = "Bit 21 - Bit 8 Default Value"]
527 #[inline(always)]
528 pub fn bit8dv(&mut self) -> BIT8DV_W {
529 BIT8DV_W::new(self)
530 }
531 #[doc = "Bit 22 - Halt DMA On Error"]
532 #[inline(always)]
533 pub fn errsdma(&mut self) -> ERRSDMA_W {
534 ERRSDMA_W::new(self)
535 }
536 #[doc = "Bit 23 - Disable RX On Error"]
537 #[inline(always)]
538 pub fn errsrx(&mut self) -> ERRSRX_W {
539 ERRSRX_W::new(self)
540 }
541 #[doc = "Bit 24 - Disable TX On Error"]
542 #[inline(always)]
543 pub fn errstx(&mut self) -> ERRSTX_W {
544 ERRSTX_W::new(self)
545 }
546 #[doc = "Bits 26:27 - TX Delay Transmission"]
547 #[inline(always)]
548 pub fn txdelay(&mut self) -> TXDELAY_W {
549 TXDELAY_W::new(self)
550 }
551 #[doc = "Bit 28 - Byteswap In Double Accesses"]
552 #[inline(always)]
553 pub fn byteswap(&mut self) -> BYTESWAP_W {
554 BYTESWAP_W::new(self)
555 }
556 #[doc = "Bit 29 - Always Transmit When RX Not Full"]
557 #[inline(always)]
558 pub fn autotx(&mut self) -> AUTOTX_W {
559 AUTOTX_W::new(self)
560 }
561 #[doc = "Bit 30 - Majority Vote Disable"]
562 #[inline(always)]
563 pub fn mvdis(&mut self) -> MVDIS_W {
564 MVDIS_W::new(self)
565 }
566 #[doc = "Writes raw bits to the register."]
567 #[inline(always)]
568 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
569 self.0.bits(bits);
570 self
571 }
572}
573#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
574pub struct CTRL_SPEC;
575impl crate::RegisterSpec for CTRL_SPEC {
576 type Ux = u32;
577}
578#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
579impl crate::Readable for CTRL_SPEC {
580 type Reader = R;
581}
582#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
583impl crate::Writable for CTRL_SPEC {
584 type Writer = W;
585}
586#[doc = "`reset()` method sets CTRL to value 0"]
587impl crate::Resettable for CTRL_SPEC {
588 #[inline(always)]
589 fn reset_value() -> Self::Ux {
590 0
591 }
592}