efm32gg840_pac/emu/
pwrconf.rs

1#[doc = "Register `PWRCONF` reader"]
2pub struct R(crate::R<PWRCONF_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PWRCONF_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PWRCONF_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PWRCONF_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PWRCONF` writer"]
17pub struct W(crate::W<PWRCONF_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PWRCONF_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PWRCONF_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PWRCONF_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `VOUTWEAK` reader - BU_VOUT weak enable"]
38pub type VOUTWEAK_R = crate::BitReader<bool>;
39#[doc = "Field `VOUTWEAK` writer - BU_VOUT weak enable"]
40pub type VOUTWEAK_W<'a> = crate::BitWriter<'a, u32, PWRCONF_SPEC, bool, 0>;
41#[doc = "Field `VOUTMED` reader - BU_VOUT medium enable"]
42pub type VOUTMED_R = crate::BitReader<bool>;
43#[doc = "Field `VOUTMED` writer - BU_VOUT medium enable"]
44pub type VOUTMED_W<'a> = crate::BitWriter<'a, u32, PWRCONF_SPEC, bool, 1>;
45#[doc = "Field `VOUTSTRONG` reader - BU_VOUT strong enable"]
46pub type VOUTSTRONG_R = crate::BitReader<bool>;
47#[doc = "Field `VOUTSTRONG` writer - BU_VOUT strong enable"]
48pub type VOUTSTRONG_W<'a> = crate::BitWriter<'a, u32, PWRCONF_SPEC, bool, 2>;
49#[doc = "Power domain resistor select\n\nValue on reset: 0"]
50#[derive(Clone, Copy, Debug, PartialEq)]
51#[repr(u8)]
52pub enum PWRRES_A {
53    #[doc = "0: Main power and backup power connected with RES0 series resistance."]
54    RES0 = 0,
55    #[doc = "1: Main power and backup power connected with RES1 series resistance."]
56    RES1 = 1,
57    #[doc = "2: Main power and backup power connected with RES2 series resistance."]
58    RES2 = 2,
59    #[doc = "3: Main power and backup power connected with RES3 series resistance."]
60    RES3 = 3,
61}
62impl From<PWRRES_A> for u8 {
63    #[inline(always)]
64    fn from(variant: PWRRES_A) -> Self {
65        variant as _
66    }
67}
68#[doc = "Field `PWRRES` reader - Power domain resistor select"]
69pub type PWRRES_R = crate::FieldReader<u8, PWRRES_A>;
70impl PWRRES_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> PWRRES_A {
74        match self.bits {
75            0 => PWRRES_A::RES0,
76            1 => PWRRES_A::RES1,
77            2 => PWRRES_A::RES2,
78            3 => PWRRES_A::RES3,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `RES0`"]
83    #[inline(always)]
84    pub fn is_res0(&self) -> bool {
85        *self == PWRRES_A::RES0
86    }
87    #[doc = "Checks if the value of the field is `RES1`"]
88    #[inline(always)]
89    pub fn is_res1(&self) -> bool {
90        *self == PWRRES_A::RES1
91    }
92    #[doc = "Checks if the value of the field is `RES2`"]
93    #[inline(always)]
94    pub fn is_res2(&self) -> bool {
95        *self == PWRRES_A::RES2
96    }
97    #[doc = "Checks if the value of the field is `RES3`"]
98    #[inline(always)]
99    pub fn is_res3(&self) -> bool {
100        *self == PWRRES_A::RES3
101    }
102}
103#[doc = "Field `PWRRES` writer - Power domain resistor select"]
104pub type PWRRES_W<'a> = crate::FieldWriterSafe<'a, u32, PWRCONF_SPEC, u8, PWRRES_A, 2, 3>;
105impl<'a> PWRRES_W<'a> {
106    #[doc = "Main power and backup power connected with RES0 series resistance."]
107    #[inline(always)]
108    pub fn res0(self) -> &'a mut W {
109        self.variant(PWRRES_A::RES0)
110    }
111    #[doc = "Main power and backup power connected with RES1 series resistance."]
112    #[inline(always)]
113    pub fn res1(self) -> &'a mut W {
114        self.variant(PWRRES_A::RES1)
115    }
116    #[doc = "Main power and backup power connected with RES2 series resistance."]
117    #[inline(always)]
118    pub fn res2(self) -> &'a mut W {
119        self.variant(PWRRES_A::RES2)
120    }
121    #[doc = "Main power and backup power connected with RES3 series resistance."]
122    #[inline(always)]
123    pub fn res3(self) -> &'a mut W {
124        self.variant(PWRRES_A::RES3)
125    }
126}
127impl R {
128    #[doc = "Bit 0 - BU_VOUT weak enable"]
129    #[inline(always)]
130    pub fn voutweak(&self) -> VOUTWEAK_R {
131        VOUTWEAK_R::new((self.bits & 1) != 0)
132    }
133    #[doc = "Bit 1 - BU_VOUT medium enable"]
134    #[inline(always)]
135    pub fn voutmed(&self) -> VOUTMED_R {
136        VOUTMED_R::new(((self.bits >> 1) & 1) != 0)
137    }
138    #[doc = "Bit 2 - BU_VOUT strong enable"]
139    #[inline(always)]
140    pub fn voutstrong(&self) -> VOUTSTRONG_R {
141        VOUTSTRONG_R::new(((self.bits >> 2) & 1) != 0)
142    }
143    #[doc = "Bits 3:4 - Power domain resistor select"]
144    #[inline(always)]
145    pub fn pwrres(&self) -> PWRRES_R {
146        PWRRES_R::new(((self.bits >> 3) & 3) as u8)
147    }
148}
149impl W {
150    #[doc = "Bit 0 - BU_VOUT weak enable"]
151    #[inline(always)]
152    pub fn voutweak(&mut self) -> VOUTWEAK_W {
153        VOUTWEAK_W::new(self)
154    }
155    #[doc = "Bit 1 - BU_VOUT medium enable"]
156    #[inline(always)]
157    pub fn voutmed(&mut self) -> VOUTMED_W {
158        VOUTMED_W::new(self)
159    }
160    #[doc = "Bit 2 - BU_VOUT strong enable"]
161    #[inline(always)]
162    pub fn voutstrong(&mut self) -> VOUTSTRONG_W {
163        VOUTSTRONG_W::new(self)
164    }
165    #[doc = "Bits 3:4 - Power domain resistor select"]
166    #[inline(always)]
167    pub fn pwrres(&mut self) -> PWRRES_W {
168        PWRRES_W::new(self)
169    }
170    #[doc = "Writes raw bits to the register."]
171    #[inline(always)]
172    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
173        self.0.bits(bits);
174        self
175    }
176}
177#[doc = "Power connection configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwrconf](index.html) module"]
178pub struct PWRCONF_SPEC;
179impl crate::RegisterSpec for PWRCONF_SPEC {
180    type Ux = u32;
181}
182#[doc = "`read()` method returns [pwrconf::R](R) reader structure"]
183impl crate::Readable for PWRCONF_SPEC {
184    type Reader = R;
185}
186#[doc = "`write(|w| ..)` method takes [pwrconf::W](W) writer structure"]
187impl crate::Writable for PWRCONF_SPEC {
188    type Writer = W;
189}
190#[doc = "`reset()` method sets PWRCONF to value 0"]
191impl crate::Resettable for PWRCONF_SPEC {
192    #[inline(always)]
193    fn reset_value() -> Self::Ux {
194        0
195    }
196}
efm32gg840_pac/emu/pwrconf.rs

efm32gg840_pac/emu/
pwrconf.rs
