1#[doc = "Reader of register CH4_CTRL"]
2pub type R = crate::R<u32, super::CH4_CTRL>;
3#[doc = "Writer for register CH4_CTRL"]
4pub type W = crate::W<u32, super::CH4_CTRL>;
5#[doc = "Register CH4_CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CH4_CTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `SIGSEL`"]
14pub type SIGSEL_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `SIGSEL`"]
16pub struct SIGSEL_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> SIGSEL_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
24 self.w
25 }
26}
27#[doc = "Source Select\n\nValue on reset: 0"]
28#[derive(Clone, Copy, Debug, PartialEq)]
29#[repr(u8)]
30pub enum SOURCESEL_A {
31 #[doc = "0: No source selected"]
32 NONE = 0,
33 #[doc = "1: Peripheral Reflex System"]
34 PRSL = 1,
35 #[doc = "2: Peripheral Reflex System"]
36 PRS = 2,
37 #[doc = "4: Analog Comparator 0"]
38 ACMP0 = 4,
39 #[doc = "5: Analog Comparator 1"]
40 ACMP1 = 5,
41 #[doc = "6: Analog to Digital Converter 0"]
42 ADC0 = 6,
43 #[doc = "7: Real-Time Counter"]
44 RTC = 7,
45 #[doc = "8: Real-Time Counter and Calendar"]
46 RTCC = 8,
47 #[doc = "9: General purpose Input/Output"]
48 GPIOL = 9,
49 #[doc = "10: General purpose Input/Output"]
50 GPIOH = 10,
51 #[doc = "11: Low Energy Timer 0"]
52 LETIMER0 = 11,
53 #[doc = "12: Low Energy Timer 1"]
54 LETIMER1 = 12,
55 #[doc = "13: Pulse Counter 0"]
56 PCNT0 = 13,
57 #[doc = "14: Pulse Counter 1"]
58 PCNT1 = 14,
59 #[doc = "15: Pulse Counter 2"]
60 PCNT2 = 15,
61 #[doc = "16: CRYOTIMER"]
62 CRYOTIMER = 16,
63 #[doc = "17: Clock Management Unit"]
64 CMU = 17,
65 #[doc = "23: Digital to Analog Converter 0"]
66 VDAC0 = 23,
67 #[doc = "24: Low Energy Sensor Interface"]
68 LESENSEL = 24,
69 #[doc = "25: Low Energy Sensor Interface"]
70 LESENSEH = 25,
71 #[doc = "26: Low Energy Sensor Interface"]
72 LESENSED = 26,
73 #[doc = "27: Low Energy Sensor Interface"]
74 LESENSE = 27,
75 #[doc = "28: Analog Comparator 2"]
76 ACMP2 = 28,
77 #[doc = "29: Analog to Digital Converter 0"]
78 ADC1 = 29,
79 #[doc = "48: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
80 USART0 = 48,
81 #[doc = "49: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
82 USART1 = 49,
83 #[doc = "50: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
84 USART2 = 50,
85 #[doc = "51: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
86 USART3 = 51,
87 #[doc = "52: Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
88 USART4 = 52,
89 #[doc = "54: Universal Asynchronous Receiver/Transmitter 0"]
90 UART0 = 54,
91 #[doc = "55: Universal Asynchronous Receiver/Transmitter 1"]
92 UART1 = 55,
93 #[doc = "60: Timer 0"]
94 TIMER0 = 60,
95 #[doc = "61: Timer 1"]
96 TIMER1 = 61,
97 #[doc = "62: Timer 2"]
98 TIMER2 = 62,
99 #[doc = "64: Universal Serial Bus Interface"]
100 USB = 64,
101 #[doc = "67: `1000011`"]
102 CM4 = 67,
103 #[doc = "80: Timer 3"]
104 TIMER3 = 80,
105 #[doc = "82: Wide Timer 0"]
106 WTIMER0 = 82,
107 #[doc = "83: Wide Timer 0"]
108 WTIMER1 = 83,
109 #[doc = "121: PDM Interface "]
110 PDM = 121,
111}
112impl From<SOURCESEL_A> for u8 {
113 #[inline(always)]
114 fn from(variant: SOURCESEL_A) -> Self {
115 variant as _
116 }
117}
118#[doc = "Reader of field `SOURCESEL`"]
119pub type SOURCESEL_R = crate::R<u8, SOURCESEL_A>;
120impl SOURCESEL_R {
121 #[doc = r"Get enumerated values variant"]
122 #[inline(always)]
123 pub fn variant(&self) -> crate::Variant<u8, SOURCESEL_A> {
124 use crate::Variant::*;
125 match self.bits {
126 0 => Val(SOURCESEL_A::NONE),
127 1 => Val(SOURCESEL_A::PRSL),
128 2 => Val(SOURCESEL_A::PRS),
129 4 => Val(SOURCESEL_A::ACMP0),
130 5 => Val(SOURCESEL_A::ACMP1),
131 6 => Val(SOURCESEL_A::ADC0),
132 7 => Val(SOURCESEL_A::RTC),
133 8 => Val(SOURCESEL_A::RTCC),
134 9 => Val(SOURCESEL_A::GPIOL),
135 10 => Val(SOURCESEL_A::GPIOH),
136 11 => Val(SOURCESEL_A::LETIMER0),
137 12 => Val(SOURCESEL_A::LETIMER1),
138 13 => Val(SOURCESEL_A::PCNT0),
139 14 => Val(SOURCESEL_A::PCNT1),
140 15 => Val(SOURCESEL_A::PCNT2),
141 16 => Val(SOURCESEL_A::CRYOTIMER),
142 17 => Val(SOURCESEL_A::CMU),
143 23 => Val(SOURCESEL_A::VDAC0),
144 24 => Val(SOURCESEL_A::LESENSEL),
145 25 => Val(SOURCESEL_A::LESENSEH),
146 26 => Val(SOURCESEL_A::LESENSED),
147 27 => Val(SOURCESEL_A::LESENSE),
148 28 => Val(SOURCESEL_A::ACMP2),
149 29 => Val(SOURCESEL_A::ADC1),
150 48 => Val(SOURCESEL_A::USART0),
151 49 => Val(SOURCESEL_A::USART1),
152 50 => Val(SOURCESEL_A::USART2),
153 51 => Val(SOURCESEL_A::USART3),
154 52 => Val(SOURCESEL_A::USART4),
155 54 => Val(SOURCESEL_A::UART0),
156 55 => Val(SOURCESEL_A::UART1),
157 60 => Val(SOURCESEL_A::TIMER0),
158 61 => Val(SOURCESEL_A::TIMER1),
159 62 => Val(SOURCESEL_A::TIMER2),
160 64 => Val(SOURCESEL_A::USB),
161 67 => Val(SOURCESEL_A::CM4),
162 80 => Val(SOURCESEL_A::TIMER3),
163 82 => Val(SOURCESEL_A::WTIMER0),
164 83 => Val(SOURCESEL_A::WTIMER1),
165 121 => Val(SOURCESEL_A::PDM),
166 i => Res(i),
167 }
168 }
169 #[doc = "Checks if the value of the field is `NONE`"]
170 #[inline(always)]
171 pub fn is_none(&self) -> bool {
172 *self == SOURCESEL_A::NONE
173 }
174 #[doc = "Checks if the value of the field is `PRSL`"]
175 #[inline(always)]
176 pub fn is_prsl(&self) -> bool {
177 *self == SOURCESEL_A::PRSL
178 }
179 #[doc = "Checks if the value of the field is `PRS`"]
180 #[inline(always)]
181 pub fn is_prs(&self) -> bool {
182 *self == SOURCESEL_A::PRS
183 }
184 #[doc = "Checks if the value of the field is `ACMP0`"]
185 #[inline(always)]
186 pub fn is_acmp0(&self) -> bool {
187 *self == SOURCESEL_A::ACMP0
188 }
189 #[doc = "Checks if the value of the field is `ACMP1`"]
190 #[inline(always)]
191 pub fn is_acmp1(&self) -> bool {
192 *self == SOURCESEL_A::ACMP1
193 }
194 #[doc = "Checks if the value of the field is `ADC0`"]
195 #[inline(always)]
196 pub fn is_adc0(&self) -> bool {
197 *self == SOURCESEL_A::ADC0
198 }
199 #[doc = "Checks if the value of the field is `RTC`"]
200 #[inline(always)]
201 pub fn is_rtc(&self) -> bool {
202 *self == SOURCESEL_A::RTC
203 }
204 #[doc = "Checks if the value of the field is `RTCC`"]
205 #[inline(always)]
206 pub fn is_rtcc(&self) -> bool {
207 *self == SOURCESEL_A::RTCC
208 }
209 #[doc = "Checks if the value of the field is `GPIOL`"]
210 #[inline(always)]
211 pub fn is_gpiol(&self) -> bool {
212 *self == SOURCESEL_A::GPIOL
213 }
214 #[doc = "Checks if the value of the field is `GPIOH`"]
215 #[inline(always)]
216 pub fn is_gpioh(&self) -> bool {
217 *self == SOURCESEL_A::GPIOH
218 }
219 #[doc = "Checks if the value of the field is `LETIMER0`"]
220 #[inline(always)]
221 pub fn is_letimer0(&self) -> bool {
222 *self == SOURCESEL_A::LETIMER0
223 }
224 #[doc = "Checks if the value of the field is `LETIMER1`"]
225 #[inline(always)]
226 pub fn is_letimer1(&self) -> bool {
227 *self == SOURCESEL_A::LETIMER1
228 }
229 #[doc = "Checks if the value of the field is `PCNT0`"]
230 #[inline(always)]
231 pub fn is_pcnt0(&self) -> bool {
232 *self == SOURCESEL_A::PCNT0
233 }
234 #[doc = "Checks if the value of the field is `PCNT1`"]
235 #[inline(always)]
236 pub fn is_pcnt1(&self) -> bool {
237 *self == SOURCESEL_A::PCNT1
238 }
239 #[doc = "Checks if the value of the field is `PCNT2`"]
240 #[inline(always)]
241 pub fn is_pcnt2(&self) -> bool {
242 *self == SOURCESEL_A::PCNT2
243 }
244 #[doc = "Checks if the value of the field is `CRYOTIMER`"]
245 #[inline(always)]
246 pub fn is_cryotimer(&self) -> bool {
247 *self == SOURCESEL_A::CRYOTIMER
248 }
249 #[doc = "Checks if the value of the field is `CMU`"]
250 #[inline(always)]
251 pub fn is_cmu(&self) -> bool {
252 *self == SOURCESEL_A::CMU
253 }
254 #[doc = "Checks if the value of the field is `VDAC0`"]
255 #[inline(always)]
256 pub fn is_vdac0(&self) -> bool {
257 *self == SOURCESEL_A::VDAC0
258 }
259 #[doc = "Checks if the value of the field is `LESENSEL`"]
260 #[inline(always)]
261 pub fn is_lesensel(&self) -> bool {
262 *self == SOURCESEL_A::LESENSEL
263 }
264 #[doc = "Checks if the value of the field is `LESENSEH`"]
265 #[inline(always)]
266 pub fn is_lesenseh(&self) -> bool {
267 *self == SOURCESEL_A::LESENSEH
268 }
269 #[doc = "Checks if the value of the field is `LESENSED`"]
270 #[inline(always)]
271 pub fn is_lesensed(&self) -> bool {
272 *self == SOURCESEL_A::LESENSED
273 }
274 #[doc = "Checks if the value of the field is `LESENSE`"]
275 #[inline(always)]
276 pub fn is_lesense(&self) -> bool {
277 *self == SOURCESEL_A::LESENSE
278 }
279 #[doc = "Checks if the value of the field is `ACMP2`"]
280 #[inline(always)]
281 pub fn is_acmp2(&self) -> bool {
282 *self == SOURCESEL_A::ACMP2
283 }
284 #[doc = "Checks if the value of the field is `ADC1`"]
285 #[inline(always)]
286 pub fn is_adc1(&self) -> bool {
287 *self == SOURCESEL_A::ADC1
288 }
289 #[doc = "Checks if the value of the field is `USART0`"]
290 #[inline(always)]
291 pub fn is_usart0(&self) -> bool {
292 *self == SOURCESEL_A::USART0
293 }
294 #[doc = "Checks if the value of the field is `USART1`"]
295 #[inline(always)]
296 pub fn is_usart1(&self) -> bool {
297 *self == SOURCESEL_A::USART1
298 }
299 #[doc = "Checks if the value of the field is `USART2`"]
300 #[inline(always)]
301 pub fn is_usart2(&self) -> bool {
302 *self == SOURCESEL_A::USART2
303 }
304 #[doc = "Checks if the value of the field is `USART3`"]
305 #[inline(always)]
306 pub fn is_usart3(&self) -> bool {
307 *self == SOURCESEL_A::USART3
308 }
309 #[doc = "Checks if the value of the field is `USART4`"]
310 #[inline(always)]
311 pub fn is_usart4(&self) -> bool {
312 *self == SOURCESEL_A::USART4
313 }
314 #[doc = "Checks if the value of the field is `UART0`"]
315 #[inline(always)]
316 pub fn is_uart0(&self) -> bool {
317 *self == SOURCESEL_A::UART0
318 }
319 #[doc = "Checks if the value of the field is `UART1`"]
320 #[inline(always)]
321 pub fn is_uart1(&self) -> bool {
322 *self == SOURCESEL_A::UART1
323 }
324 #[doc = "Checks if the value of the field is `TIMER0`"]
325 #[inline(always)]
326 pub fn is_timer0(&self) -> bool {
327 *self == SOURCESEL_A::TIMER0
328 }
329 #[doc = "Checks if the value of the field is `TIMER1`"]
330 #[inline(always)]
331 pub fn is_timer1(&self) -> bool {
332 *self == SOURCESEL_A::TIMER1
333 }
334 #[doc = "Checks if the value of the field is `TIMER2`"]
335 #[inline(always)]
336 pub fn is_timer2(&self) -> bool {
337 *self == SOURCESEL_A::TIMER2
338 }
339 #[doc = "Checks if the value of the field is `USB`"]
340 #[inline(always)]
341 pub fn is_usb(&self) -> bool {
342 *self == SOURCESEL_A::USB
343 }
344 #[doc = "Checks if the value of the field is `CM4`"]
345 #[inline(always)]
346 pub fn is_cm4(&self) -> bool {
347 *self == SOURCESEL_A::CM4
348 }
349 #[doc = "Checks if the value of the field is `TIMER3`"]
350 #[inline(always)]
351 pub fn is_timer3(&self) -> bool {
352 *self == SOURCESEL_A::TIMER3
353 }
354 #[doc = "Checks if the value of the field is `WTIMER0`"]
355 #[inline(always)]
356 pub fn is_wtimer0(&self) -> bool {
357 *self == SOURCESEL_A::WTIMER0
358 }
359 #[doc = "Checks if the value of the field is `WTIMER1`"]
360 #[inline(always)]
361 pub fn is_wtimer1(&self) -> bool {
362 *self == SOURCESEL_A::WTIMER1
363 }
364 #[doc = "Checks if the value of the field is `PDM`"]
365 #[inline(always)]
366 pub fn is_pdm(&self) -> bool {
367 *self == SOURCESEL_A::PDM
368 }
369}
370#[doc = "Write proxy for field `SOURCESEL`"]
371pub struct SOURCESEL_W<'a> {
372 w: &'a mut W,
373}
374impl<'a> SOURCESEL_W<'a> {
375 #[doc = r"Writes `variant` to the field"]
376 #[inline(always)]
377 pub fn variant(self, variant: SOURCESEL_A) -> &'a mut W {
378 unsafe { self.bits(variant.into()) }
379 }
380 #[doc = "No source selected"]
381 #[inline(always)]
382 pub fn none(self) -> &'a mut W {
383 self.variant(SOURCESEL_A::NONE)
384 }
385 #[doc = "Peripheral Reflex System"]
386 #[inline(always)]
387 pub fn prsl(self) -> &'a mut W {
388 self.variant(SOURCESEL_A::PRSL)
389 }
390 #[doc = "Peripheral Reflex System"]
391 #[inline(always)]
392 pub fn prs(self) -> &'a mut W {
393 self.variant(SOURCESEL_A::PRS)
394 }
395 #[doc = "Analog Comparator 0"]
396 #[inline(always)]
397 pub fn acmp0(self) -> &'a mut W {
398 self.variant(SOURCESEL_A::ACMP0)
399 }
400 #[doc = "Analog Comparator 1"]
401 #[inline(always)]
402 pub fn acmp1(self) -> &'a mut W {
403 self.variant(SOURCESEL_A::ACMP1)
404 }
405 #[doc = "Analog to Digital Converter 0"]
406 #[inline(always)]
407 pub fn adc0(self) -> &'a mut W {
408 self.variant(SOURCESEL_A::ADC0)
409 }
410 #[doc = "Real-Time Counter"]
411 #[inline(always)]
412 pub fn rtc(self) -> &'a mut W {
413 self.variant(SOURCESEL_A::RTC)
414 }
415 #[doc = "Real-Time Counter and Calendar"]
416 #[inline(always)]
417 pub fn rtcc(self) -> &'a mut W {
418 self.variant(SOURCESEL_A::RTCC)
419 }
420 #[doc = "General purpose Input/Output"]
421 #[inline(always)]
422 pub fn gpiol(self) -> &'a mut W {
423 self.variant(SOURCESEL_A::GPIOL)
424 }
425 #[doc = "General purpose Input/Output"]
426 #[inline(always)]
427 pub fn gpioh(self) -> &'a mut W {
428 self.variant(SOURCESEL_A::GPIOH)
429 }
430 #[doc = "Low Energy Timer 0"]
431 #[inline(always)]
432 pub fn letimer0(self) -> &'a mut W {
433 self.variant(SOURCESEL_A::LETIMER0)
434 }
435 #[doc = "Low Energy Timer 1"]
436 #[inline(always)]
437 pub fn letimer1(self) -> &'a mut W {
438 self.variant(SOURCESEL_A::LETIMER1)
439 }
440 #[doc = "Pulse Counter 0"]
441 #[inline(always)]
442 pub fn pcnt0(self) -> &'a mut W {
443 self.variant(SOURCESEL_A::PCNT0)
444 }
445 #[doc = "Pulse Counter 1"]
446 #[inline(always)]
447 pub fn pcnt1(self) -> &'a mut W {
448 self.variant(SOURCESEL_A::PCNT1)
449 }
450 #[doc = "Pulse Counter 2"]
451 #[inline(always)]
452 pub fn pcnt2(self) -> &'a mut W {
453 self.variant(SOURCESEL_A::PCNT2)
454 }
455 #[doc = "CRYOTIMER"]
456 #[inline(always)]
457 pub fn cryotimer(self) -> &'a mut W {
458 self.variant(SOURCESEL_A::CRYOTIMER)
459 }
460 #[doc = "Clock Management Unit"]
461 #[inline(always)]
462 pub fn cmu(self) -> &'a mut W {
463 self.variant(SOURCESEL_A::CMU)
464 }
465 #[doc = "Digital to Analog Converter 0"]
466 #[inline(always)]
467 pub fn vdac0(self) -> &'a mut W {
468 self.variant(SOURCESEL_A::VDAC0)
469 }
470 #[doc = "Low Energy Sensor Interface"]
471 #[inline(always)]
472 pub fn lesensel(self) -> &'a mut W {
473 self.variant(SOURCESEL_A::LESENSEL)
474 }
475 #[doc = "Low Energy Sensor Interface"]
476 #[inline(always)]
477 pub fn lesenseh(self) -> &'a mut W {
478 self.variant(SOURCESEL_A::LESENSEH)
479 }
480 #[doc = "Low Energy Sensor Interface"]
481 #[inline(always)]
482 pub fn lesensed(self) -> &'a mut W {
483 self.variant(SOURCESEL_A::LESENSED)
484 }
485 #[doc = "Low Energy Sensor Interface"]
486 #[inline(always)]
487 pub fn lesense(self) -> &'a mut W {
488 self.variant(SOURCESEL_A::LESENSE)
489 }
490 #[doc = "Analog Comparator 2"]
491 #[inline(always)]
492 pub fn acmp2(self) -> &'a mut W {
493 self.variant(SOURCESEL_A::ACMP2)
494 }
495 #[doc = "Analog to Digital Converter 0"]
496 #[inline(always)]
497 pub fn adc1(self) -> &'a mut W {
498 self.variant(SOURCESEL_A::ADC1)
499 }
500 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
501 #[inline(always)]
502 pub fn usart0(self) -> &'a mut W {
503 self.variant(SOURCESEL_A::USART0)
504 }
505 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
506 #[inline(always)]
507 pub fn usart1(self) -> &'a mut W {
508 self.variant(SOURCESEL_A::USART1)
509 }
510 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
511 #[inline(always)]
512 pub fn usart2(self) -> &'a mut W {
513 self.variant(SOURCESEL_A::USART2)
514 }
515 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
516 #[inline(always)]
517 pub fn usart3(self) -> &'a mut W {
518 self.variant(SOURCESEL_A::USART3)
519 }
520 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
521 #[inline(always)]
522 pub fn usart4(self) -> &'a mut W {
523 self.variant(SOURCESEL_A::USART4)
524 }
525 #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
526 #[inline(always)]
527 pub fn uart0(self) -> &'a mut W {
528 self.variant(SOURCESEL_A::UART0)
529 }
530 #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
531 #[inline(always)]
532 pub fn uart1(self) -> &'a mut W {
533 self.variant(SOURCESEL_A::UART1)
534 }
535 #[doc = "Timer 0"]
536 #[inline(always)]
537 pub fn timer0(self) -> &'a mut W {
538 self.variant(SOURCESEL_A::TIMER0)
539 }
540 #[doc = "Timer 1"]
541 #[inline(always)]
542 pub fn timer1(self) -> &'a mut W {
543 self.variant(SOURCESEL_A::TIMER1)
544 }
545 #[doc = "Timer 2"]
546 #[inline(always)]
547 pub fn timer2(self) -> &'a mut W {
548 self.variant(SOURCESEL_A::TIMER2)
549 }
550 #[doc = "Universal Serial Bus Interface"]
551 #[inline(always)]
552 pub fn usb(self) -> &'a mut W {
553 self.variant(SOURCESEL_A::USB)
554 }
555 #[doc = "`1000011`"]
556 #[inline(always)]
557 pub fn cm4(self) -> &'a mut W {
558 self.variant(SOURCESEL_A::CM4)
559 }
560 #[doc = "Timer 3"]
561 #[inline(always)]
562 pub fn timer3(self) -> &'a mut W {
563 self.variant(SOURCESEL_A::TIMER3)
564 }
565 #[doc = "Wide Timer 0"]
566 #[inline(always)]
567 pub fn wtimer0(self) -> &'a mut W {
568 self.variant(SOURCESEL_A::WTIMER0)
569 }
570 #[doc = "Wide Timer 0"]
571 #[inline(always)]
572 pub fn wtimer1(self) -> &'a mut W {
573 self.variant(SOURCESEL_A::WTIMER1)
574 }
575 #[doc = "PDM Interface"]
576 #[inline(always)]
577 pub fn pdm(self) -> &'a mut W {
578 self.variant(SOURCESEL_A::PDM)
579 }
580 #[doc = r"Writes raw bits to the field"]
581 #[inline(always)]
582 pub unsafe fn bits(self, value: u8) -> &'a mut W {
583 self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8);
584 self.w
585 }
586}
587#[doc = "Edge Detect Select\n\nValue on reset: 0"]
588#[derive(Clone, Copy, Debug, PartialEq)]
589#[repr(u8)]
590pub enum EDSEL_A {
591 #[doc = "0: Signal is left as it is"]
592 OFF = 0,
593 #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
594 POSEDGE = 1,
595 #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
596 NEGEDGE = 2,
597 #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
598 BOTHEDGES = 3,
599}
600impl From<EDSEL_A> for u8 {
601 #[inline(always)]
602 fn from(variant: EDSEL_A) -> Self {
603 variant as _
604 }
605}
606#[doc = "Reader of field `EDSEL`"]
607pub type EDSEL_R = crate::R<u8, EDSEL_A>;
608impl EDSEL_R {
609 #[doc = r"Get enumerated values variant"]
610 #[inline(always)]
611 pub fn variant(&self) -> EDSEL_A {
612 match self.bits {
613 0 => EDSEL_A::OFF,
614 1 => EDSEL_A::POSEDGE,
615 2 => EDSEL_A::NEGEDGE,
616 3 => EDSEL_A::BOTHEDGES,
617 _ => unreachable!(),
618 }
619 }
620 #[doc = "Checks if the value of the field is `OFF`"]
621 #[inline(always)]
622 pub fn is_off(&self) -> bool {
623 *self == EDSEL_A::OFF
624 }
625 #[doc = "Checks if the value of the field is `POSEDGE`"]
626 #[inline(always)]
627 pub fn is_posedge(&self) -> bool {
628 *self == EDSEL_A::POSEDGE
629 }
630 #[doc = "Checks if the value of the field is `NEGEDGE`"]
631 #[inline(always)]
632 pub fn is_negedge(&self) -> bool {
633 *self == EDSEL_A::NEGEDGE
634 }
635 #[doc = "Checks if the value of the field is `BOTHEDGES`"]
636 #[inline(always)]
637 pub fn is_bothedges(&self) -> bool {
638 *self == EDSEL_A::BOTHEDGES
639 }
640}
641#[doc = "Write proxy for field `EDSEL`"]
642pub struct EDSEL_W<'a> {
643 w: &'a mut W,
644}
645impl<'a> EDSEL_W<'a> {
646 #[doc = r"Writes `variant` to the field"]
647 #[inline(always)]
648 pub fn variant(self, variant: EDSEL_A) -> &'a mut W {
649 {
650 self.bits(variant.into())
651 }
652 }
653 #[doc = "Signal is left as it is"]
654 #[inline(always)]
655 pub fn off(self) -> &'a mut W {
656 self.variant(EDSEL_A::OFF)
657 }
658 #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
659 #[inline(always)]
660 pub fn posedge(self) -> &'a mut W {
661 self.variant(EDSEL_A::POSEDGE)
662 }
663 #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
664 #[inline(always)]
665 pub fn negedge(self) -> &'a mut W {
666 self.variant(EDSEL_A::NEGEDGE)
667 }
668 #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
669 #[inline(always)]
670 pub fn bothedges(self) -> &'a mut W {
671 self.variant(EDSEL_A::BOTHEDGES)
672 }
673 #[doc = r"Writes raw bits to the field"]
674 #[inline(always)]
675 pub fn bits(self, value: u8) -> &'a mut W {
676 self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
677 self.w
678 }
679}
680#[doc = "Reader of field `STRETCH`"]
681pub type STRETCH_R = crate::R<bool, bool>;
682#[doc = "Write proxy for field `STRETCH`"]
683pub struct STRETCH_W<'a> {
684 w: &'a mut W,
685}
686impl<'a> STRETCH_W<'a> {
687 #[doc = r"Sets the field bit"]
688 #[inline(always)]
689 pub fn set_bit(self) -> &'a mut W {
690 self.bit(true)
691 }
692 #[doc = r"Clears the field bit"]
693 #[inline(always)]
694 pub fn clear_bit(self) -> &'a mut W {
695 self.bit(false)
696 }
697 #[doc = r"Writes raw bits to the field"]
698 #[inline(always)]
699 pub fn bit(self, value: bool) -> &'a mut W {
700 self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
701 self.w
702 }
703}
704#[doc = "Reader of field `INV`"]
705pub type INV_R = crate::R<bool, bool>;
706#[doc = "Write proxy for field `INV`"]
707pub struct INV_W<'a> {
708 w: &'a mut W,
709}
710impl<'a> INV_W<'a> {
711 #[doc = r"Sets the field bit"]
712 #[inline(always)]
713 pub fn set_bit(self) -> &'a mut W {
714 self.bit(true)
715 }
716 #[doc = r"Clears the field bit"]
717 #[inline(always)]
718 pub fn clear_bit(self) -> &'a mut W {
719 self.bit(false)
720 }
721 #[doc = r"Writes raw bits to the field"]
722 #[inline(always)]
723 pub fn bit(self, value: bool) -> &'a mut W {
724 self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
725 self.w
726 }
727}
728#[doc = "Reader of field `ORPREV`"]
729pub type ORPREV_R = crate::R<bool, bool>;
730#[doc = "Write proxy for field `ORPREV`"]
731pub struct ORPREV_W<'a> {
732 w: &'a mut W,
733}
734impl<'a> ORPREV_W<'a> {
735 #[doc = r"Sets the field bit"]
736 #[inline(always)]
737 pub fn set_bit(self) -> &'a mut W {
738 self.bit(true)
739 }
740 #[doc = r"Clears the field bit"]
741 #[inline(always)]
742 pub fn clear_bit(self) -> &'a mut W {
743 self.bit(false)
744 }
745 #[doc = r"Writes raw bits to the field"]
746 #[inline(always)]
747 pub fn bit(self, value: bool) -> &'a mut W {
748 self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
749 self.w
750 }
751}
752#[doc = "Reader of field `ANDNEXT`"]
753pub type ANDNEXT_R = crate::R<bool, bool>;
754#[doc = "Write proxy for field `ANDNEXT`"]
755pub struct ANDNEXT_W<'a> {
756 w: &'a mut W,
757}
758impl<'a> ANDNEXT_W<'a> {
759 #[doc = r"Sets the field bit"]
760 #[inline(always)]
761 pub fn set_bit(self) -> &'a mut W {
762 self.bit(true)
763 }
764 #[doc = r"Clears the field bit"]
765 #[inline(always)]
766 pub fn clear_bit(self) -> &'a mut W {
767 self.bit(false)
768 }
769 #[doc = r"Writes raw bits to the field"]
770 #[inline(always)]
771 pub fn bit(self, value: bool) -> &'a mut W {
772 self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
773 self.w
774 }
775}
776#[doc = "Reader of field `ASYNC`"]
777pub type ASYNC_R = crate::R<bool, bool>;
778#[doc = "Write proxy for field `ASYNC`"]
779pub struct ASYNC_W<'a> {
780 w: &'a mut W,
781}
782impl<'a> ASYNC_W<'a> {
783 #[doc = r"Sets the field bit"]
784 #[inline(always)]
785 pub fn set_bit(self) -> &'a mut W {
786 self.bit(true)
787 }
788 #[doc = r"Clears the field bit"]
789 #[inline(always)]
790 pub fn clear_bit(self) -> &'a mut W {
791 self.bit(false)
792 }
793 #[doc = r"Writes raw bits to the field"]
794 #[inline(always)]
795 pub fn bit(self, value: bool) -> &'a mut W {
796 self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
797 self.w
798 }
799}
800impl R {
801 #[doc = "Bits 0:2 - Signal Select"]
802 #[inline(always)]
803 pub fn sigsel(&self) -> SIGSEL_R {
804 SIGSEL_R::new((self.bits & 0x07) as u8)
805 }
806 #[doc = "Bits 8:14 - Source Select"]
807 #[inline(always)]
808 pub fn sourcesel(&self) -> SOURCESEL_R {
809 SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
810 }
811 #[doc = "Bits 20:21 - Edge Detect Select"]
812 #[inline(always)]
813 pub fn edsel(&self) -> EDSEL_R {
814 EDSEL_R::new(((self.bits >> 20) & 0x03) as u8)
815 }
816 #[doc = "Bit 25 - Stretch Channel Output"]
817 #[inline(always)]
818 pub fn stretch(&self) -> STRETCH_R {
819 STRETCH_R::new(((self.bits >> 25) & 0x01) != 0)
820 }
821 #[doc = "Bit 26 - Invert Channel"]
822 #[inline(always)]
823 pub fn inv(&self) -> INV_R {
824 INV_R::new(((self.bits >> 26) & 0x01) != 0)
825 }
826 #[doc = "Bit 27 - Or Previous"]
827 #[inline(always)]
828 pub fn orprev(&self) -> ORPREV_R {
829 ORPREV_R::new(((self.bits >> 27) & 0x01) != 0)
830 }
831 #[doc = "Bit 28 - And Next"]
832 #[inline(always)]
833 pub fn andnext(&self) -> ANDNEXT_R {
834 ANDNEXT_R::new(((self.bits >> 28) & 0x01) != 0)
835 }
836 #[doc = "Bit 30 - Asynchronous Reflex"]
837 #[inline(always)]
838 pub fn async(&self) -> ASYNC_R {
839 ASYNC_R::new(((self.bits >> 30) & 0x01) != 0)
840 }
841}
842impl W {
843 #[doc = "Bits 0:2 - Signal Select"]
844 #[inline(always)]
845 pub fn sigsel(&mut self) -> SIGSEL_W {
846 SIGSEL_W { w: self }
847 }
848 #[doc = "Bits 8:14 - Source Select"]
849 #[inline(always)]
850 pub fn sourcesel(&mut self) -> SOURCESEL_W {
851 SOURCESEL_W { w: self }
852 }
853 #[doc = "Bits 20:21 - Edge Detect Select"]
854 #[inline(always)]
855 pub fn edsel(&mut self) -> EDSEL_W {
856 EDSEL_W { w: self }
857 }
858 #[doc = "Bit 25 - Stretch Channel Output"]
859 #[inline(always)]
860 pub fn stretch(&mut self) -> STRETCH_W {
861 STRETCH_W { w: self }
862 }
863 #[doc = "Bit 26 - Invert Channel"]
864 #[inline(always)]
865 pub fn inv(&mut self) -> INV_W {
866 INV_W { w: self }
867 }
868 #[doc = "Bit 27 - Or Previous"]
869 #[inline(always)]
870 pub fn orprev(&mut self) -> ORPREV_W {
871 ORPREV_W { w: self }
872 }
873 #[doc = "Bit 28 - And Next"]
874 #[inline(always)]
875 pub fn andnext(&mut self) -> ANDNEXT_W {
876 ANDNEXT_W { w: self }
877 }
878 #[doc = "Bit 30 - Asynchronous Reflex"]
879 #[inline(always)]
880 pub fn async(&mut self) -> ASYNC_W {
881 ASYNC_W { w: self }
882 }
883}