efm32gg12b810/msc/
eccctrl.rs

1#[doc = "Reader of register ECCCTRL"]
2pub type R = crate::R<u32, super::ECCCTRL>;
3#[doc = "Writer for register ECCCTRL"]
4pub type W = crate::W<u32, super::ECCCTRL>;
5#[doc = "Register ECCCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::ECCCTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `RAMECCEWEN`"]
14pub type RAMECCEWEN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `RAMECCEWEN`"]
16pub struct RAMECCEWEN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RAMECCEWEN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `RAMECCCHKEN`"]
38pub type RAMECCCHKEN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `RAMECCCHKEN`"]
40pub struct RAMECCCHKEN_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> RAMECCCHKEN_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58        self.w
59    }
60}
61#[doc = "Reader of field `RAM1ECCEWEN`"]
62pub type RAM1ECCEWEN_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `RAM1ECCEWEN`"]
64pub struct RAM1ECCEWEN_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> RAM1ECCEWEN_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82        self.w
83    }
84}
85#[doc = "Reader of field `RAM1ECCCHKEN`"]
86pub type RAM1ECCCHKEN_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `RAM1ECCCHKEN`"]
88pub struct RAM1ECCCHKEN_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> RAM1ECCCHKEN_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
106        self.w
107    }
108}
109#[doc = "Reader of field `RAM2ECCEWEN`"]
110pub type RAM2ECCEWEN_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `RAM2ECCEWEN`"]
112pub struct RAM2ECCEWEN_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> RAM2ECCEWEN_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
130        self.w
131    }
132}
133#[doc = "Reader of field `RAM2ECCCHKEN`"]
134pub type RAM2ECCCHKEN_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `RAM2ECCCHKEN`"]
136pub struct RAM2ECCCHKEN_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> RAM2ECCCHKEN_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
154        self.w
155    }
156}
157impl R {
158    #[doc = "Bit 0 - RAM ECC Write Enable"]
159    #[inline(always)]
160    pub fn rameccewen(&self) -> RAMECCEWEN_R {
161        RAMECCEWEN_R::new((self.bits & 0x01) != 0)
162    }
163    #[doc = "Bit 1 - RAM ECC Check Enable"]
164    #[inline(always)]
165    pub fn rameccchken(&self) -> RAMECCCHKEN_R {
166        RAMECCCHKEN_R::new(((self.bits >> 1) & 0x01) != 0)
167    }
168    #[doc = "Bit 2 - RAM1 ECC Write Enable"]
169    #[inline(always)]
170    pub fn ram1eccewen(&self) -> RAM1ECCEWEN_R {
171        RAM1ECCEWEN_R::new(((self.bits >> 2) & 0x01) != 0)
172    }
173    #[doc = "Bit 3 - RAM1 ECC Check Enable"]
174    #[inline(always)]
175    pub fn ram1eccchken(&self) -> RAM1ECCCHKEN_R {
176        RAM1ECCCHKEN_R::new(((self.bits >> 3) & 0x01) != 0)
177    }
178    #[doc = "Bit 4 - RAM2 ECC Write Enable"]
179    #[inline(always)]
180    pub fn ram2eccewen(&self) -> RAM2ECCEWEN_R {
181        RAM2ECCEWEN_R::new(((self.bits >> 4) & 0x01) != 0)
182    }
183    #[doc = "Bit 5 - RAM2 ECC Check Enable"]
184    #[inline(always)]
185    pub fn ram2eccchken(&self) -> RAM2ECCCHKEN_R {
186        RAM2ECCCHKEN_R::new(((self.bits >> 5) & 0x01) != 0)
187    }
188}
189impl W {
190    #[doc = "Bit 0 - RAM ECC Write Enable"]
191    #[inline(always)]
192    pub fn rameccewen(&mut self) -> RAMECCEWEN_W {
193        RAMECCEWEN_W { w: self }
194    }
195    #[doc = "Bit 1 - RAM ECC Check Enable"]
196    #[inline(always)]
197    pub fn rameccchken(&mut self) -> RAMECCCHKEN_W {
198        RAMECCCHKEN_W { w: self }
199    }
200    #[doc = "Bit 2 - RAM1 ECC Write Enable"]
201    #[inline(always)]
202    pub fn ram1eccewen(&mut self) -> RAM1ECCEWEN_W {
203        RAM1ECCEWEN_W { w: self }
204    }
205    #[doc = "Bit 3 - RAM1 ECC Check Enable"]
206    #[inline(always)]
207    pub fn ram1eccchken(&mut self) -> RAM1ECCCHKEN_W {
208        RAM1ECCCHKEN_W { w: self }
209    }
210    #[doc = "Bit 4 - RAM2 ECC Write Enable"]
211    #[inline(always)]
212    pub fn ram2eccewen(&mut self) -> RAM2ECCEWEN_W {
213        RAM2ECCEWEN_W { w: self }
214    }
215    #[doc = "Bit 5 - RAM2 ECC Check Enable"]
216    #[inline(always)]
217    pub fn ram2eccchken(&mut self) -> RAM2ECCCHKEN_W {
218        RAM2ECCCHKEN_W { w: self }
219    }
220}
efm32gg12b810/msc/eccctrl.rs

efm32gg12b810/msc/
eccctrl.rs
