efm32gg12b810_pac/usb/
doep2_int.rs

1#[doc = "Register `DOEP2_INT` reader"]
2pub struct R(crate::R<DOEP2_INT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DOEP2_INT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DOEP2_INT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DOEP2_INT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DOEP2_INT` writer"]
17pub struct W(crate::W<DOEP2_INT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DOEP2_INT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DOEP2_INT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DOEP2_INT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `XFERCOMPL` reader - Transfer Completed Interrupt"]
38pub type XFERCOMPL_R = crate::BitReader<bool>;
39#[doc = "Field `XFERCOMPL` writer - Transfer Completed Interrupt"]
40pub type XFERCOMPL_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 0>;
41#[doc = "Field `EPDISBLD` reader - Endpoint Disabled Interrupt"]
42pub type EPDISBLD_R = crate::BitReader<bool>;
43#[doc = "Field `EPDISBLD` writer - Endpoint Disabled Interrupt"]
44pub type EPDISBLD_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 1>;
45#[doc = "Field `AHBERR` reader - AHB Error"]
46pub type AHBERR_R = crate::BitReader<bool>;
47#[doc = "Field `AHBERR` writer - AHB Error"]
48pub type AHBERR_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 2>;
49#[doc = "Field `SETUP` reader - Setup Phase Done"]
50pub type SETUP_R = crate::BitReader<bool>;
51#[doc = "Field `SETUP` writer - Setup Phase Done"]
52pub type SETUP_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 3>;
53#[doc = "Field `OUTTKNEPDIS` reader - OUT Token Received When Endpoint Disabled"]
54pub type OUTTKNEPDIS_R = crate::BitReader<bool>;
55#[doc = "Field `OUTTKNEPDIS` writer - OUT Token Received When Endpoint Disabled"]
56pub type OUTTKNEPDIS_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 4>;
57#[doc = "Field `STSPHSERCVD` reader - Status Phase Received For Control Write"]
58pub type STSPHSERCVD_R = crate::BitReader<bool>;
59#[doc = "Field `STSPHSERCVD` writer - Status Phase Received For Control Write"]
60pub type STSPHSERCVD_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 5>;
61#[doc = "Field `BACK2BACKSETUP` reader - Back-to-Back SETUP Packets Received"]
62pub type BACK2BACKSETUP_R = crate::BitReader<bool>;
63#[doc = "Field `BACK2BACKSETUP` writer - Back-to-Back SETUP Packets Received"]
64pub type BACK2BACKSETUP_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 6>;
65#[doc = "Field `OUTPKTERR` reader - OUT Packet Error"]
66pub type OUTPKTERR_R = crate::BitReader<bool>;
67#[doc = "Field `OUTPKTERR` writer - OUT Packet Error"]
68pub type OUTPKTERR_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 8>;
69#[doc = "Field `PKTDRPSTS` reader - Packet Drop Status"]
70pub type PKTDRPSTS_R = crate::BitReader<bool>;
71#[doc = "Field `PKTDRPSTS` writer - Packet Drop Status"]
72pub type PKTDRPSTS_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 11>;
73#[doc = "Field `BBLEERR` reader - Babble Error"]
74pub type BBLEERR_R = crate::BitReader<bool>;
75#[doc = "Field `BBLEERR` writer - Babble Error"]
76pub type BBLEERR_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 12>;
77#[doc = "Field `NAKINTRPT` reader - NAK Interrupt"]
78pub type NAKINTRPT_R = crate::BitReader<bool>;
79#[doc = "Field `NAKINTRPT` writer - NAK Interrupt"]
80pub type NAKINTRPT_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 13>;
81#[doc = "Field `STUPPKTRCVD` reader - "]
82pub type STUPPKTRCVD_R = crate::BitReader<bool>;
83#[doc = "Field `STUPPKTRCVD` writer - "]
84pub type STUPPKTRCVD_W<'a> = crate::BitWriter<'a, u32, DOEP2_INT_SPEC, bool, 15>;
85impl R {
86    #[doc = "Bit 0 - Transfer Completed Interrupt"]
87    #[inline(always)]
88    pub fn xfercompl(&self) -> XFERCOMPL_R {
89        XFERCOMPL_R::new((self.bits & 1) != 0)
90    }
91    #[doc = "Bit 1 - Endpoint Disabled Interrupt"]
92    #[inline(always)]
93    pub fn epdisbld(&self) -> EPDISBLD_R {
94        EPDISBLD_R::new(((self.bits >> 1) & 1) != 0)
95    }
96    #[doc = "Bit 2 - AHB Error"]
97    #[inline(always)]
98    pub fn ahberr(&self) -> AHBERR_R {
99        AHBERR_R::new(((self.bits >> 2) & 1) != 0)
100    }
101    #[doc = "Bit 3 - Setup Phase Done"]
102    #[inline(always)]
103    pub fn setup(&self) -> SETUP_R {
104        SETUP_R::new(((self.bits >> 3) & 1) != 0)
105    }
106    #[doc = "Bit 4 - OUT Token Received When Endpoint Disabled"]
107    #[inline(always)]
108    pub fn outtknepdis(&self) -> OUTTKNEPDIS_R {
109        OUTTKNEPDIS_R::new(((self.bits >> 4) & 1) != 0)
110    }
111    #[doc = "Bit 5 - Status Phase Received For Control Write"]
112    #[inline(always)]
113    pub fn stsphsercvd(&self) -> STSPHSERCVD_R {
114        STSPHSERCVD_R::new(((self.bits >> 5) & 1) != 0)
115    }
116    #[doc = "Bit 6 - Back-to-Back SETUP Packets Received"]
117    #[inline(always)]
118    pub fn back2backsetup(&self) -> BACK2BACKSETUP_R {
119        BACK2BACKSETUP_R::new(((self.bits >> 6) & 1) != 0)
120    }
121    #[doc = "Bit 8 - OUT Packet Error"]
122    #[inline(always)]
123    pub fn outpkterr(&self) -> OUTPKTERR_R {
124        OUTPKTERR_R::new(((self.bits >> 8) & 1) != 0)
125    }
126    #[doc = "Bit 11 - Packet Drop Status"]
127    #[inline(always)]
128    pub fn pktdrpsts(&self) -> PKTDRPSTS_R {
129        PKTDRPSTS_R::new(((self.bits >> 11) & 1) != 0)
130    }
131    #[doc = "Bit 12 - Babble Error"]
132    #[inline(always)]
133    pub fn bbleerr(&self) -> BBLEERR_R {
134        BBLEERR_R::new(((self.bits >> 12) & 1) != 0)
135    }
136    #[doc = "Bit 13 - NAK Interrupt"]
137    #[inline(always)]
138    pub fn nakintrpt(&self) -> NAKINTRPT_R {
139        NAKINTRPT_R::new(((self.bits >> 13) & 1) != 0)
140    }
141    #[doc = "Bit 15"]
142    #[inline(always)]
143    pub fn stuppktrcvd(&self) -> STUPPKTRCVD_R {
144        STUPPKTRCVD_R::new(((self.bits >> 15) & 1) != 0)
145    }
146}
147impl W {
148    #[doc = "Bit 0 - Transfer Completed Interrupt"]
149    #[inline(always)]
150    pub fn xfercompl(&mut self) -> XFERCOMPL_W {
151        XFERCOMPL_W::new(self)
152    }
153    #[doc = "Bit 1 - Endpoint Disabled Interrupt"]
154    #[inline(always)]
155    pub fn epdisbld(&mut self) -> EPDISBLD_W {
156        EPDISBLD_W::new(self)
157    }
158    #[doc = "Bit 2 - AHB Error"]
159    #[inline(always)]
160    pub fn ahberr(&mut self) -> AHBERR_W {
161        AHBERR_W::new(self)
162    }
163    #[doc = "Bit 3 - Setup Phase Done"]
164    #[inline(always)]
165    pub fn setup(&mut self) -> SETUP_W {
166        SETUP_W::new(self)
167    }
168    #[doc = "Bit 4 - OUT Token Received When Endpoint Disabled"]
169    #[inline(always)]
170    pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W {
171        OUTTKNEPDIS_W::new(self)
172    }
173    #[doc = "Bit 5 - Status Phase Received For Control Write"]
174    #[inline(always)]
175    pub fn stsphsercvd(&mut self) -> STSPHSERCVD_W {
176        STSPHSERCVD_W::new(self)
177    }
178    #[doc = "Bit 6 - Back-to-Back SETUP Packets Received"]
179    #[inline(always)]
180    pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W {
181        BACK2BACKSETUP_W::new(self)
182    }
183    #[doc = "Bit 8 - OUT Packet Error"]
184    #[inline(always)]
185    pub fn outpkterr(&mut self) -> OUTPKTERR_W {
186        OUTPKTERR_W::new(self)
187    }
188    #[doc = "Bit 11 - Packet Drop Status"]
189    #[inline(always)]
190    pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W {
191        PKTDRPSTS_W::new(self)
192    }
193    #[doc = "Bit 12 - Babble Error"]
194    #[inline(always)]
195    pub fn bbleerr(&mut self) -> BBLEERR_W {
196        BBLEERR_W::new(self)
197    }
198    #[doc = "Bit 13 - NAK Interrupt"]
199    #[inline(always)]
200    pub fn nakintrpt(&mut self) -> NAKINTRPT_W {
201        NAKINTRPT_W::new(self)
202    }
203    #[doc = "Bit 15"]
204    #[inline(always)]
205    pub fn stuppktrcvd(&mut self) -> STUPPKTRCVD_W {
206        STUPPKTRCVD_W::new(self)
207    }
208    #[doc = "Writes raw bits to the register."]
209    #[inline(always)]
210    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
211        self.0.bits(bits);
212        self
213    }
214}
215#[doc = "Device OUT Endpoint x+1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep2_int](index.html) module"]
216pub struct DOEP2_INT_SPEC;
217impl crate::RegisterSpec for DOEP2_INT_SPEC {
218    type Ux = u32;
219}
220#[doc = "`read()` method returns [doep2_int::R](R) reader structure"]
221impl crate::Readable for DOEP2_INT_SPEC {
222    type Reader = R;
223}
224#[doc = "`write(|w| ..)` method takes [doep2_int::W](W) writer structure"]
225impl crate::Writable for DOEP2_INT_SPEC {
226    type Writer = W;
227}
228#[doc = "`reset()` method sets DOEP2_INT to value 0"]
229impl crate::Resettable for DOEP2_INT_SPEC {
230    #[inline(always)]
231    fn reset_value() -> Self::Ux {
232        0
233    }
234}
efm32gg12b810_pac/usb/doep2_int.rs

efm32gg12b810_pac/usb/
doep2_int.rs
