1#[doc = "Register `PPUPATD1` reader"]
2pub struct R(crate::R<PPUPATD1_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<PPUPATD1_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<PPUPATD1_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<PPUPATD1_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `PPUPATD1` writer"]
17pub struct W(crate::W<PPUPATD1_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<PPUPATD1_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<PPUPATD1_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<PPUPATD1_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `PCNT0` reader - Pulse Counter 0 access control bit"]
38pub type PCNT0_R = crate::BitReader<bool>;
39#[doc = "Field `PCNT0` writer - Pulse Counter 0 access control bit"]
40pub type PCNT0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 0>;
41#[doc = "Field `PCNT1` reader - Pulse Counter 1 access control bit"]
42pub type PCNT1_R = crate::BitReader<bool>;
43#[doc = "Field `PCNT1` writer - Pulse Counter 1 access control bit"]
44pub type PCNT1_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 1>;
45#[doc = "Field `PCNT2` reader - Pulse Counter 2 access control bit"]
46pub type PCNT2_R = crate::BitReader<bool>;
47#[doc = "Field `PCNT2` writer - Pulse Counter 2 access control bit"]
48pub type PCNT2_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 2>;
49#[doc = "Field `PDM` reader - PDM Interface access control bit"]
50pub type PDM_R = crate::BitReader<bool>;
51#[doc = "Field `PDM` writer - PDM Interface access control bit"]
52pub type PDM_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 3>;
53#[doc = "Field `QSPI0` reader - Quad-SPI access control bit"]
54pub type QSPI0_R = crate::BitReader<bool>;
55#[doc = "Field `QSPI0` writer - Quad-SPI access control bit"]
56pub type QSPI0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 4>;
57#[doc = "Field `RMU` reader - Reset Management Unit access control bit"]
58pub type RMU_R = crate::BitReader<bool>;
59#[doc = "Field `RMU` writer - Reset Management Unit access control bit"]
60pub type RMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 5>;
61#[doc = "Field `RTC` reader - Real-Time Counter access control bit"]
62pub type RTC_R = crate::BitReader<bool>;
63#[doc = "Field `RTC` writer - Real-Time Counter access control bit"]
64pub type RTC_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 6>;
65#[doc = "Field `RTCC` reader - Real-Time Counter and Calendar access control bit"]
66pub type RTCC_R = crate::BitReader<bool>;
67#[doc = "Field `RTCC` writer - Real-Time Counter and Calendar access control bit"]
68pub type RTCC_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 7>;
69#[doc = "Field `SDIO` reader - SDIO Controller access control bit"]
70pub type SDIO_R = crate::BitReader<bool>;
71#[doc = "Field `SDIO` writer - SDIO Controller access control bit"]
72pub type SDIO_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 8>;
73#[doc = "Field `SMU` reader - Security Management Unit access control bit"]
74pub type SMU_R = crate::BitReader<bool>;
75#[doc = "Field `SMU` writer - Security Management Unit access control bit"]
76pub type SMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 9>;
77#[doc = "Field `TIMER0` reader - Timer 0 access control bit"]
78pub type TIMER0_R = crate::BitReader<bool>;
79#[doc = "Field `TIMER0` writer - Timer 0 access control bit"]
80pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 10>;
81#[doc = "Field `TIMER1` reader - Timer 1 access control bit"]
82pub type TIMER1_R = crate::BitReader<bool>;
83#[doc = "Field `TIMER1` writer - Timer 1 access control bit"]
84pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 11>;
85#[doc = "Field `TIMER2` reader - Timer 2 access control bit"]
86pub type TIMER2_R = crate::BitReader<bool>;
87#[doc = "Field `TIMER2` writer - Timer 2 access control bit"]
88pub type TIMER2_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 12>;
89#[doc = "Field `TIMER3` reader - Timer 3 access control bit"]
90pub type TIMER3_R = crate::BitReader<bool>;
91#[doc = "Field `TIMER3` writer - Timer 3 access control bit"]
92pub type TIMER3_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 13>;
93#[doc = "Field `TRNG0` reader - True Random Number Generator 0 access control bit"]
94pub type TRNG0_R = crate::BitReader<bool>;
95#[doc = "Field `TRNG0` writer - True Random Number Generator 0 access control bit"]
96pub type TRNG0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 14>;
97#[doc = "Field `UART0` reader - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
98pub type UART0_R = crate::BitReader<bool>;
99#[doc = "Field `UART0` writer - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
100pub type UART0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 15>;
101#[doc = "Field `UART1` reader - Universal Asynchronous Receiver/Transmitter 1 access control bit"]
102pub type UART1_R = crate::BitReader<bool>;
103#[doc = "Field `UART1` writer - Universal Asynchronous Receiver/Transmitter 1 access control bit"]
104pub type UART1_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 16>;
105#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
106pub type USART0_R = crate::BitReader<bool>;
107#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
108pub type USART0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 17>;
109#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
110pub type USART1_R = crate::BitReader<bool>;
111#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
112pub type USART1_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 18>;
113#[doc = "Field `USART2` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
114pub type USART2_R = crate::BitReader<bool>;
115#[doc = "Field `USART2` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
116pub type USART2_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 19>;
117#[doc = "Field `USART3` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
118pub type USART3_R = crate::BitReader<bool>;
119#[doc = "Field `USART3` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
120pub type USART3_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 20>;
121#[doc = "Field `USART4` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit"]
122pub type USART4_R = crate::BitReader<bool>;
123#[doc = "Field `USART4` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit"]
124pub type USART4_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 21>;
125#[doc = "Field `USB` reader - Universal Serial Bus Interface access control bit"]
126pub type USB_R = crate::BitReader<bool>;
127#[doc = "Field `USB` writer - Universal Serial Bus Interface access control bit"]
128pub type USB_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 22>;
129#[doc = "Field `WDOG0` reader - Watchdog access control bit"]
130pub type WDOG0_R = crate::BitReader<bool>;
131#[doc = "Field `WDOG0` writer - Watchdog access control bit"]
132pub type WDOG0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 23>;
133#[doc = "Field `WDOG1` reader - Watchdog access control bit"]
134pub type WDOG1_R = crate::BitReader<bool>;
135#[doc = "Field `WDOG1` writer - Watchdog access control bit"]
136pub type WDOG1_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 24>;
137#[doc = "Field `WTIMER0` reader - Wide Timer 0 access control bit"]
138pub type WTIMER0_R = crate::BitReader<bool>;
139#[doc = "Field `WTIMER0` writer - Wide Timer 0 access control bit"]
140pub type WTIMER0_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 25>;
141#[doc = "Field `WTIMER1` reader - Wide Timer 0 access control bit"]
142pub type WTIMER1_R = crate::BitReader<bool>;
143#[doc = "Field `WTIMER1` writer - Wide Timer 0 access control bit"]
144pub type WTIMER1_W<'a> = crate::BitWriter<'a, u32, PPUPATD1_SPEC, bool, 26>;
145impl R {
146 #[doc = "Bit 0 - Pulse Counter 0 access control bit"]
147 #[inline(always)]
148 pub fn pcnt0(&self) -> PCNT0_R {
149 PCNT0_R::new((self.bits & 1) != 0)
150 }
151 #[doc = "Bit 1 - Pulse Counter 1 access control bit"]
152 #[inline(always)]
153 pub fn pcnt1(&self) -> PCNT1_R {
154 PCNT1_R::new(((self.bits >> 1) & 1) != 0)
155 }
156 #[doc = "Bit 2 - Pulse Counter 2 access control bit"]
157 #[inline(always)]
158 pub fn pcnt2(&self) -> PCNT2_R {
159 PCNT2_R::new(((self.bits >> 2) & 1) != 0)
160 }
161 #[doc = "Bit 3 - PDM Interface access control bit"]
162 #[inline(always)]
163 pub fn pdm(&self) -> PDM_R {
164 PDM_R::new(((self.bits >> 3) & 1) != 0)
165 }
166 #[doc = "Bit 4 - Quad-SPI access control bit"]
167 #[inline(always)]
168 pub fn qspi0(&self) -> QSPI0_R {
169 QSPI0_R::new(((self.bits >> 4) & 1) != 0)
170 }
171 #[doc = "Bit 5 - Reset Management Unit access control bit"]
172 #[inline(always)]
173 pub fn rmu(&self) -> RMU_R {
174 RMU_R::new(((self.bits >> 5) & 1) != 0)
175 }
176 #[doc = "Bit 6 - Real-Time Counter access control bit"]
177 #[inline(always)]
178 pub fn rtc(&self) -> RTC_R {
179 RTC_R::new(((self.bits >> 6) & 1) != 0)
180 }
181 #[doc = "Bit 7 - Real-Time Counter and Calendar access control bit"]
182 #[inline(always)]
183 pub fn rtcc(&self) -> RTCC_R {
184 RTCC_R::new(((self.bits >> 7) & 1) != 0)
185 }
186 #[doc = "Bit 8 - SDIO Controller access control bit"]
187 #[inline(always)]
188 pub fn sdio(&self) -> SDIO_R {
189 SDIO_R::new(((self.bits >> 8) & 1) != 0)
190 }
191 #[doc = "Bit 9 - Security Management Unit access control bit"]
192 #[inline(always)]
193 pub fn smu(&self) -> SMU_R {
194 SMU_R::new(((self.bits >> 9) & 1) != 0)
195 }
196 #[doc = "Bit 10 - Timer 0 access control bit"]
197 #[inline(always)]
198 pub fn timer0(&self) -> TIMER0_R {
199 TIMER0_R::new(((self.bits >> 10) & 1) != 0)
200 }
201 #[doc = "Bit 11 - Timer 1 access control bit"]
202 #[inline(always)]
203 pub fn timer1(&self) -> TIMER1_R {
204 TIMER1_R::new(((self.bits >> 11) & 1) != 0)
205 }
206 #[doc = "Bit 12 - Timer 2 access control bit"]
207 #[inline(always)]
208 pub fn timer2(&self) -> TIMER2_R {
209 TIMER2_R::new(((self.bits >> 12) & 1) != 0)
210 }
211 #[doc = "Bit 13 - Timer 3 access control bit"]
212 #[inline(always)]
213 pub fn timer3(&self) -> TIMER3_R {
214 TIMER3_R::new(((self.bits >> 13) & 1) != 0)
215 }
216 #[doc = "Bit 14 - True Random Number Generator 0 access control bit"]
217 #[inline(always)]
218 pub fn trng0(&self) -> TRNG0_R {
219 TRNG0_R::new(((self.bits >> 14) & 1) != 0)
220 }
221 #[doc = "Bit 15 - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
222 #[inline(always)]
223 pub fn uart0(&self) -> UART0_R {
224 UART0_R::new(((self.bits >> 15) & 1) != 0)
225 }
226 #[doc = "Bit 16 - Universal Asynchronous Receiver/Transmitter 1 access control bit"]
227 #[inline(always)]
228 pub fn uart1(&self) -> UART1_R {
229 UART1_R::new(((self.bits >> 16) & 1) != 0)
230 }
231 #[doc = "Bit 17 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
232 #[inline(always)]
233 pub fn usart0(&self) -> USART0_R {
234 USART0_R::new(((self.bits >> 17) & 1) != 0)
235 }
236 #[doc = "Bit 18 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
237 #[inline(always)]
238 pub fn usart1(&self) -> USART1_R {
239 USART1_R::new(((self.bits >> 18) & 1) != 0)
240 }
241 #[doc = "Bit 19 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
242 #[inline(always)]
243 pub fn usart2(&self) -> USART2_R {
244 USART2_R::new(((self.bits >> 19) & 1) != 0)
245 }
246 #[doc = "Bit 20 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
247 #[inline(always)]
248 pub fn usart3(&self) -> USART3_R {
249 USART3_R::new(((self.bits >> 20) & 1) != 0)
250 }
251 #[doc = "Bit 21 - Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit"]
252 #[inline(always)]
253 pub fn usart4(&self) -> USART4_R {
254 USART4_R::new(((self.bits >> 21) & 1) != 0)
255 }
256 #[doc = "Bit 22 - Universal Serial Bus Interface access control bit"]
257 #[inline(always)]
258 pub fn usb(&self) -> USB_R {
259 USB_R::new(((self.bits >> 22) & 1) != 0)
260 }
261 #[doc = "Bit 23 - Watchdog access control bit"]
262 #[inline(always)]
263 pub fn wdog0(&self) -> WDOG0_R {
264 WDOG0_R::new(((self.bits >> 23) & 1) != 0)
265 }
266 #[doc = "Bit 24 - Watchdog access control bit"]
267 #[inline(always)]
268 pub fn wdog1(&self) -> WDOG1_R {
269 WDOG1_R::new(((self.bits >> 24) & 1) != 0)
270 }
271 #[doc = "Bit 25 - Wide Timer 0 access control bit"]
272 #[inline(always)]
273 pub fn wtimer0(&self) -> WTIMER0_R {
274 WTIMER0_R::new(((self.bits >> 25) & 1) != 0)
275 }
276 #[doc = "Bit 26 - Wide Timer 0 access control bit"]
277 #[inline(always)]
278 pub fn wtimer1(&self) -> WTIMER1_R {
279 WTIMER1_R::new(((self.bits >> 26) & 1) != 0)
280 }
281}
282impl W {
283 #[doc = "Bit 0 - Pulse Counter 0 access control bit"]
284 #[inline(always)]
285 pub fn pcnt0(&mut self) -> PCNT0_W {
286 PCNT0_W::new(self)
287 }
288 #[doc = "Bit 1 - Pulse Counter 1 access control bit"]
289 #[inline(always)]
290 pub fn pcnt1(&mut self) -> PCNT1_W {
291 PCNT1_W::new(self)
292 }
293 #[doc = "Bit 2 - Pulse Counter 2 access control bit"]
294 #[inline(always)]
295 pub fn pcnt2(&mut self) -> PCNT2_W {
296 PCNT2_W::new(self)
297 }
298 #[doc = "Bit 3 - PDM Interface access control bit"]
299 #[inline(always)]
300 pub fn pdm(&mut self) -> PDM_W {
301 PDM_W::new(self)
302 }
303 #[doc = "Bit 4 - Quad-SPI access control bit"]
304 #[inline(always)]
305 pub fn qspi0(&mut self) -> QSPI0_W {
306 QSPI0_W::new(self)
307 }
308 #[doc = "Bit 5 - Reset Management Unit access control bit"]
309 #[inline(always)]
310 pub fn rmu(&mut self) -> RMU_W {
311 RMU_W::new(self)
312 }
313 #[doc = "Bit 6 - Real-Time Counter access control bit"]
314 #[inline(always)]
315 pub fn rtc(&mut self) -> RTC_W {
316 RTC_W::new(self)
317 }
318 #[doc = "Bit 7 - Real-Time Counter and Calendar access control bit"]
319 #[inline(always)]
320 pub fn rtcc(&mut self) -> RTCC_W {
321 RTCC_W::new(self)
322 }
323 #[doc = "Bit 8 - SDIO Controller access control bit"]
324 #[inline(always)]
325 pub fn sdio(&mut self) -> SDIO_W {
326 SDIO_W::new(self)
327 }
328 #[doc = "Bit 9 - Security Management Unit access control bit"]
329 #[inline(always)]
330 pub fn smu(&mut self) -> SMU_W {
331 SMU_W::new(self)
332 }
333 #[doc = "Bit 10 - Timer 0 access control bit"]
334 #[inline(always)]
335 pub fn timer0(&mut self) -> TIMER0_W {
336 TIMER0_W::new(self)
337 }
338 #[doc = "Bit 11 - Timer 1 access control bit"]
339 #[inline(always)]
340 pub fn timer1(&mut self) -> TIMER1_W {
341 TIMER1_W::new(self)
342 }
343 #[doc = "Bit 12 - Timer 2 access control bit"]
344 #[inline(always)]
345 pub fn timer2(&mut self) -> TIMER2_W {
346 TIMER2_W::new(self)
347 }
348 #[doc = "Bit 13 - Timer 3 access control bit"]
349 #[inline(always)]
350 pub fn timer3(&mut self) -> TIMER3_W {
351 TIMER3_W::new(self)
352 }
353 #[doc = "Bit 14 - True Random Number Generator 0 access control bit"]
354 #[inline(always)]
355 pub fn trng0(&mut self) -> TRNG0_W {
356 TRNG0_W::new(self)
357 }
358 #[doc = "Bit 15 - Universal Asynchronous Receiver/Transmitter 0 access control bit"]
359 #[inline(always)]
360 pub fn uart0(&mut self) -> UART0_W {
361 UART0_W::new(self)
362 }
363 #[doc = "Bit 16 - Universal Asynchronous Receiver/Transmitter 1 access control bit"]
364 #[inline(always)]
365 pub fn uart1(&mut self) -> UART1_W {
366 UART1_W::new(self)
367 }
368 #[doc = "Bit 17 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit"]
369 #[inline(always)]
370 pub fn usart0(&mut self) -> USART0_W {
371 USART0_W::new(self)
372 }
373 #[doc = "Bit 18 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit"]
374 #[inline(always)]
375 pub fn usart1(&mut self) -> USART1_W {
376 USART1_W::new(self)
377 }
378 #[doc = "Bit 19 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit"]
379 #[inline(always)]
380 pub fn usart2(&mut self) -> USART2_W {
381 USART2_W::new(self)
382 }
383 #[doc = "Bit 20 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit"]
384 #[inline(always)]
385 pub fn usart3(&mut self) -> USART3_W {
386 USART3_W::new(self)
387 }
388 #[doc = "Bit 21 - Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit"]
389 #[inline(always)]
390 pub fn usart4(&mut self) -> USART4_W {
391 USART4_W::new(self)
392 }
393 #[doc = "Bit 22 - Universal Serial Bus Interface access control bit"]
394 #[inline(always)]
395 pub fn usb(&mut self) -> USB_W {
396 USB_W::new(self)
397 }
398 #[doc = "Bit 23 - Watchdog access control bit"]
399 #[inline(always)]
400 pub fn wdog0(&mut self) -> WDOG0_W {
401 WDOG0_W::new(self)
402 }
403 #[doc = "Bit 24 - Watchdog access control bit"]
404 #[inline(always)]
405 pub fn wdog1(&mut self) -> WDOG1_W {
406 WDOG1_W::new(self)
407 }
408 #[doc = "Bit 25 - Wide Timer 0 access control bit"]
409 #[inline(always)]
410 pub fn wtimer0(&mut self) -> WTIMER0_W {
411 WTIMER0_W::new(self)
412 }
413 #[doc = "Bit 26 - Wide Timer 0 access control bit"]
414 #[inline(always)]
415 pub fn wtimer1(&mut self) -> WTIMER1_W {
416 WTIMER1_W::new(self)
417 }
418 #[doc = "Writes raw bits to the register."]
419 #[inline(always)]
420 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
421 self.0.bits(bits);
422 self
423 }
424}
425#[doc = "PPU Privilege Access Type Descriptor 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppupatd1](index.html) module"]
426pub struct PPUPATD1_SPEC;
427impl crate::RegisterSpec for PPUPATD1_SPEC {
428 type Ux = u32;
429}
430#[doc = "`read()` method returns [ppupatd1::R](R) reader structure"]
431impl crate::Readable for PPUPATD1_SPEC {
432 type Reader = R;
433}
434#[doc = "`write(|w| ..)` method takes [ppupatd1::W](W) writer structure"]
435impl crate::Writable for PPUPATD1_SPEC {
436 type Writer = W;
437}
438#[doc = "`reset()` method sets PPUPATD1 to value 0"]
439impl crate::Resettable for PPUPATD1_SPEC {
440 #[inline(always)]
441 fn reset_value() -> Self::Ux {
442 0
443 }
444}