efm32gg12b410_pac/cmu/
hfperclken0.rs

1#[doc = "Register `HFPERCLKEN0` reader"]
2pub struct R(crate::R<HFPERCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFPERCLKEN0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFPERCLKEN0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFPERCLKEN0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFPERCLKEN0` writer"]
17pub struct W(crate::W<HFPERCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFPERCLKEN0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFPERCLKEN0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFPERCLKEN0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
38pub type USART0_R = crate::BitReader<bool>;
39#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
40pub type USART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
42pub type USART1_R = crate::BitReader<bool>;
43#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
44pub type USART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `USART2` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
46pub type USART2_R = crate::BitReader<bool>;
47#[doc = "Field `USART2` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
48pub type USART2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 2>;
49#[doc = "Field `USART3` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
50pub type USART3_R = crate::BitReader<bool>;
51#[doc = "Field `USART3` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
52pub type USART3_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 3>;
53#[doc = "Field `USART4` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable"]
54pub type USART4_R = crate::BitReader<bool>;
55#[doc = "Field `USART4` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable"]
56pub type USART4_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 4>;
57#[doc = "Field `TIMER0` reader - Timer 0 Clock Enable"]
58pub type TIMER0_R = crate::BitReader<bool>;
59#[doc = "Field `TIMER0` writer - Timer 0 Clock Enable"]
60pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 5>;
61#[doc = "Field `TIMER1` reader - Timer 1 Clock Enable"]
62pub type TIMER1_R = crate::BitReader<bool>;
63#[doc = "Field `TIMER1` writer - Timer 1 Clock Enable"]
64pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 6>;
65#[doc = "Field `TIMER2` reader - Timer 2 Clock Enable"]
66pub type TIMER2_R = crate::BitReader<bool>;
67#[doc = "Field `TIMER2` writer - Timer 2 Clock Enable"]
68pub type TIMER2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 7>;
69#[doc = "Field `TIMER3` reader - Timer 3 Clock Enable"]
70pub type TIMER3_R = crate::BitReader<bool>;
71#[doc = "Field `TIMER3` writer - Timer 3 Clock Enable"]
72pub type TIMER3_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 8>;
73#[doc = "Field `ACMP0` reader - Analog Comparator 0 Clock Enable"]
74pub type ACMP0_R = crate::BitReader<bool>;
75#[doc = "Field `ACMP0` writer - Analog Comparator 0 Clock Enable"]
76pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 9>;
77#[doc = "Field `ACMP1` reader - Analog Comparator 1 Clock Enable"]
78pub type ACMP1_R = crate::BitReader<bool>;
79#[doc = "Field `ACMP1` writer - Analog Comparator 1 Clock Enable"]
80pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 10>;
81#[doc = "Field `ACMP2` reader - Analog Comparator 2 Clock Enable"]
82pub type ACMP2_R = crate::BitReader<bool>;
83#[doc = "Field `ACMP2` writer - Analog Comparator 2 Clock Enable"]
84pub type ACMP2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 11>;
85#[doc = "Field `I2C0` reader - I2C 0 Clock Enable"]
86pub type I2C0_R = crate::BitReader<bool>;
87#[doc = "Field `I2C0` writer - I2C 0 Clock Enable"]
88pub type I2C0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 12>;
89#[doc = "Field `I2C1` reader - I2C 1 Clock Enable"]
90pub type I2C1_R = crate::BitReader<bool>;
91#[doc = "Field `I2C1` writer - I2C 1 Clock Enable"]
92pub type I2C1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 13>;
93#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 Clock Enable"]
94pub type ADC0_R = crate::BitReader<bool>;
95#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 Clock Enable"]
96pub type ADC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 14>;
97#[doc = "Field `ADC1` reader - Analog to Digital Converter 0 Clock Enable"]
98pub type ADC1_R = crate::BitReader<bool>;
99#[doc = "Field `ADC1` writer - Analog to Digital Converter 0 Clock Enable"]
100pub type ADC1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 15>;
101#[doc = "Field `PDM` reader - PDM Interface Clock Enable"]
102pub type PDM_R = crate::BitReader<bool>;
103#[doc = "Field `PDM` writer - PDM Interface Clock Enable"]
104pub type PDM_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 16>;
105#[doc = "Field `CRYOTIMER` reader - CRYOTIMER Clock Enable"]
106pub type CRYOTIMER_R = crate::BitReader<bool>;
107#[doc = "Field `CRYOTIMER` writer - CRYOTIMER Clock Enable"]
108pub type CRYOTIMER_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 17>;
109#[doc = "Field `IDAC0` reader - Current Digital to Analog Converter 0 Clock Enable"]
110pub type IDAC0_R = crate::BitReader<bool>;
111#[doc = "Field `IDAC0` writer - Current Digital to Analog Converter 0 Clock Enable"]
112pub type IDAC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 18>;
113#[doc = "Field `TRNG0` reader - True Random Number Generator 0 Clock Enable"]
114pub type TRNG0_R = crate::BitReader<bool>;
115#[doc = "Field `TRNG0` writer - True Random Number Generator 0 Clock Enable"]
116pub type TRNG0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 19>;
117impl R {
118    #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
119    #[inline(always)]
120    pub fn usart0(&self) -> USART0_R {
121        USART0_R::new((self.bits & 1) != 0)
122    }
123    #[doc = "Bit 1 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
124    #[inline(always)]
125    pub fn usart1(&self) -> USART1_R {
126        USART1_R::new(((self.bits >> 1) & 1) != 0)
127    }
128    #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
129    #[inline(always)]
130    pub fn usart2(&self) -> USART2_R {
131        USART2_R::new(((self.bits >> 2) & 1) != 0)
132    }
133    #[doc = "Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
134    #[inline(always)]
135    pub fn usart3(&self) -> USART3_R {
136        USART3_R::new(((self.bits >> 3) & 1) != 0)
137    }
138    #[doc = "Bit 4 - Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable"]
139    #[inline(always)]
140    pub fn usart4(&self) -> USART4_R {
141        USART4_R::new(((self.bits >> 4) & 1) != 0)
142    }
143    #[doc = "Bit 5 - Timer 0 Clock Enable"]
144    #[inline(always)]
145    pub fn timer0(&self) -> TIMER0_R {
146        TIMER0_R::new(((self.bits >> 5) & 1) != 0)
147    }
148    #[doc = "Bit 6 - Timer 1 Clock Enable"]
149    #[inline(always)]
150    pub fn timer1(&self) -> TIMER1_R {
151        TIMER1_R::new(((self.bits >> 6) & 1) != 0)
152    }
153    #[doc = "Bit 7 - Timer 2 Clock Enable"]
154    #[inline(always)]
155    pub fn timer2(&self) -> TIMER2_R {
156        TIMER2_R::new(((self.bits >> 7) & 1) != 0)
157    }
158    #[doc = "Bit 8 - Timer 3 Clock Enable"]
159    #[inline(always)]
160    pub fn timer3(&self) -> TIMER3_R {
161        TIMER3_R::new(((self.bits >> 8) & 1) != 0)
162    }
163    #[doc = "Bit 9 - Analog Comparator 0 Clock Enable"]
164    #[inline(always)]
165    pub fn acmp0(&self) -> ACMP0_R {
166        ACMP0_R::new(((self.bits >> 9) & 1) != 0)
167    }
168    #[doc = "Bit 10 - Analog Comparator 1 Clock Enable"]
169    #[inline(always)]
170    pub fn acmp1(&self) -> ACMP1_R {
171        ACMP1_R::new(((self.bits >> 10) & 1) != 0)
172    }
173    #[doc = "Bit 11 - Analog Comparator 2 Clock Enable"]
174    #[inline(always)]
175    pub fn acmp2(&self) -> ACMP2_R {
176        ACMP2_R::new(((self.bits >> 11) & 1) != 0)
177    }
178    #[doc = "Bit 12 - I2C 0 Clock Enable"]
179    #[inline(always)]
180    pub fn i2c0(&self) -> I2C0_R {
181        I2C0_R::new(((self.bits >> 12) & 1) != 0)
182    }
183    #[doc = "Bit 13 - I2C 1 Clock Enable"]
184    #[inline(always)]
185    pub fn i2c1(&self) -> I2C1_R {
186        I2C1_R::new(((self.bits >> 13) & 1) != 0)
187    }
188    #[doc = "Bit 14 - Analog to Digital Converter 0 Clock Enable"]
189    #[inline(always)]
190    pub fn adc0(&self) -> ADC0_R {
191        ADC0_R::new(((self.bits >> 14) & 1) != 0)
192    }
193    #[doc = "Bit 15 - Analog to Digital Converter 0 Clock Enable"]
194    #[inline(always)]
195    pub fn adc1(&self) -> ADC1_R {
196        ADC1_R::new(((self.bits >> 15) & 1) != 0)
197    }
198    #[doc = "Bit 16 - PDM Interface Clock Enable"]
199    #[inline(always)]
200    pub fn pdm(&self) -> PDM_R {
201        PDM_R::new(((self.bits >> 16) & 1) != 0)
202    }
203    #[doc = "Bit 17 - CRYOTIMER Clock Enable"]
204    #[inline(always)]
205    pub fn cryotimer(&self) -> CRYOTIMER_R {
206        CRYOTIMER_R::new(((self.bits >> 17) & 1) != 0)
207    }
208    #[doc = "Bit 18 - Current Digital to Analog Converter 0 Clock Enable"]
209    #[inline(always)]
210    pub fn idac0(&self) -> IDAC0_R {
211        IDAC0_R::new(((self.bits >> 18) & 1) != 0)
212    }
213    #[doc = "Bit 19 - True Random Number Generator 0 Clock Enable"]
214    #[inline(always)]
215    pub fn trng0(&self) -> TRNG0_R {
216        TRNG0_R::new(((self.bits >> 19) & 1) != 0)
217    }
218}
219impl W {
220    #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
221    #[inline(always)]
222    pub fn usart0(&mut self) -> USART0_W {
223        USART0_W::new(self)
224    }
225    #[doc = "Bit 1 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
226    #[inline(always)]
227    pub fn usart1(&mut self) -> USART1_W {
228        USART1_W::new(self)
229    }
230    #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
231    #[inline(always)]
232    pub fn usart2(&mut self) -> USART2_W {
233        USART2_W::new(self)
234    }
235    #[doc = "Bit 3 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
236    #[inline(always)]
237    pub fn usart3(&mut self) -> USART3_W {
238        USART3_W::new(self)
239    }
240    #[doc = "Bit 4 - Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable"]
241    #[inline(always)]
242    pub fn usart4(&mut self) -> USART4_W {
243        USART4_W::new(self)
244    }
245    #[doc = "Bit 5 - Timer 0 Clock Enable"]
246    #[inline(always)]
247    pub fn timer0(&mut self) -> TIMER0_W {
248        TIMER0_W::new(self)
249    }
250    #[doc = "Bit 6 - Timer 1 Clock Enable"]
251    #[inline(always)]
252    pub fn timer1(&mut self) -> TIMER1_W {
253        TIMER1_W::new(self)
254    }
255    #[doc = "Bit 7 - Timer 2 Clock Enable"]
256    #[inline(always)]
257    pub fn timer2(&mut self) -> TIMER2_W {
258        TIMER2_W::new(self)
259    }
260    #[doc = "Bit 8 - Timer 3 Clock Enable"]
261    #[inline(always)]
262    pub fn timer3(&mut self) -> TIMER3_W {
263        TIMER3_W::new(self)
264    }
265    #[doc = "Bit 9 - Analog Comparator 0 Clock Enable"]
266    #[inline(always)]
267    pub fn acmp0(&mut self) -> ACMP0_W {
268        ACMP0_W::new(self)
269    }
270    #[doc = "Bit 10 - Analog Comparator 1 Clock Enable"]
271    #[inline(always)]
272    pub fn acmp1(&mut self) -> ACMP1_W {
273        ACMP1_W::new(self)
274    }
275    #[doc = "Bit 11 - Analog Comparator 2 Clock Enable"]
276    #[inline(always)]
277    pub fn acmp2(&mut self) -> ACMP2_W {
278        ACMP2_W::new(self)
279    }
280    #[doc = "Bit 12 - I2C 0 Clock Enable"]
281    #[inline(always)]
282    pub fn i2c0(&mut self) -> I2C0_W {
283        I2C0_W::new(self)
284    }
285    #[doc = "Bit 13 - I2C 1 Clock Enable"]
286    #[inline(always)]
287    pub fn i2c1(&mut self) -> I2C1_W {
288        I2C1_W::new(self)
289    }
290    #[doc = "Bit 14 - Analog to Digital Converter 0 Clock Enable"]
291    #[inline(always)]
292    pub fn adc0(&mut self) -> ADC0_W {
293        ADC0_W::new(self)
294    }
295    #[doc = "Bit 15 - Analog to Digital Converter 0 Clock Enable"]
296    #[inline(always)]
297    pub fn adc1(&mut self) -> ADC1_W {
298        ADC1_W::new(self)
299    }
300    #[doc = "Bit 16 - PDM Interface Clock Enable"]
301    #[inline(always)]
302    pub fn pdm(&mut self) -> PDM_W {
303        PDM_W::new(self)
304    }
305    #[doc = "Bit 17 - CRYOTIMER Clock Enable"]
306    #[inline(always)]
307    pub fn cryotimer(&mut self) -> CRYOTIMER_W {
308        CRYOTIMER_W::new(self)
309    }
310    #[doc = "Bit 18 - Current Digital to Analog Converter 0 Clock Enable"]
311    #[inline(always)]
312    pub fn idac0(&mut self) -> IDAC0_W {
313        IDAC0_W::new(self)
314    }
315    #[doc = "Bit 19 - True Random Number Generator 0 Clock Enable"]
316    #[inline(always)]
317    pub fn trng0(&mut self) -> TRNG0_W {
318        TRNG0_W::new(self)
319    }
320    #[doc = "Writes raw bits to the register."]
321    #[inline(always)]
322    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
323        self.0.bits(bits);
324        self
325    }
326}
327#[doc = "High Frequency Peripheral Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken0](index.html) module"]
328pub struct HFPERCLKEN0_SPEC;
329impl crate::RegisterSpec for HFPERCLKEN0_SPEC {
330    type Ux = u32;
331}
332#[doc = "`read()` method returns [hfperclken0::R](R) reader structure"]
333impl crate::Readable for HFPERCLKEN0_SPEC {
334    type Reader = R;
335}
336#[doc = "`write(|w| ..)` method takes [hfperclken0::W](W) writer structure"]
337impl crate::Writable for HFPERCLKEN0_SPEC {
338    type Writer = W;
339}
340#[doc = "`reset()` method sets HFPERCLKEN0 to value 0"]
341impl crate::Resettable for HFPERCLKEN0_SPEC {
342    #[inline(always)]
343    fn reset_value() -> Self::Ux {
344        0
345    }
346}
efm32gg12b410_pac/cmu/hfperclken0.rs

efm32gg12b410_pac/cmu/
hfperclken0.rs
