efm32gg12b390_pac/qspi0/
irqstatus.rs

1#[doc = "Register `IRQSTATUS` reader"]
2pub struct R(crate::R<IRQSTATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IRQSTATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IRQSTATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IRQSTATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IRQSTATUS` writer"]
17pub struct W(crate::W<IRQSTATUS_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IRQSTATUS_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IRQSTATUS_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IRQSTATUS_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MODEMFAIL` reader - Mode M Failure"]
38pub type MODEMFAIL_R = crate::BitReader<bool>;
39#[doc = "Field `MODEMFAIL` writer - Mode M Failure"]
40pub type MODEMFAIL_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 0>;
41#[doc = "Field `UNDERFLOWDET` reader - Underflow Detected"]
42pub type UNDERFLOWDET_R = crate::BitReader<bool>;
43#[doc = "Field `UNDERFLOWDET` writer - Underflow Detected"]
44pub type UNDERFLOWDET_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 1>;
45#[doc = "Field `INDIRECTOPDONE` reader - Indirect Operation Complete"]
46pub type INDIRECTOPDONE_R = crate::BitReader<bool>;
47#[doc = "Field `INDIRECTOPDONE` writer - Indirect Operation Complete"]
48pub type INDIRECTOPDONE_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 2>;
49#[doc = "Field `INDIRECTREADREJECT` reader - Indirect Operation Was Requested but Could Not Be Accepted"]
50pub type INDIRECTREADREJECT_R = crate::BitReader<bool>;
51#[doc = "Field `INDIRECTREADREJECT` writer - Indirect Operation Was Requested but Could Not Be Accepted"]
52pub type INDIRECTREADREJECT_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 3>;
53#[doc = "Field `PROTWRATTEMPT` reader - Write to Protected Area Was Attempted and Rejected"]
54pub type PROTWRATTEMPT_R = crate::BitReader<bool>;
55#[doc = "Field `PROTWRATTEMPT` writer - Write to Protected Area Was Attempted and Rejected"]
56pub type PROTWRATTEMPT_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 4>;
57#[doc = "Field `ILLEGALACCESSDET` reader - Illegal Memory Access Has Been Detected"]
58pub type ILLEGALACCESSDET_R = crate::BitReader<bool>;
59#[doc = "Field `ILLEGALACCESSDET` writer - Illegal Memory Access Has Been Detected"]
60pub type ILLEGALACCESSDET_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 5>;
61#[doc = "Field `INDIRECTXFERLEVELBREACH` reader - Indirect Transfer Watermark Level Breached"]
62pub type INDIRECTXFERLEVELBREACH_R = crate::BitReader<bool>;
63#[doc = "Field `INDIRECTXFERLEVELBREACH` writer - Indirect Transfer Watermark Level Breached"]
64pub type INDIRECTXFERLEVELBREACH_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 6>;
65#[doc = "Field `RECVOVERFLOW` reader - Receive Overflow"]
66pub type RECVOVERFLOW_R = crate::BitReader<bool>;
67#[doc = "Field `RECVOVERFLOW` writer - Receive Overflow"]
68pub type RECVOVERFLOW_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 7>;
69#[doc = "Field `TXFIFONOTFULL` reader - Small TX FIFO Not Full"]
70pub type TXFIFONOTFULL_R = crate::BitReader<bool>;
71#[doc = "Field `TXFIFONOTFULL` writer - Small TX FIFO Not Full"]
72pub type TXFIFONOTFULL_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 8>;
73#[doc = "Field `TXFIFOFULL` reader - Small TX FIFO Full"]
74pub type TXFIFOFULL_R = crate::BitReader<bool>;
75#[doc = "Field `TXFIFOFULL` writer - Small TX FIFO Full"]
76pub type TXFIFOFULL_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 9>;
77#[doc = "Field `RXFIFONOTEMPTY` reader - Small RX FIFO Not Empty"]
78pub type RXFIFONOTEMPTY_R = crate::BitReader<bool>;
79#[doc = "Field `RXFIFONOTEMPTY` writer - Small RX FIFO Not Empty"]
80pub type RXFIFONOTEMPTY_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 10>;
81#[doc = "Field `RXFIFOFULL` reader - Small RX FIFO Full"]
82pub type RXFIFOFULL_R = crate::BitReader<bool>;
83#[doc = "Field `RXFIFOFULL` writer - Small RX FIFO Full"]
84pub type RXFIFOFULL_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 11>;
85#[doc = "Field `INDRDSRAMFULL` reader - Indirect Read Partition Overflow"]
86pub type INDRDSRAMFULL_R = crate::BitReader<bool>;
87#[doc = "Field `INDRDSRAMFULL` writer - Indirect Read Partition Overflow"]
88pub type INDRDSRAMFULL_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 12>;
89#[doc = "Field `POLLEXPINT` reader - The Maximum Number of Programmed Polls Cycles is Expired"]
90pub type POLLEXPINT_R = crate::BitReader<bool>;
91#[doc = "Field `POLLEXPINT` writer - The Maximum Number of Programmed Polls Cycles is Expired"]
92pub type POLLEXPINT_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 13>;
93#[doc = "Field `STIGREQINT` reader - The Controller is Ready for Getting Another STIG Request"]
94pub type STIGREQINT_R = crate::BitReader<bool>;
95#[doc = "Field `STIGREQINT` writer - The Controller is Ready for Getting Another STIG Request"]
96pub type STIGREQINT_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 14>;
97#[doc = "Field `RXCRCDATAERR` reader - RX CRC Data Error"]
98pub type RXCRCDATAERR_R = crate::BitReader<bool>;
99#[doc = "Field `RXCRCDATAERR` writer - RX CRC Data Error"]
100pub type RXCRCDATAERR_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 16>;
101#[doc = "Field `RXCRCDATAVAL` reader - RX CRC Data Valid"]
102pub type RXCRCDATAVAL_R = crate::BitReader<bool>;
103#[doc = "Field `RXCRCDATAVAL` writer - RX CRC Data Valid"]
104pub type RXCRCDATAVAL_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 17>;
105#[doc = "Field `TXCRCCHUNKBRK` reader - TX CRC Chunk Was Broken"]
106pub type TXCRCCHUNKBRK_R = crate::BitReader<bool>;
107#[doc = "Field `TXCRCCHUNKBRK` writer - TX CRC Chunk Was Broken"]
108pub type TXCRCCHUNKBRK_W<'a> = crate::BitWriter<'a, u32, IRQSTATUS_SPEC, bool, 18>;
109impl R {
110    #[doc = "Bit 0 - Mode M Failure"]
111    #[inline(always)]
112    pub fn modemfail(&self) -> MODEMFAIL_R {
113        MODEMFAIL_R::new((self.bits & 1) != 0)
114    }
115    #[doc = "Bit 1 - Underflow Detected"]
116    #[inline(always)]
117    pub fn underflowdet(&self) -> UNDERFLOWDET_R {
118        UNDERFLOWDET_R::new(((self.bits >> 1) & 1) != 0)
119    }
120    #[doc = "Bit 2 - Indirect Operation Complete"]
121    #[inline(always)]
122    pub fn indirectopdone(&self) -> INDIRECTOPDONE_R {
123        INDIRECTOPDONE_R::new(((self.bits >> 2) & 1) != 0)
124    }
125    #[doc = "Bit 3 - Indirect Operation Was Requested but Could Not Be Accepted"]
126    #[inline(always)]
127    pub fn indirectreadreject(&self) -> INDIRECTREADREJECT_R {
128        INDIRECTREADREJECT_R::new(((self.bits >> 3) & 1) != 0)
129    }
130    #[doc = "Bit 4 - Write to Protected Area Was Attempted and Rejected"]
131    #[inline(always)]
132    pub fn protwrattempt(&self) -> PROTWRATTEMPT_R {
133        PROTWRATTEMPT_R::new(((self.bits >> 4) & 1) != 0)
134    }
135    #[doc = "Bit 5 - Illegal Memory Access Has Been Detected"]
136    #[inline(always)]
137    pub fn illegalaccessdet(&self) -> ILLEGALACCESSDET_R {
138        ILLEGALACCESSDET_R::new(((self.bits >> 5) & 1) != 0)
139    }
140    #[doc = "Bit 6 - Indirect Transfer Watermark Level Breached"]
141    #[inline(always)]
142    pub fn indirectxferlevelbreach(&self) -> INDIRECTXFERLEVELBREACH_R {
143        INDIRECTXFERLEVELBREACH_R::new(((self.bits >> 6) & 1) != 0)
144    }
145    #[doc = "Bit 7 - Receive Overflow"]
146    #[inline(always)]
147    pub fn recvoverflow(&self) -> RECVOVERFLOW_R {
148        RECVOVERFLOW_R::new(((self.bits >> 7) & 1) != 0)
149    }
150    #[doc = "Bit 8 - Small TX FIFO Not Full"]
151    #[inline(always)]
152    pub fn txfifonotfull(&self) -> TXFIFONOTFULL_R {
153        TXFIFONOTFULL_R::new(((self.bits >> 8) & 1) != 0)
154    }
155    #[doc = "Bit 9 - Small TX FIFO Full"]
156    #[inline(always)]
157    pub fn txfifofull(&self) -> TXFIFOFULL_R {
158        TXFIFOFULL_R::new(((self.bits >> 9) & 1) != 0)
159    }
160    #[doc = "Bit 10 - Small RX FIFO Not Empty"]
161    #[inline(always)]
162    pub fn rxfifonotempty(&self) -> RXFIFONOTEMPTY_R {
163        RXFIFONOTEMPTY_R::new(((self.bits >> 10) & 1) != 0)
164    }
165    #[doc = "Bit 11 - Small RX FIFO Full"]
166    #[inline(always)]
167    pub fn rxfifofull(&self) -> RXFIFOFULL_R {
168        RXFIFOFULL_R::new(((self.bits >> 11) & 1) != 0)
169    }
170    #[doc = "Bit 12 - Indirect Read Partition Overflow"]
171    #[inline(always)]
172    pub fn indrdsramfull(&self) -> INDRDSRAMFULL_R {
173        INDRDSRAMFULL_R::new(((self.bits >> 12) & 1) != 0)
174    }
175    #[doc = "Bit 13 - The Maximum Number of Programmed Polls Cycles is Expired"]
176    #[inline(always)]
177    pub fn pollexpint(&self) -> POLLEXPINT_R {
178        POLLEXPINT_R::new(((self.bits >> 13) & 1) != 0)
179    }
180    #[doc = "Bit 14 - The Controller is Ready for Getting Another STIG Request"]
181    #[inline(always)]
182    pub fn stigreqint(&self) -> STIGREQINT_R {
183        STIGREQINT_R::new(((self.bits >> 14) & 1) != 0)
184    }
185    #[doc = "Bit 16 - RX CRC Data Error"]
186    #[inline(always)]
187    pub fn rxcrcdataerr(&self) -> RXCRCDATAERR_R {
188        RXCRCDATAERR_R::new(((self.bits >> 16) & 1) != 0)
189    }
190    #[doc = "Bit 17 - RX CRC Data Valid"]
191    #[inline(always)]
192    pub fn rxcrcdataval(&self) -> RXCRCDATAVAL_R {
193        RXCRCDATAVAL_R::new(((self.bits >> 17) & 1) != 0)
194    }
195    #[doc = "Bit 18 - TX CRC Chunk Was Broken"]
196    #[inline(always)]
197    pub fn txcrcchunkbrk(&self) -> TXCRCCHUNKBRK_R {
198        TXCRCCHUNKBRK_R::new(((self.bits >> 18) & 1) != 0)
199    }
200}
201impl W {
202    #[doc = "Bit 0 - Mode M Failure"]
203    #[inline(always)]
204    pub fn modemfail(&mut self) -> MODEMFAIL_W {
205        MODEMFAIL_W::new(self)
206    }
207    #[doc = "Bit 1 - Underflow Detected"]
208    #[inline(always)]
209    pub fn underflowdet(&mut self) -> UNDERFLOWDET_W {
210        UNDERFLOWDET_W::new(self)
211    }
212    #[doc = "Bit 2 - Indirect Operation Complete"]
213    #[inline(always)]
214    pub fn indirectopdone(&mut self) -> INDIRECTOPDONE_W {
215        INDIRECTOPDONE_W::new(self)
216    }
217    #[doc = "Bit 3 - Indirect Operation Was Requested but Could Not Be Accepted"]
218    #[inline(always)]
219    pub fn indirectreadreject(&mut self) -> INDIRECTREADREJECT_W {
220        INDIRECTREADREJECT_W::new(self)
221    }
222    #[doc = "Bit 4 - Write to Protected Area Was Attempted and Rejected"]
223    #[inline(always)]
224    pub fn protwrattempt(&mut self) -> PROTWRATTEMPT_W {
225        PROTWRATTEMPT_W::new(self)
226    }
227    #[doc = "Bit 5 - Illegal Memory Access Has Been Detected"]
228    #[inline(always)]
229    pub fn illegalaccessdet(&mut self) -> ILLEGALACCESSDET_W {
230        ILLEGALACCESSDET_W::new(self)
231    }
232    #[doc = "Bit 6 - Indirect Transfer Watermark Level Breached"]
233    #[inline(always)]
234    pub fn indirectxferlevelbreach(&mut self) -> INDIRECTXFERLEVELBREACH_W {
235        INDIRECTXFERLEVELBREACH_W::new(self)
236    }
237    #[doc = "Bit 7 - Receive Overflow"]
238    #[inline(always)]
239    pub fn recvoverflow(&mut self) -> RECVOVERFLOW_W {
240        RECVOVERFLOW_W::new(self)
241    }
242    #[doc = "Bit 8 - Small TX FIFO Not Full"]
243    #[inline(always)]
244    pub fn txfifonotfull(&mut self) -> TXFIFONOTFULL_W {
245        TXFIFONOTFULL_W::new(self)
246    }
247    #[doc = "Bit 9 - Small TX FIFO Full"]
248    #[inline(always)]
249    pub fn txfifofull(&mut self) -> TXFIFOFULL_W {
250        TXFIFOFULL_W::new(self)
251    }
252    #[doc = "Bit 10 - Small RX FIFO Not Empty"]
253    #[inline(always)]
254    pub fn rxfifonotempty(&mut self) -> RXFIFONOTEMPTY_W {
255        RXFIFONOTEMPTY_W::new(self)
256    }
257    #[doc = "Bit 11 - Small RX FIFO Full"]
258    #[inline(always)]
259    pub fn rxfifofull(&mut self) -> RXFIFOFULL_W {
260        RXFIFOFULL_W::new(self)
261    }
262    #[doc = "Bit 12 - Indirect Read Partition Overflow"]
263    #[inline(always)]
264    pub fn indrdsramfull(&mut self) -> INDRDSRAMFULL_W {
265        INDRDSRAMFULL_W::new(self)
266    }
267    #[doc = "Bit 13 - The Maximum Number of Programmed Polls Cycles is Expired"]
268    #[inline(always)]
269    pub fn pollexpint(&mut self) -> POLLEXPINT_W {
270        POLLEXPINT_W::new(self)
271    }
272    #[doc = "Bit 14 - The Controller is Ready for Getting Another STIG Request"]
273    #[inline(always)]
274    pub fn stigreqint(&mut self) -> STIGREQINT_W {
275        STIGREQINT_W::new(self)
276    }
277    #[doc = "Bit 16 - RX CRC Data Error"]
278    #[inline(always)]
279    pub fn rxcrcdataerr(&mut self) -> RXCRCDATAERR_W {
280        RXCRCDATAERR_W::new(self)
281    }
282    #[doc = "Bit 17 - RX CRC Data Valid"]
283    #[inline(always)]
284    pub fn rxcrcdataval(&mut self) -> RXCRCDATAVAL_W {
285        RXCRCDATAVAL_W::new(self)
286    }
287    #[doc = "Bit 18 - TX CRC Chunk Was Broken"]
288    #[inline(always)]
289    pub fn txcrcchunkbrk(&mut self) -> TXCRCCHUNKBRK_W {
290        TXCRCCHUNKBRK_W::new(self)
291    }
292    #[doc = "Writes raw bits to the register."]
293    #[inline(always)]
294    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
295        self.0.bits(bits);
296        self
297    }
298}
299#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irqstatus](index.html) module"]
300pub struct IRQSTATUS_SPEC;
301impl crate::RegisterSpec for IRQSTATUS_SPEC {
302    type Ux = u32;
303}
304#[doc = "`read()` method returns [irqstatus::R](R) reader structure"]
305impl crate::Readable for IRQSTATUS_SPEC {
306    type Reader = R;
307}
308#[doc = "`write(|w| ..)` method takes [irqstatus::W](W) writer structure"]
309impl crate::Writable for IRQSTATUS_SPEC {
310    type Writer = W;
311}
312#[doc = "`reset()` method sets IRQSTATUS to value 0"]
313impl crate::Resettable for IRQSTATUS_SPEC {
314    #[inline(always)]
315    fn reset_value() -> Self::Ux {
316        0
317    }
318}
efm32gg12b390_pac/qspi0/irqstatus.rs

efm32gg12b390_pac/qspi0/
irqstatus.rs
