1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Mode\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum MODE_A {
41 #[doc = "0: EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled."]
42 D8A8 = 0,
43 #[doc = "1: EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled."]
44 D16A16ALE = 1,
45 #[doc = "2: EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled."]
46 D8A24ALE = 2,
47 #[doc = "3: EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled."]
48 D16 = 3,
49}
50impl From<MODE_A> for u8 {
51 #[inline(always)]
52 fn from(variant: MODE_A) -> Self {
53 variant as _
54 }
55}
56#[doc = "Field `MODE` reader - Mode"]
57pub type MODE_R = crate::FieldReader<u8, MODE_A>;
58impl MODE_R {
59 #[doc = "Get enumerated values variant"]
60 #[inline(always)]
61 pub fn variant(&self) -> MODE_A {
62 match self.bits {
63 0 => MODE_A::D8A8,
64 1 => MODE_A::D16A16ALE,
65 2 => MODE_A::D8A24ALE,
66 3 => MODE_A::D16,
67 _ => unreachable!(),
68 }
69 }
70 #[doc = "Checks if the value of the field is `D8A8`"]
71 #[inline(always)]
72 pub fn is_d8a8(&self) -> bool {
73 *self == MODE_A::D8A8
74 }
75 #[doc = "Checks if the value of the field is `D16A16ALE`"]
76 #[inline(always)]
77 pub fn is_d16a16ale(&self) -> bool {
78 *self == MODE_A::D16A16ALE
79 }
80 #[doc = "Checks if the value of the field is `D8A24ALE`"]
81 #[inline(always)]
82 pub fn is_d8a24ale(&self) -> bool {
83 *self == MODE_A::D8A24ALE
84 }
85 #[doc = "Checks if the value of the field is `D16`"]
86 #[inline(always)]
87 pub fn is_d16(&self) -> bool {
88 *self == MODE_A::D16
89 }
90}
91#[doc = "Field `MODE` writer - Mode"]
92pub type MODE_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, MODE_A, 2, 0>;
93impl<'a> MODE_W<'a> {
94 #[doc = "EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled."]
95 #[inline(always)]
96 pub fn d8a8(self) -> &'a mut W {
97 self.variant(MODE_A::D8A8)
98 }
99 #[doc = "EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled."]
100 #[inline(always)]
101 pub fn d16a16ale(self) -> &'a mut W {
102 self.variant(MODE_A::D16A16ALE)
103 }
104 #[doc = "EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled."]
105 #[inline(always)]
106 pub fn d8a24ale(self) -> &'a mut W {
107 self.variant(MODE_A::D8A24ALE)
108 }
109 #[doc = "EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled."]
110 #[inline(always)]
111 pub fn d16(self) -> &'a mut W {
112 self.variant(MODE_A::D16)
113 }
114}
115#[doc = "Mode 1\n\nValue on reset: 0"]
116#[derive(Clone, Copy, Debug, PartialEq)]
117#[repr(u8)]
118pub enum MODE1_A {
119 #[doc = "0: EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled."]
120 D8A8 = 0,
121 #[doc = "1: EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled."]
122 D16A16ALE = 1,
123 #[doc = "2: EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled."]
124 D8A24ALE = 2,
125 #[doc = "3: EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled."]
126 D16 = 3,
127}
128impl From<MODE1_A> for u8 {
129 #[inline(always)]
130 fn from(variant: MODE1_A) -> Self {
131 variant as _
132 }
133}
134#[doc = "Field `MODE1` reader - Mode 1"]
135pub type MODE1_R = crate::FieldReader<u8, MODE1_A>;
136impl MODE1_R {
137 #[doc = "Get enumerated values variant"]
138 #[inline(always)]
139 pub fn variant(&self) -> MODE1_A {
140 match self.bits {
141 0 => MODE1_A::D8A8,
142 1 => MODE1_A::D16A16ALE,
143 2 => MODE1_A::D8A24ALE,
144 3 => MODE1_A::D16,
145 _ => unreachable!(),
146 }
147 }
148 #[doc = "Checks if the value of the field is `D8A8`"]
149 #[inline(always)]
150 pub fn is_d8a8(&self) -> bool {
151 *self == MODE1_A::D8A8
152 }
153 #[doc = "Checks if the value of the field is `D16A16ALE`"]
154 #[inline(always)]
155 pub fn is_d16a16ale(&self) -> bool {
156 *self == MODE1_A::D16A16ALE
157 }
158 #[doc = "Checks if the value of the field is `D8A24ALE`"]
159 #[inline(always)]
160 pub fn is_d8a24ale(&self) -> bool {
161 *self == MODE1_A::D8A24ALE
162 }
163 #[doc = "Checks if the value of the field is `D16`"]
164 #[inline(always)]
165 pub fn is_d16(&self) -> bool {
166 *self == MODE1_A::D16
167 }
168}
169#[doc = "Field `MODE1` writer - Mode 1"]
170pub type MODE1_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, MODE1_A, 2, 2>;
171impl<'a> MODE1_W<'a> {
172 #[doc = "EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled."]
173 #[inline(always)]
174 pub fn d8a8(self) -> &'a mut W {
175 self.variant(MODE1_A::D8A8)
176 }
177 #[doc = "EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled."]
178 #[inline(always)]
179 pub fn d16a16ale(self) -> &'a mut W {
180 self.variant(MODE1_A::D16A16ALE)
181 }
182 #[doc = "EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled."]
183 #[inline(always)]
184 pub fn d8a24ale(self) -> &'a mut W {
185 self.variant(MODE1_A::D8A24ALE)
186 }
187 #[doc = "EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled."]
188 #[inline(always)]
189 pub fn d16(self) -> &'a mut W {
190 self.variant(MODE1_A::D16)
191 }
192}
193#[doc = "Mode 2\n\nValue on reset: 0"]
194#[derive(Clone, Copy, Debug, PartialEq)]
195#[repr(u8)]
196pub enum MODE2_A {
197 #[doc = "0: EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled."]
198 D8A8 = 0,
199 #[doc = "1: EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled."]
200 D16A16ALE = 1,
201 #[doc = "2: EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled."]
202 D8A24ALE = 2,
203 #[doc = "3: EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled."]
204 D16 = 3,
205}
206impl From<MODE2_A> for u8 {
207 #[inline(always)]
208 fn from(variant: MODE2_A) -> Self {
209 variant as _
210 }
211}
212#[doc = "Field `MODE2` reader - Mode 2"]
213pub type MODE2_R = crate::FieldReader<u8, MODE2_A>;
214impl MODE2_R {
215 #[doc = "Get enumerated values variant"]
216 #[inline(always)]
217 pub fn variant(&self) -> MODE2_A {
218 match self.bits {
219 0 => MODE2_A::D8A8,
220 1 => MODE2_A::D16A16ALE,
221 2 => MODE2_A::D8A24ALE,
222 3 => MODE2_A::D16,
223 _ => unreachable!(),
224 }
225 }
226 #[doc = "Checks if the value of the field is `D8A8`"]
227 #[inline(always)]
228 pub fn is_d8a8(&self) -> bool {
229 *self == MODE2_A::D8A8
230 }
231 #[doc = "Checks if the value of the field is `D16A16ALE`"]
232 #[inline(always)]
233 pub fn is_d16a16ale(&self) -> bool {
234 *self == MODE2_A::D16A16ALE
235 }
236 #[doc = "Checks if the value of the field is `D8A24ALE`"]
237 #[inline(always)]
238 pub fn is_d8a24ale(&self) -> bool {
239 *self == MODE2_A::D8A24ALE
240 }
241 #[doc = "Checks if the value of the field is `D16`"]
242 #[inline(always)]
243 pub fn is_d16(&self) -> bool {
244 *self == MODE2_A::D16
245 }
246}
247#[doc = "Field `MODE2` writer - Mode 2"]
248pub type MODE2_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, MODE2_A, 2, 4>;
249impl<'a> MODE2_W<'a> {
250 #[doc = "EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled."]
251 #[inline(always)]
252 pub fn d8a8(self) -> &'a mut W {
253 self.variant(MODE2_A::D8A8)
254 }
255 #[doc = "EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled."]
256 #[inline(always)]
257 pub fn d16a16ale(self) -> &'a mut W {
258 self.variant(MODE2_A::D16A16ALE)
259 }
260 #[doc = "EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled."]
261 #[inline(always)]
262 pub fn d8a24ale(self) -> &'a mut W {
263 self.variant(MODE2_A::D8A24ALE)
264 }
265 #[doc = "EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled."]
266 #[inline(always)]
267 pub fn d16(self) -> &'a mut W {
268 self.variant(MODE2_A::D16)
269 }
270}
271#[doc = "Mode 3\n\nValue on reset: 0"]
272#[derive(Clone, Copy, Debug, PartialEq)]
273#[repr(u8)]
274pub enum MODE3_A {
275 #[doc = "0: EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled."]
276 D8A8 = 0,
277 #[doc = "1: EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled."]
278 D16A16ALE = 1,
279 #[doc = "2: EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled."]
280 D8A24ALE = 2,
281 #[doc = "3: EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled."]
282 D16 = 3,
283}
284impl From<MODE3_A> for u8 {
285 #[inline(always)]
286 fn from(variant: MODE3_A) -> Self {
287 variant as _
288 }
289}
290#[doc = "Field `MODE3` reader - Mode 3"]
291pub type MODE3_R = crate::FieldReader<u8, MODE3_A>;
292impl MODE3_R {
293 #[doc = "Get enumerated values variant"]
294 #[inline(always)]
295 pub fn variant(&self) -> MODE3_A {
296 match self.bits {
297 0 => MODE3_A::D8A8,
298 1 => MODE3_A::D16A16ALE,
299 2 => MODE3_A::D8A24ALE,
300 3 => MODE3_A::D16,
301 _ => unreachable!(),
302 }
303 }
304 #[doc = "Checks if the value of the field is `D8A8`"]
305 #[inline(always)]
306 pub fn is_d8a8(&self) -> bool {
307 *self == MODE3_A::D8A8
308 }
309 #[doc = "Checks if the value of the field is `D16A16ALE`"]
310 #[inline(always)]
311 pub fn is_d16a16ale(&self) -> bool {
312 *self == MODE3_A::D16A16ALE
313 }
314 #[doc = "Checks if the value of the field is `D8A24ALE`"]
315 #[inline(always)]
316 pub fn is_d8a24ale(&self) -> bool {
317 *self == MODE3_A::D8A24ALE
318 }
319 #[doc = "Checks if the value of the field is `D16`"]
320 #[inline(always)]
321 pub fn is_d16(&self) -> bool {
322 *self == MODE3_A::D16
323 }
324}
325#[doc = "Field `MODE3` writer - Mode 3"]
326pub type MODE3_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, MODE3_A, 2, 6>;
327impl<'a> MODE3_W<'a> {
328 #[doc = "EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled."]
329 #[inline(always)]
330 pub fn d8a8(self) -> &'a mut W {
331 self.variant(MODE3_A::D8A8)
332 }
333 #[doc = "EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled."]
334 #[inline(always)]
335 pub fn d16a16ale(self) -> &'a mut W {
336 self.variant(MODE3_A::D16A16ALE)
337 }
338 #[doc = "EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled."]
339 #[inline(always)]
340 pub fn d8a24ale(self) -> &'a mut W {
341 self.variant(MODE3_A::D8A24ALE)
342 }
343 #[doc = "EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled."]
344 #[inline(always)]
345 pub fn d16(self) -> &'a mut W {
346 self.variant(MODE3_A::D16)
347 }
348}
349#[doc = "Field `BANK0EN` reader - Bank 0 Enable"]
350pub type BANK0EN_R = crate::BitReader<bool>;
351#[doc = "Field `BANK0EN` writer - Bank 0 Enable"]
352pub type BANK0EN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 8>;
353#[doc = "Field `BANK1EN` reader - Bank 1 Enable"]
354pub type BANK1EN_R = crate::BitReader<bool>;
355#[doc = "Field `BANK1EN` writer - Bank 1 Enable"]
356pub type BANK1EN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 9>;
357#[doc = "Field `BANK2EN` reader - Bank 2 Enable"]
358pub type BANK2EN_R = crate::BitReader<bool>;
359#[doc = "Field `BANK2EN` writer - Bank 2 Enable"]
360pub type BANK2EN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 10>;
361#[doc = "Field `BANK3EN` reader - Bank 3 Enable"]
362pub type BANK3EN_R = crate::BitReader<bool>;
363#[doc = "Field `BANK3EN` writer - Bank 3 Enable"]
364pub type BANK3EN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 11>;
365#[doc = "Field `NOIDLE` reader - No Idle Cycle Insertion on Bank 0"]
366pub type NOIDLE_R = crate::BitReader<bool>;
367#[doc = "Field `NOIDLE` writer - No Idle Cycle Insertion on Bank 0"]
368pub type NOIDLE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 12>;
369#[doc = "Field `NOIDLE1` reader - No Idle Cycle Insertion on Bank 1"]
370pub type NOIDLE1_R = crate::BitReader<bool>;
371#[doc = "Field `NOIDLE1` writer - No Idle Cycle Insertion on Bank 1"]
372pub type NOIDLE1_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 13>;
373#[doc = "Field `NOIDLE2` reader - No Idle Cycle Insertion on Bank 2"]
374pub type NOIDLE2_R = crate::BitReader<bool>;
375#[doc = "Field `NOIDLE2` writer - No Idle Cycle Insertion on Bank 2"]
376pub type NOIDLE2_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 14>;
377#[doc = "Field `NOIDLE3` reader - No Idle Cycle Insertion on Bank 3"]
378pub type NOIDLE3_R = crate::BitReader<bool>;
379#[doc = "Field `NOIDLE3` writer - No Idle Cycle Insertion on Bank 3"]
380pub type NOIDLE3_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 15>;
381#[doc = "Field `ARDYEN` reader - ARDY Enable"]
382pub type ARDYEN_R = crate::BitReader<bool>;
383#[doc = "Field `ARDYEN` writer - ARDY Enable"]
384pub type ARDYEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 16>;
385#[doc = "Field `ARDYTODIS` reader - ARDY Timeout Disable"]
386pub type ARDYTODIS_R = crate::BitReader<bool>;
387#[doc = "Field `ARDYTODIS` writer - ARDY Timeout Disable"]
388pub type ARDYTODIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 17>;
389#[doc = "Field `ARDY1EN` reader - ARDY Enable for Bank 1"]
390pub type ARDY1EN_R = crate::BitReader<bool>;
391#[doc = "Field `ARDY1EN` writer - ARDY Enable for Bank 1"]
392pub type ARDY1EN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 18>;
393#[doc = "Field `ARDYTO1DIS` reader - ARDY Timeout Disable for Bank 1"]
394pub type ARDYTO1DIS_R = crate::BitReader<bool>;
395#[doc = "Field `ARDYTO1DIS` writer - ARDY Timeout Disable for Bank 1"]
396pub type ARDYTO1DIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 19>;
397#[doc = "Field `ARDY2EN` reader - ARDY Enable for Bank 2"]
398pub type ARDY2EN_R = crate::BitReader<bool>;
399#[doc = "Field `ARDY2EN` writer - ARDY Enable for Bank 2"]
400pub type ARDY2EN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 20>;
401#[doc = "Field `ARDYTO2DIS` reader - ARDY Timeout Disable for Bank 2"]
402pub type ARDYTO2DIS_R = crate::BitReader<bool>;
403#[doc = "Field `ARDYTO2DIS` writer - ARDY Timeout Disable for Bank 2"]
404pub type ARDYTO2DIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 21>;
405#[doc = "Field `ARDY3EN` reader - ARDY Enable for Bank 3"]
406pub type ARDY3EN_R = crate::BitReader<bool>;
407#[doc = "Field `ARDY3EN` writer - ARDY Enable for Bank 3"]
408pub type ARDY3EN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 22>;
409#[doc = "Field `ARDYTO3DIS` reader - ARDY Timeout Disable for Bank 3"]
410pub type ARDYTO3DIS_R = crate::BitReader<bool>;
411#[doc = "Field `ARDYTO3DIS` writer - ARDY Timeout Disable for Bank 3"]
412pub type ARDYTO3DIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 23>;
413#[doc = "Field `BL` reader - Byte Lane Enable for Bank 0"]
414pub type BL_R = crate::BitReader<bool>;
415#[doc = "Field `BL` writer - Byte Lane Enable for Bank 0"]
416pub type BL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 24>;
417#[doc = "Field `BL1` reader - Byte Lane Enable for Bank 1"]
418pub type BL1_R = crate::BitReader<bool>;
419#[doc = "Field `BL1` writer - Byte Lane Enable for Bank 1"]
420pub type BL1_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 25>;
421#[doc = "Field `BL2` reader - Byte Lane Enable for Bank 2"]
422pub type BL2_R = crate::BitReader<bool>;
423#[doc = "Field `BL2` writer - Byte Lane Enable for Bank 2"]
424pub type BL2_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 26>;
425#[doc = "Field `BL3` reader - Byte Lane Enable for Bank 3"]
426pub type BL3_R = crate::BitReader<bool>;
427#[doc = "Field `BL3` writer - Byte Lane Enable for Bank 3"]
428pub type BL3_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 27>;
429#[doc = "Field `ITS` reader - Individual Timing Set, Line Polarity and Mode Definition Enable"]
430pub type ITS_R = crate::BitReader<bool>;
431#[doc = "Field `ITS` writer - Individual Timing Set, Line Polarity and Mode Definition Enable"]
432pub type ITS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 30>;
433#[doc = "Field `ALTMAP` reader - Alternative Address Map Enable"]
434pub type ALTMAP_R = crate::BitReader<bool>;
435#[doc = "Field `ALTMAP` writer - Alternative Address Map Enable"]
436pub type ALTMAP_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 31>;
437impl R {
438 #[doc = "Bits 0:1 - Mode"]
439 #[inline(always)]
440 pub fn mode(&self) -> MODE_R {
441 MODE_R::new((self.bits & 3) as u8)
442 }
443 #[doc = "Bits 2:3 - Mode 1"]
444 #[inline(always)]
445 pub fn mode1(&self) -> MODE1_R {
446 MODE1_R::new(((self.bits >> 2) & 3) as u8)
447 }
448 #[doc = "Bits 4:5 - Mode 2"]
449 #[inline(always)]
450 pub fn mode2(&self) -> MODE2_R {
451 MODE2_R::new(((self.bits >> 4) & 3) as u8)
452 }
453 #[doc = "Bits 6:7 - Mode 3"]
454 #[inline(always)]
455 pub fn mode3(&self) -> MODE3_R {
456 MODE3_R::new(((self.bits >> 6) & 3) as u8)
457 }
458 #[doc = "Bit 8 - Bank 0 Enable"]
459 #[inline(always)]
460 pub fn bank0en(&self) -> BANK0EN_R {
461 BANK0EN_R::new(((self.bits >> 8) & 1) != 0)
462 }
463 #[doc = "Bit 9 - Bank 1 Enable"]
464 #[inline(always)]
465 pub fn bank1en(&self) -> BANK1EN_R {
466 BANK1EN_R::new(((self.bits >> 9) & 1) != 0)
467 }
468 #[doc = "Bit 10 - Bank 2 Enable"]
469 #[inline(always)]
470 pub fn bank2en(&self) -> BANK2EN_R {
471 BANK2EN_R::new(((self.bits >> 10) & 1) != 0)
472 }
473 #[doc = "Bit 11 - Bank 3 Enable"]
474 #[inline(always)]
475 pub fn bank3en(&self) -> BANK3EN_R {
476 BANK3EN_R::new(((self.bits >> 11) & 1) != 0)
477 }
478 #[doc = "Bit 12 - No Idle Cycle Insertion on Bank 0"]
479 #[inline(always)]
480 pub fn noidle(&self) -> NOIDLE_R {
481 NOIDLE_R::new(((self.bits >> 12) & 1) != 0)
482 }
483 #[doc = "Bit 13 - No Idle Cycle Insertion on Bank 1"]
484 #[inline(always)]
485 pub fn noidle1(&self) -> NOIDLE1_R {
486 NOIDLE1_R::new(((self.bits >> 13) & 1) != 0)
487 }
488 #[doc = "Bit 14 - No Idle Cycle Insertion on Bank 2"]
489 #[inline(always)]
490 pub fn noidle2(&self) -> NOIDLE2_R {
491 NOIDLE2_R::new(((self.bits >> 14) & 1) != 0)
492 }
493 #[doc = "Bit 15 - No Idle Cycle Insertion on Bank 3"]
494 #[inline(always)]
495 pub fn noidle3(&self) -> NOIDLE3_R {
496 NOIDLE3_R::new(((self.bits >> 15) & 1) != 0)
497 }
498 #[doc = "Bit 16 - ARDY Enable"]
499 #[inline(always)]
500 pub fn ardyen(&self) -> ARDYEN_R {
501 ARDYEN_R::new(((self.bits >> 16) & 1) != 0)
502 }
503 #[doc = "Bit 17 - ARDY Timeout Disable"]
504 #[inline(always)]
505 pub fn ardytodis(&self) -> ARDYTODIS_R {
506 ARDYTODIS_R::new(((self.bits >> 17) & 1) != 0)
507 }
508 #[doc = "Bit 18 - ARDY Enable for Bank 1"]
509 #[inline(always)]
510 pub fn ardy1en(&self) -> ARDY1EN_R {
511 ARDY1EN_R::new(((self.bits >> 18) & 1) != 0)
512 }
513 #[doc = "Bit 19 - ARDY Timeout Disable for Bank 1"]
514 #[inline(always)]
515 pub fn ardyto1dis(&self) -> ARDYTO1DIS_R {
516 ARDYTO1DIS_R::new(((self.bits >> 19) & 1) != 0)
517 }
518 #[doc = "Bit 20 - ARDY Enable for Bank 2"]
519 #[inline(always)]
520 pub fn ardy2en(&self) -> ARDY2EN_R {
521 ARDY2EN_R::new(((self.bits >> 20) & 1) != 0)
522 }
523 #[doc = "Bit 21 - ARDY Timeout Disable for Bank 2"]
524 #[inline(always)]
525 pub fn ardyto2dis(&self) -> ARDYTO2DIS_R {
526 ARDYTO2DIS_R::new(((self.bits >> 21) & 1) != 0)
527 }
528 #[doc = "Bit 22 - ARDY Enable for Bank 3"]
529 #[inline(always)]
530 pub fn ardy3en(&self) -> ARDY3EN_R {
531 ARDY3EN_R::new(((self.bits >> 22) & 1) != 0)
532 }
533 #[doc = "Bit 23 - ARDY Timeout Disable for Bank 3"]
534 #[inline(always)]
535 pub fn ardyto3dis(&self) -> ARDYTO3DIS_R {
536 ARDYTO3DIS_R::new(((self.bits >> 23) & 1) != 0)
537 }
538 #[doc = "Bit 24 - Byte Lane Enable for Bank 0"]
539 #[inline(always)]
540 pub fn bl(&self) -> BL_R {
541 BL_R::new(((self.bits >> 24) & 1) != 0)
542 }
543 #[doc = "Bit 25 - Byte Lane Enable for Bank 1"]
544 #[inline(always)]
545 pub fn bl1(&self) -> BL1_R {
546 BL1_R::new(((self.bits >> 25) & 1) != 0)
547 }
548 #[doc = "Bit 26 - Byte Lane Enable for Bank 2"]
549 #[inline(always)]
550 pub fn bl2(&self) -> BL2_R {
551 BL2_R::new(((self.bits >> 26) & 1) != 0)
552 }
553 #[doc = "Bit 27 - Byte Lane Enable for Bank 3"]
554 #[inline(always)]
555 pub fn bl3(&self) -> BL3_R {
556 BL3_R::new(((self.bits >> 27) & 1) != 0)
557 }
558 #[doc = "Bit 30 - Individual Timing Set, Line Polarity and Mode Definition Enable"]
559 #[inline(always)]
560 pub fn its(&self) -> ITS_R {
561 ITS_R::new(((self.bits >> 30) & 1) != 0)
562 }
563 #[doc = "Bit 31 - Alternative Address Map Enable"]
564 #[inline(always)]
565 pub fn altmap(&self) -> ALTMAP_R {
566 ALTMAP_R::new(((self.bits >> 31) & 1) != 0)
567 }
568}
569impl W {
570 #[doc = "Bits 0:1 - Mode"]
571 #[inline(always)]
572 pub fn mode(&mut self) -> MODE_W {
573 MODE_W::new(self)
574 }
575 #[doc = "Bits 2:3 - Mode 1"]
576 #[inline(always)]
577 pub fn mode1(&mut self) -> MODE1_W {
578 MODE1_W::new(self)
579 }
580 #[doc = "Bits 4:5 - Mode 2"]
581 #[inline(always)]
582 pub fn mode2(&mut self) -> MODE2_W {
583 MODE2_W::new(self)
584 }
585 #[doc = "Bits 6:7 - Mode 3"]
586 #[inline(always)]
587 pub fn mode3(&mut self) -> MODE3_W {
588 MODE3_W::new(self)
589 }
590 #[doc = "Bit 8 - Bank 0 Enable"]
591 #[inline(always)]
592 pub fn bank0en(&mut self) -> BANK0EN_W {
593 BANK0EN_W::new(self)
594 }
595 #[doc = "Bit 9 - Bank 1 Enable"]
596 #[inline(always)]
597 pub fn bank1en(&mut self) -> BANK1EN_W {
598 BANK1EN_W::new(self)
599 }
600 #[doc = "Bit 10 - Bank 2 Enable"]
601 #[inline(always)]
602 pub fn bank2en(&mut self) -> BANK2EN_W {
603 BANK2EN_W::new(self)
604 }
605 #[doc = "Bit 11 - Bank 3 Enable"]
606 #[inline(always)]
607 pub fn bank3en(&mut self) -> BANK3EN_W {
608 BANK3EN_W::new(self)
609 }
610 #[doc = "Bit 12 - No Idle Cycle Insertion on Bank 0"]
611 #[inline(always)]
612 pub fn noidle(&mut self) -> NOIDLE_W {
613 NOIDLE_W::new(self)
614 }
615 #[doc = "Bit 13 - No Idle Cycle Insertion on Bank 1"]
616 #[inline(always)]
617 pub fn noidle1(&mut self) -> NOIDLE1_W {
618 NOIDLE1_W::new(self)
619 }
620 #[doc = "Bit 14 - No Idle Cycle Insertion on Bank 2"]
621 #[inline(always)]
622 pub fn noidle2(&mut self) -> NOIDLE2_W {
623 NOIDLE2_W::new(self)
624 }
625 #[doc = "Bit 15 - No Idle Cycle Insertion on Bank 3"]
626 #[inline(always)]
627 pub fn noidle3(&mut self) -> NOIDLE3_W {
628 NOIDLE3_W::new(self)
629 }
630 #[doc = "Bit 16 - ARDY Enable"]
631 #[inline(always)]
632 pub fn ardyen(&mut self) -> ARDYEN_W {
633 ARDYEN_W::new(self)
634 }
635 #[doc = "Bit 17 - ARDY Timeout Disable"]
636 #[inline(always)]
637 pub fn ardytodis(&mut self) -> ARDYTODIS_W {
638 ARDYTODIS_W::new(self)
639 }
640 #[doc = "Bit 18 - ARDY Enable for Bank 1"]
641 #[inline(always)]
642 pub fn ardy1en(&mut self) -> ARDY1EN_W {
643 ARDY1EN_W::new(self)
644 }
645 #[doc = "Bit 19 - ARDY Timeout Disable for Bank 1"]
646 #[inline(always)]
647 pub fn ardyto1dis(&mut self) -> ARDYTO1DIS_W {
648 ARDYTO1DIS_W::new(self)
649 }
650 #[doc = "Bit 20 - ARDY Enable for Bank 2"]
651 #[inline(always)]
652 pub fn ardy2en(&mut self) -> ARDY2EN_W {
653 ARDY2EN_W::new(self)
654 }
655 #[doc = "Bit 21 - ARDY Timeout Disable for Bank 2"]
656 #[inline(always)]
657 pub fn ardyto2dis(&mut self) -> ARDYTO2DIS_W {
658 ARDYTO2DIS_W::new(self)
659 }
660 #[doc = "Bit 22 - ARDY Enable for Bank 3"]
661 #[inline(always)]
662 pub fn ardy3en(&mut self) -> ARDY3EN_W {
663 ARDY3EN_W::new(self)
664 }
665 #[doc = "Bit 23 - ARDY Timeout Disable for Bank 3"]
666 #[inline(always)]
667 pub fn ardyto3dis(&mut self) -> ARDYTO3DIS_W {
668 ARDYTO3DIS_W::new(self)
669 }
670 #[doc = "Bit 24 - Byte Lane Enable for Bank 0"]
671 #[inline(always)]
672 pub fn bl(&mut self) -> BL_W {
673 BL_W::new(self)
674 }
675 #[doc = "Bit 25 - Byte Lane Enable for Bank 1"]
676 #[inline(always)]
677 pub fn bl1(&mut self) -> BL1_W {
678 BL1_W::new(self)
679 }
680 #[doc = "Bit 26 - Byte Lane Enable for Bank 2"]
681 #[inline(always)]
682 pub fn bl2(&mut self) -> BL2_W {
683 BL2_W::new(self)
684 }
685 #[doc = "Bit 27 - Byte Lane Enable for Bank 3"]
686 #[inline(always)]
687 pub fn bl3(&mut self) -> BL3_W {
688 BL3_W::new(self)
689 }
690 #[doc = "Bit 30 - Individual Timing Set, Line Polarity and Mode Definition Enable"]
691 #[inline(always)]
692 pub fn its(&mut self) -> ITS_W {
693 ITS_W::new(self)
694 }
695 #[doc = "Bit 31 - Alternative Address Map Enable"]
696 #[inline(always)]
697 pub fn altmap(&mut self) -> ALTMAP_W {
698 ALTMAP_W::new(self)
699 }
700 #[doc = "Writes raw bits to the register."]
701 #[inline(always)]
702 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
703 self.0.bits(bits);
704 self
705 }
706}
707#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
708pub struct CTRL_SPEC;
709impl crate::RegisterSpec for CTRL_SPEC {
710 type Ux = u32;
711}
712#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
713impl crate::Readable for CTRL_SPEC {
714 type Reader = R;
715}
716#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
717impl crate::Writable for CTRL_SPEC {
718 type Writer = W;
719}
720#[doc = "`reset()` method sets CTRL to value 0"]
721impl crate::Resettable for CTRL_SPEC {
722 #[inline(always)]
723 fn reset_value() -> Self::Ux {
724 0
725 }
726}