efm32gg11b820_pac/sdio/
cfgpresetval0.rs1#[doc = "Register `CFGPRESETVAL0` reader"]
2pub struct R(crate::R<CFGPRESETVAL0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CFGPRESETVAL0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CFGPRESETVAL0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CFGPRESETVAL0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CFGPRESETVAL0` writer"]
17pub struct W(crate::W<CFGPRESETVAL0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CFGPRESETVAL0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CFGPRESETVAL0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CFGPRESETVAL0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `INITSDCLKFREQ` reader - Initial SD_CLK Frequency"]
38pub type INITSDCLKFREQ_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `INITSDCLKFREQ` writer - Initial SD_CLK Frequency"]
40pub type INITSDCLKFREQ_W<'a> = crate::FieldWriter<'a, u32, CFGPRESETVAL0_SPEC, u16, u16, 10, 0>;
41#[doc = "Field `INITCLKGENEN` reader - Initial Clock Gen Enable"]
42pub type INITCLKGENEN_R = crate::BitReader<bool>;
43#[doc = "Field `INITCLKGENEN` writer - Initial Clock Gen Enable"]
44pub type INITCLKGENEN_W<'a> = crate::BitWriter<'a, u32, CFGPRESETVAL0_SPEC, bool, 10>;
45#[doc = "Field `INITDRVST` reader - Initial Drive Strength"]
46pub type INITDRVST_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `INITDRVST` writer - Initial Drive Strength"]
48pub type INITDRVST_W<'a> = crate::FieldWriter<'a, u32, CFGPRESETVAL0_SPEC, u8, u8, 2, 11>;
49#[doc = "Field `DSPSDCLKFREQ` reader - Preset Value for Default Speed of SD_CLK"]
50pub type DSPSDCLKFREQ_R = crate::FieldReader<u16, u16>;
51#[doc = "Field `DSPSDCLKFREQ` writer - Preset Value for Default Speed of SD_CLK"]
52pub type DSPSDCLKFREQ_W<'a> = crate::FieldWriter<'a, u32, CFGPRESETVAL0_SPEC, u16, u16, 10, 16>;
53#[doc = "Field `DSPCLKGENEN` reader - Default Speed Clock Gen Enable"]
54pub type DSPCLKGENEN_R = crate::BitReader<bool>;
55#[doc = "Field `DSPCLKGENEN` writer - Default Speed Clock Gen Enable"]
56pub type DSPCLKGENEN_W<'a> = crate::BitWriter<'a, u32, CFGPRESETVAL0_SPEC, bool, 26>;
57#[doc = "Field `DSPDRVST` reader - Default Speed Drive Strength"]
58pub type DSPDRVST_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `DSPDRVST` writer - Default Speed Drive Strength"]
60pub type DSPDRVST_W<'a> = crate::FieldWriter<'a, u32, CFGPRESETVAL0_SPEC, u8, u8, 2, 27>;
61impl R {
62 #[doc = "Bits 0:9 - Initial SD_CLK Frequency"]
63 #[inline(always)]
64 pub fn initsdclkfreq(&self) -> INITSDCLKFREQ_R {
65 INITSDCLKFREQ_R::new((self.bits & 0x03ff) as u16)
66 }
67 #[doc = "Bit 10 - Initial Clock Gen Enable"]
68 #[inline(always)]
69 pub fn initclkgenen(&self) -> INITCLKGENEN_R {
70 INITCLKGENEN_R::new(((self.bits >> 10) & 1) != 0)
71 }
72 #[doc = "Bits 11:12 - Initial Drive Strength"]
73 #[inline(always)]
74 pub fn initdrvst(&self) -> INITDRVST_R {
75 INITDRVST_R::new(((self.bits >> 11) & 3) as u8)
76 }
77 #[doc = "Bits 16:25 - Preset Value for Default Speed of SD_CLK"]
78 #[inline(always)]
79 pub fn dspsdclkfreq(&self) -> DSPSDCLKFREQ_R {
80 DSPSDCLKFREQ_R::new(((self.bits >> 16) & 0x03ff) as u16)
81 }
82 #[doc = "Bit 26 - Default Speed Clock Gen Enable"]
83 #[inline(always)]
84 pub fn dspclkgenen(&self) -> DSPCLKGENEN_R {
85 DSPCLKGENEN_R::new(((self.bits >> 26) & 1) != 0)
86 }
87 #[doc = "Bits 27:28 - Default Speed Drive Strength"]
88 #[inline(always)]
89 pub fn dspdrvst(&self) -> DSPDRVST_R {
90 DSPDRVST_R::new(((self.bits >> 27) & 3) as u8)
91 }
92}
93impl W {
94 #[doc = "Bits 0:9 - Initial SD_CLK Frequency"]
95 #[inline(always)]
96 pub fn initsdclkfreq(&mut self) -> INITSDCLKFREQ_W {
97 INITSDCLKFREQ_W::new(self)
98 }
99 #[doc = "Bit 10 - Initial Clock Gen Enable"]
100 #[inline(always)]
101 pub fn initclkgenen(&mut self) -> INITCLKGENEN_W {
102 INITCLKGENEN_W::new(self)
103 }
104 #[doc = "Bits 11:12 - Initial Drive Strength"]
105 #[inline(always)]
106 pub fn initdrvst(&mut self) -> INITDRVST_W {
107 INITDRVST_W::new(self)
108 }
109 #[doc = "Bits 16:25 - Preset Value for Default Speed of SD_CLK"]
110 #[inline(always)]
111 pub fn dspsdclkfreq(&mut self) -> DSPSDCLKFREQ_W {
112 DSPSDCLKFREQ_W::new(self)
113 }
114 #[doc = "Bit 26 - Default Speed Clock Gen Enable"]
115 #[inline(always)]
116 pub fn dspclkgenen(&mut self) -> DSPCLKGENEN_W {
117 DSPCLKGENEN_W::new(self)
118 }
119 #[doc = "Bits 27:28 - Default Speed Drive Strength"]
120 #[inline(always)]
121 pub fn dspdrvst(&mut self) -> DSPDRVST_W {
122 DSPDRVST_W::new(self)
123 }
124 #[doc = "Writes raw bits to the register."]
125 #[inline(always)]
126 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
127 self.0.bits(bits);
128 self
129 }
130}
131#[doc = "Core Configuration Preset Value 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgpresetval0](index.html) module"]
132pub struct CFGPRESETVAL0_SPEC;
133impl crate::RegisterSpec for CFGPRESETVAL0_SPEC {
134 type Ux = u32;
135}
136#[doc = "`read()` method returns [cfgpresetval0::R](R) reader structure"]
137impl crate::Readable for CFGPRESETVAL0_SPEC {
138 type Reader = R;
139}
140#[doc = "`write(|w| ..)` method takes [cfgpresetval0::W](W) writer structure"]
141impl crate::Writable for CFGPRESETVAL0_SPEC {
142 type Writer = W;
143}
144#[doc = "`reset()` method sets CFGPRESETVAL0 to value 0"]
145impl crate::Resettable for CFGPRESETVAL0_SPEC {
146 #[inline(always)]
147 fn reset_value() -> Self::Ux {
148 0
149 }
150}