efm32gg11b510_pac/cmu/
hfxosteadystatectrl.rs

1#[doc = "Register `HFXOSTEADYSTATECTRL` reader"]
2pub struct R(crate::R<HFXOSTEADYSTATECTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFXOSTEADYSTATECTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFXOSTEADYSTATECTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFXOSTEADYSTATECTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFXOSTEADYSTATECTRL` writer"]
17pub struct W(crate::W<HFXOSTEADYSTATECTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFXOSTEADYSTATECTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFXOSTEADYSTATECTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFXOSTEADYSTATECTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `IBTRIMXOCORE` reader - Sets the Steady State Oscillator Core Bias Current."]
38pub type IBTRIMXOCORE_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `IBTRIMXOCORE` writer - Sets the Steady State Oscillator Core Bias Current."]
40pub type IBTRIMXOCORE_W<'a> =
41    crate::FieldWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, u16, u16, 11, 0>;
42#[doc = "Field `CTUNE` reader - Sets Oscillator Tuning Capacitance"]
43pub type CTUNE_R = crate::FieldReader<u16, u16>;
44#[doc = "Field `CTUNE` writer - Sets Oscillator Tuning Capacitance"]
45pub type CTUNE_W<'a> = crate::FieldWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, u16, u16, 9, 11>;
46#[doc = "Field `PEAKDETEN` reader - Enables Oscillator Peak Detectors"]
47pub type PEAKDETEN_R = crate::BitReader<bool>;
48#[doc = "Field `PEAKDETEN` writer - Enables Oscillator Peak Detectors"]
49pub type PEAKDETEN_W<'a> = crate::BitWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, bool, 26>;
50#[doc = "Field `PEAKMONEN` reader - Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO"]
51pub type PEAKMONEN_R = crate::BitReader<bool>;
52#[doc = "Field `PEAKMONEN` writer - Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO"]
53pub type PEAKMONEN_W<'a> = crate::BitWriter<'a, u32, HFXOSTEADYSTATECTRL_SPEC, bool, 27>;
54impl R {
55    #[doc = "Bits 0:10 - Sets the Steady State Oscillator Core Bias Current."]
56    #[inline(always)]
57    pub fn ibtrimxocore(&self) -> IBTRIMXOCORE_R {
58        IBTRIMXOCORE_R::new((self.bits & 0x07ff) as u16)
59    }
60    #[doc = "Bits 11:19 - Sets Oscillator Tuning Capacitance"]
61    #[inline(always)]
62    pub fn ctune(&self) -> CTUNE_R {
63        CTUNE_R::new(((self.bits >> 11) & 0x01ff) as u16)
64    }
65    #[doc = "Bit 26 - Enables Oscillator Peak Detectors"]
66    #[inline(always)]
67    pub fn peakdeten(&self) -> PEAKDETEN_R {
68        PEAKDETEN_R::new(((self.bits >> 26) & 1) != 0)
69    }
70    #[doc = "Bit 27 - Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO"]
71    #[inline(always)]
72    pub fn peakmonen(&self) -> PEAKMONEN_R {
73        PEAKMONEN_R::new(((self.bits >> 27) & 1) != 0)
74    }
75}
76impl W {
77    #[doc = "Bits 0:10 - Sets the Steady State Oscillator Core Bias Current."]
78    #[inline(always)]
79    pub fn ibtrimxocore(&mut self) -> IBTRIMXOCORE_W {
80        IBTRIMXOCORE_W::new(self)
81    }
82    #[doc = "Bits 11:19 - Sets Oscillator Tuning Capacitance"]
83    #[inline(always)]
84    pub fn ctune(&mut self) -> CTUNE_W {
85        CTUNE_W::new(self)
86    }
87    #[doc = "Bit 26 - Enables Oscillator Peak Detectors"]
88    #[inline(always)]
89    pub fn peakdeten(&mut self) -> PEAKDETEN_W {
90        PEAKDETEN_W::new(self)
91    }
92    #[doc = "Bit 27 - Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO"]
93    #[inline(always)]
94    pub fn peakmonen(&mut self) -> PEAKMONEN_W {
95        PEAKMONEN_W::new(self)
96    }
97    #[doc = "Writes raw bits to the register."]
98    #[inline(always)]
99    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
100        self.0.bits(bits);
101        self
102    }
103}
104#[doc = "HFXO Steady State Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfxosteadystatectrl](index.html) module"]
105pub struct HFXOSTEADYSTATECTRL_SPEC;
106impl crate::RegisterSpec for HFXOSTEADYSTATECTRL_SPEC {
107    type Ux = u32;
108}
109#[doc = "`read()` method returns [hfxosteadystatectrl::R](R) reader structure"]
110impl crate::Readable for HFXOSTEADYSTATECTRL_SPEC {
111    type Reader = R;
112}
113#[doc = "`write(|w| ..)` method takes [hfxosteadystatectrl::W](W) writer structure"]
114impl crate::Writable for HFXOSTEADYSTATECTRL_SPEC {
115    type Writer = W;
116}
117#[doc = "`reset()` method sets HFXOSTEADYSTATECTRL to value 0x0800_0100"]
118impl crate::Resettable for HFXOSTEADYSTATECTRL_SPEC {
119    #[inline(always)]
120    fn reset_value() -> Self::Ux {
121        0x0800_0100
122    }
123}
efm32gg11b510_pac/cmu/hfxosteadystatectrl.rs

efm32gg11b510_pac/cmu/
hfxosteadystatectrl.rs
