1#[doc = "Register `CH11_REQSEL` reader"]
2pub struct R(crate::R<CH11_REQSEL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CH11_REQSEL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CH11_REQSEL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CH11_REQSEL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CH11_REQSEL` writer"]
17pub struct W(crate::W<CH11_REQSEL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CH11_REQSEL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CH11_REQSEL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CH11_REQSEL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH11_REQSEL_SPEC, u8, u8, 4, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45 #[doc = "0: No source selected"]
46 NONE = 0,
47 #[doc = "1: Peripheral Reflex System"]
48 PRS = 1,
49 #[doc = "8: Analog to Digital Converter 0"]
50 ADC0 = 8,
51 #[doc = "9: Analog to Digital Converter 0"]
52 ADC1 = 9,
53 #[doc = "10: Digital to Analog Converter 0"]
54 VDAC0 = 10,
55 #[doc = "12: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
56 USART0 = 12,
57 #[doc = "13: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
58 USART1 = 13,
59 #[doc = "14: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
60 USART2 = 14,
61 #[doc = "15: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
62 USART3 = 15,
63 #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
64 USART4 = 16,
65 #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 5"]
66 USART5 = 17,
67 #[doc = "18: Universal Asynchronous Receiver/Transmitter 0"]
68 UART0 = 18,
69 #[doc = "19: Universal Asynchronous Receiver/Transmitter 1"]
70 UART1 = 19,
71 #[doc = "20: Low Energy UART 0"]
72 LEUART0 = 20,
73 #[doc = "21: Low Energy UART 1"]
74 LEUART1 = 21,
75 #[doc = "22: I2C 0"]
76 I2C0 = 22,
77 #[doc = "23: I2C 1"]
78 I2C1 = 23,
79 #[doc = "24: I2C 2"]
80 I2C2 = 24,
81 #[doc = "25: Timer 0"]
82 TIMER0 = 25,
83 #[doc = "26: Timer 1"]
84 TIMER1 = 26,
85 #[doc = "27: Timer 2"]
86 TIMER2 = 27,
87 #[doc = "28: Timer 3"]
88 TIMER3 = 28,
89 #[doc = "29: Timer 4"]
90 TIMER4 = 29,
91 #[doc = "30: Timer 5"]
92 TIMER5 = 30,
93 #[doc = "31: Timer 6"]
94 TIMER6 = 31,
95 #[doc = "32: Wide Timer 0"]
96 WTIMER0 = 32,
97 #[doc = "33: Wide Timer 0"]
98 WTIMER1 = 33,
99 #[doc = "34: Wide Timer 2"]
100 WTIMER2 = 34,
101 #[doc = "35: Wide Timer 3"]
102 WTIMER3 = 35,
103 #[doc = "48: Memory System Controller"]
104 MSC = 48,
105 #[doc = "49: Advanced Encryption Standard Accelerator"]
106 CRYPTO0 = 49,
107 #[doc = "50: External Bus Interface"]
108 EBI = 50,
109 #[doc = "61: Capacitive touch sense module"]
110 CSEN = 61,
111 #[doc = "62: Low Energy Sensor Interface"]
112 LESENSE = 62,
113}
114impl From<SOURCESEL_A> for u8 {
115 #[inline(always)]
116 fn from(variant: SOURCESEL_A) -> Self {
117 variant as _
118 }
119}
120#[doc = "Field `SOURCESEL` reader - Source Select"]
121pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
122impl SOURCESEL_R {
123 #[doc = "Get enumerated values variant"]
124 #[inline(always)]
125 pub fn variant(&self) -> Option<SOURCESEL_A> {
126 match self.bits {
127 0 => Some(SOURCESEL_A::NONE),
128 1 => Some(SOURCESEL_A::PRS),
129 8 => Some(SOURCESEL_A::ADC0),
130 9 => Some(SOURCESEL_A::ADC1),
131 10 => Some(SOURCESEL_A::VDAC0),
132 12 => Some(SOURCESEL_A::USART0),
133 13 => Some(SOURCESEL_A::USART1),
134 14 => Some(SOURCESEL_A::USART2),
135 15 => Some(SOURCESEL_A::USART3),
136 16 => Some(SOURCESEL_A::USART4),
137 17 => Some(SOURCESEL_A::USART5),
138 18 => Some(SOURCESEL_A::UART0),
139 19 => Some(SOURCESEL_A::UART1),
140 20 => Some(SOURCESEL_A::LEUART0),
141 21 => Some(SOURCESEL_A::LEUART1),
142 22 => Some(SOURCESEL_A::I2C0),
143 23 => Some(SOURCESEL_A::I2C1),
144 24 => Some(SOURCESEL_A::I2C2),
145 25 => Some(SOURCESEL_A::TIMER0),
146 26 => Some(SOURCESEL_A::TIMER1),
147 27 => Some(SOURCESEL_A::TIMER2),
148 28 => Some(SOURCESEL_A::TIMER3),
149 29 => Some(SOURCESEL_A::TIMER4),
150 30 => Some(SOURCESEL_A::TIMER5),
151 31 => Some(SOURCESEL_A::TIMER6),
152 32 => Some(SOURCESEL_A::WTIMER0),
153 33 => Some(SOURCESEL_A::WTIMER1),
154 34 => Some(SOURCESEL_A::WTIMER2),
155 35 => Some(SOURCESEL_A::WTIMER3),
156 48 => Some(SOURCESEL_A::MSC),
157 49 => Some(SOURCESEL_A::CRYPTO0),
158 50 => Some(SOURCESEL_A::EBI),
159 61 => Some(SOURCESEL_A::CSEN),
160 62 => Some(SOURCESEL_A::LESENSE),
161 _ => None,
162 }
163 }
164 #[doc = "Checks if the value of the field is `NONE`"]
165 #[inline(always)]
166 pub fn is_none(&self) -> bool {
167 *self == SOURCESEL_A::NONE
168 }
169 #[doc = "Checks if the value of the field is `PRS`"]
170 #[inline(always)]
171 pub fn is_prs(&self) -> bool {
172 *self == SOURCESEL_A::PRS
173 }
174 #[doc = "Checks if the value of the field is `ADC0`"]
175 #[inline(always)]
176 pub fn is_adc0(&self) -> bool {
177 *self == SOURCESEL_A::ADC0
178 }
179 #[doc = "Checks if the value of the field is `ADC1`"]
180 #[inline(always)]
181 pub fn is_adc1(&self) -> bool {
182 *self == SOURCESEL_A::ADC1
183 }
184 #[doc = "Checks if the value of the field is `VDAC0`"]
185 #[inline(always)]
186 pub fn is_vdac0(&self) -> bool {
187 *self == SOURCESEL_A::VDAC0
188 }
189 #[doc = "Checks if the value of the field is `USART0`"]
190 #[inline(always)]
191 pub fn is_usart0(&self) -> bool {
192 *self == SOURCESEL_A::USART0
193 }
194 #[doc = "Checks if the value of the field is `USART1`"]
195 #[inline(always)]
196 pub fn is_usart1(&self) -> bool {
197 *self == SOURCESEL_A::USART1
198 }
199 #[doc = "Checks if the value of the field is `USART2`"]
200 #[inline(always)]
201 pub fn is_usart2(&self) -> bool {
202 *self == SOURCESEL_A::USART2
203 }
204 #[doc = "Checks if the value of the field is `USART3`"]
205 #[inline(always)]
206 pub fn is_usart3(&self) -> bool {
207 *self == SOURCESEL_A::USART3
208 }
209 #[doc = "Checks if the value of the field is `USART4`"]
210 #[inline(always)]
211 pub fn is_usart4(&self) -> bool {
212 *self == SOURCESEL_A::USART4
213 }
214 #[doc = "Checks if the value of the field is `USART5`"]
215 #[inline(always)]
216 pub fn is_usart5(&self) -> bool {
217 *self == SOURCESEL_A::USART5
218 }
219 #[doc = "Checks if the value of the field is `UART0`"]
220 #[inline(always)]
221 pub fn is_uart0(&self) -> bool {
222 *self == SOURCESEL_A::UART0
223 }
224 #[doc = "Checks if the value of the field is `UART1`"]
225 #[inline(always)]
226 pub fn is_uart1(&self) -> bool {
227 *self == SOURCESEL_A::UART1
228 }
229 #[doc = "Checks if the value of the field is `LEUART0`"]
230 #[inline(always)]
231 pub fn is_leuart0(&self) -> bool {
232 *self == SOURCESEL_A::LEUART0
233 }
234 #[doc = "Checks if the value of the field is `LEUART1`"]
235 #[inline(always)]
236 pub fn is_leuart1(&self) -> bool {
237 *self == SOURCESEL_A::LEUART1
238 }
239 #[doc = "Checks if the value of the field is `I2C0`"]
240 #[inline(always)]
241 pub fn is_i2c0(&self) -> bool {
242 *self == SOURCESEL_A::I2C0
243 }
244 #[doc = "Checks if the value of the field is `I2C1`"]
245 #[inline(always)]
246 pub fn is_i2c1(&self) -> bool {
247 *self == SOURCESEL_A::I2C1
248 }
249 #[doc = "Checks if the value of the field is `I2C2`"]
250 #[inline(always)]
251 pub fn is_i2c2(&self) -> bool {
252 *self == SOURCESEL_A::I2C2
253 }
254 #[doc = "Checks if the value of the field is `TIMER0`"]
255 #[inline(always)]
256 pub fn is_timer0(&self) -> bool {
257 *self == SOURCESEL_A::TIMER0
258 }
259 #[doc = "Checks if the value of the field is `TIMER1`"]
260 #[inline(always)]
261 pub fn is_timer1(&self) -> bool {
262 *self == SOURCESEL_A::TIMER1
263 }
264 #[doc = "Checks if the value of the field is `TIMER2`"]
265 #[inline(always)]
266 pub fn is_timer2(&self) -> bool {
267 *self == SOURCESEL_A::TIMER2
268 }
269 #[doc = "Checks if the value of the field is `TIMER3`"]
270 #[inline(always)]
271 pub fn is_timer3(&self) -> bool {
272 *self == SOURCESEL_A::TIMER3
273 }
274 #[doc = "Checks if the value of the field is `TIMER4`"]
275 #[inline(always)]
276 pub fn is_timer4(&self) -> bool {
277 *self == SOURCESEL_A::TIMER4
278 }
279 #[doc = "Checks if the value of the field is `TIMER5`"]
280 #[inline(always)]
281 pub fn is_timer5(&self) -> bool {
282 *self == SOURCESEL_A::TIMER5
283 }
284 #[doc = "Checks if the value of the field is `TIMER6`"]
285 #[inline(always)]
286 pub fn is_timer6(&self) -> bool {
287 *self == SOURCESEL_A::TIMER6
288 }
289 #[doc = "Checks if the value of the field is `WTIMER0`"]
290 #[inline(always)]
291 pub fn is_wtimer0(&self) -> bool {
292 *self == SOURCESEL_A::WTIMER0
293 }
294 #[doc = "Checks if the value of the field is `WTIMER1`"]
295 #[inline(always)]
296 pub fn is_wtimer1(&self) -> bool {
297 *self == SOURCESEL_A::WTIMER1
298 }
299 #[doc = "Checks if the value of the field is `WTIMER2`"]
300 #[inline(always)]
301 pub fn is_wtimer2(&self) -> bool {
302 *self == SOURCESEL_A::WTIMER2
303 }
304 #[doc = "Checks if the value of the field is `WTIMER3`"]
305 #[inline(always)]
306 pub fn is_wtimer3(&self) -> bool {
307 *self == SOURCESEL_A::WTIMER3
308 }
309 #[doc = "Checks if the value of the field is `MSC`"]
310 #[inline(always)]
311 pub fn is_msc(&self) -> bool {
312 *self == SOURCESEL_A::MSC
313 }
314 #[doc = "Checks if the value of the field is `CRYPTO0`"]
315 #[inline(always)]
316 pub fn is_crypto0(&self) -> bool {
317 *self == SOURCESEL_A::CRYPTO0
318 }
319 #[doc = "Checks if the value of the field is `EBI`"]
320 #[inline(always)]
321 pub fn is_ebi(&self) -> bool {
322 *self == SOURCESEL_A::EBI
323 }
324 #[doc = "Checks if the value of the field is `CSEN`"]
325 #[inline(always)]
326 pub fn is_csen(&self) -> bool {
327 *self == SOURCESEL_A::CSEN
328 }
329 #[doc = "Checks if the value of the field is `LESENSE`"]
330 #[inline(always)]
331 pub fn is_lesense(&self) -> bool {
332 *self == SOURCESEL_A::LESENSE
333 }
334}
335#[doc = "Field `SOURCESEL` writer - Source Select"]
336pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH11_REQSEL_SPEC, u8, SOURCESEL_A, 6, 16>;
337impl<'a> SOURCESEL_W<'a> {
338 #[doc = "No source selected"]
339 #[inline(always)]
340 pub fn none(self) -> &'a mut W {
341 self.variant(SOURCESEL_A::NONE)
342 }
343 #[doc = "Peripheral Reflex System"]
344 #[inline(always)]
345 pub fn prs(self) -> &'a mut W {
346 self.variant(SOURCESEL_A::PRS)
347 }
348 #[doc = "Analog to Digital Converter 0"]
349 #[inline(always)]
350 pub fn adc0(self) -> &'a mut W {
351 self.variant(SOURCESEL_A::ADC0)
352 }
353 #[doc = "Analog to Digital Converter 0"]
354 #[inline(always)]
355 pub fn adc1(self) -> &'a mut W {
356 self.variant(SOURCESEL_A::ADC1)
357 }
358 #[doc = "Digital to Analog Converter 0"]
359 #[inline(always)]
360 pub fn vdac0(self) -> &'a mut W {
361 self.variant(SOURCESEL_A::VDAC0)
362 }
363 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
364 #[inline(always)]
365 pub fn usart0(self) -> &'a mut W {
366 self.variant(SOURCESEL_A::USART0)
367 }
368 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
369 #[inline(always)]
370 pub fn usart1(self) -> &'a mut W {
371 self.variant(SOURCESEL_A::USART1)
372 }
373 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
374 #[inline(always)]
375 pub fn usart2(self) -> &'a mut W {
376 self.variant(SOURCESEL_A::USART2)
377 }
378 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
379 #[inline(always)]
380 pub fn usart3(self) -> &'a mut W {
381 self.variant(SOURCESEL_A::USART3)
382 }
383 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
384 #[inline(always)]
385 pub fn usart4(self) -> &'a mut W {
386 self.variant(SOURCESEL_A::USART4)
387 }
388 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 5"]
389 #[inline(always)]
390 pub fn usart5(self) -> &'a mut W {
391 self.variant(SOURCESEL_A::USART5)
392 }
393 #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
394 #[inline(always)]
395 pub fn uart0(self) -> &'a mut W {
396 self.variant(SOURCESEL_A::UART0)
397 }
398 #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
399 #[inline(always)]
400 pub fn uart1(self) -> &'a mut W {
401 self.variant(SOURCESEL_A::UART1)
402 }
403 #[doc = "Low Energy UART 0"]
404 #[inline(always)]
405 pub fn leuart0(self) -> &'a mut W {
406 self.variant(SOURCESEL_A::LEUART0)
407 }
408 #[doc = "Low Energy UART 1"]
409 #[inline(always)]
410 pub fn leuart1(self) -> &'a mut W {
411 self.variant(SOURCESEL_A::LEUART1)
412 }
413 #[doc = "I2C 0"]
414 #[inline(always)]
415 pub fn i2c0(self) -> &'a mut W {
416 self.variant(SOURCESEL_A::I2C0)
417 }
418 #[doc = "I2C 1"]
419 #[inline(always)]
420 pub fn i2c1(self) -> &'a mut W {
421 self.variant(SOURCESEL_A::I2C1)
422 }
423 #[doc = "I2C 2"]
424 #[inline(always)]
425 pub fn i2c2(self) -> &'a mut W {
426 self.variant(SOURCESEL_A::I2C2)
427 }
428 #[doc = "Timer 0"]
429 #[inline(always)]
430 pub fn timer0(self) -> &'a mut W {
431 self.variant(SOURCESEL_A::TIMER0)
432 }
433 #[doc = "Timer 1"]
434 #[inline(always)]
435 pub fn timer1(self) -> &'a mut W {
436 self.variant(SOURCESEL_A::TIMER1)
437 }
438 #[doc = "Timer 2"]
439 #[inline(always)]
440 pub fn timer2(self) -> &'a mut W {
441 self.variant(SOURCESEL_A::TIMER2)
442 }
443 #[doc = "Timer 3"]
444 #[inline(always)]
445 pub fn timer3(self) -> &'a mut W {
446 self.variant(SOURCESEL_A::TIMER3)
447 }
448 #[doc = "Timer 4"]
449 #[inline(always)]
450 pub fn timer4(self) -> &'a mut W {
451 self.variant(SOURCESEL_A::TIMER4)
452 }
453 #[doc = "Timer 5"]
454 #[inline(always)]
455 pub fn timer5(self) -> &'a mut W {
456 self.variant(SOURCESEL_A::TIMER5)
457 }
458 #[doc = "Timer 6"]
459 #[inline(always)]
460 pub fn timer6(self) -> &'a mut W {
461 self.variant(SOURCESEL_A::TIMER6)
462 }
463 #[doc = "Wide Timer 0"]
464 #[inline(always)]
465 pub fn wtimer0(self) -> &'a mut W {
466 self.variant(SOURCESEL_A::WTIMER0)
467 }
468 #[doc = "Wide Timer 0"]
469 #[inline(always)]
470 pub fn wtimer1(self) -> &'a mut W {
471 self.variant(SOURCESEL_A::WTIMER1)
472 }
473 #[doc = "Wide Timer 2"]
474 #[inline(always)]
475 pub fn wtimer2(self) -> &'a mut W {
476 self.variant(SOURCESEL_A::WTIMER2)
477 }
478 #[doc = "Wide Timer 3"]
479 #[inline(always)]
480 pub fn wtimer3(self) -> &'a mut W {
481 self.variant(SOURCESEL_A::WTIMER3)
482 }
483 #[doc = "Memory System Controller"]
484 #[inline(always)]
485 pub fn msc(self) -> &'a mut W {
486 self.variant(SOURCESEL_A::MSC)
487 }
488 #[doc = "Advanced Encryption Standard Accelerator"]
489 #[inline(always)]
490 pub fn crypto0(self) -> &'a mut W {
491 self.variant(SOURCESEL_A::CRYPTO0)
492 }
493 #[doc = "External Bus Interface"]
494 #[inline(always)]
495 pub fn ebi(self) -> &'a mut W {
496 self.variant(SOURCESEL_A::EBI)
497 }
498 #[doc = "Capacitive touch sense module"]
499 #[inline(always)]
500 pub fn csen(self) -> &'a mut W {
501 self.variant(SOURCESEL_A::CSEN)
502 }
503 #[doc = "Low Energy Sensor Interface"]
504 #[inline(always)]
505 pub fn lesense(self) -> &'a mut W {
506 self.variant(SOURCESEL_A::LESENSE)
507 }
508}
509impl R {
510 #[doc = "Bits 0:3 - Signal Select"]
511 #[inline(always)]
512 pub fn sigsel(&self) -> SIGSEL_R {
513 SIGSEL_R::new((self.bits & 0x0f) as u8)
514 }
515 #[doc = "Bits 16:21 - Source Select"]
516 #[inline(always)]
517 pub fn sourcesel(&self) -> SOURCESEL_R {
518 SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
519 }
520}
521impl W {
522 #[doc = "Bits 0:3 - Signal Select"]
523 #[inline(always)]
524 pub fn sigsel(&mut self) -> SIGSEL_W {
525 SIGSEL_W::new(self)
526 }
527 #[doc = "Bits 16:21 - Source Select"]
528 #[inline(always)]
529 pub fn sourcesel(&mut self) -> SOURCESEL_W {
530 SOURCESEL_W::new(self)
531 }
532 #[doc = "Writes raw bits to the register."]
533 #[inline(always)]
534 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
535 self.0.bits(bits);
536 self
537 }
538}
539#[doc = "Channel Peripheral Request Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch11_reqsel](index.html) module"]
540pub struct CH11_REQSEL_SPEC;
541impl crate::RegisterSpec for CH11_REQSEL_SPEC {
542 type Ux = u32;
543}
544#[doc = "`read()` method returns [ch11_reqsel::R](R) reader structure"]
545impl crate::Readable for CH11_REQSEL_SPEC {
546 type Reader = R;
547}
548#[doc = "`write(|w| ..)` method takes [ch11_reqsel::W](W) writer structure"]
549impl crate::Writable for CH11_REQSEL_SPEC {
550 type Writer = W;
551}
552#[doc = "`reset()` method sets CH11_REQSEL to value 0"]
553impl crate::Resettable for CH11_REQSEL_SPEC {
554 #[inline(always)]
555 fn reset_value() -> Self::Ux {
556 0
557 }
558}