Type Definition efm32gg11b::uart1::ctrl::R[][src]

type R = R<u32, CTRL>;
Expand description

Reader of register CTRL

Implementations

Bit 0 - USART Synchronous Mode

Bit 1 - Loopback Enable

Bit 2 - Collision Check Enable

Bit 3 - Multi-Processor Mode

Bit 4 - Multi-Processor Address-Bit

Bits 5:6 - Oversampling

Bit 8 - Clock Polarity

Bit 9 - Clock Edge for Setup/Sample

Bit 10 - Most Significant Bit First

Bit 11 - Action on Slave-Select in Master Mode

Bit 12 - TX Buffer Interrupt Level

Bit 13 - Receiver Input Invert

Bit 14 - Transmitter Output Invert

Bit 15 - Chip Select Invert

Bit 16 - Automatic Chip Select

Bit 17 - Automatic TX Tristate

Bit 18 - SmartCard Mode

Bit 19 - SmartCard Retransmit

Bit 20 - Skip Parity Error Frames

Bit 21 - Bit 8 Default Value

Bit 22 - Halt DMA on Error

Bit 23 - Disable RX on Error

Bit 24 - Disable TX on Error

Bit 25 - Synchronous Slave Setup Early

Bit 28 - Byteswap in Double Accesses

Bit 29 - Always Transmit When RX Not Full

Bit 30 - Majority Vote Disable

Bit 31 - Synchronous Master Sample Delay