Type Definition efm32gg11b::lesense::decctrl::R[][src]

type R = R<u32, DECCTRL>;
Expand description

Reader of register DECCTRL

Implementations

Bit 0 - Disable the Decoder

Bit 1 - Enable Check of Current State

Bit 2 - Enable Decoder to Channel Interrupt Mapping

Bit 3 - Enable Decoder Hysteresis on PRS0 Output

Bit 4 - Enable Decoder Hysteresis on PRS1 Output

Bit 5 - Enable Decoder Hysteresis on PRS2 Output

Bit 6 - Enable Decoder Hysteresis on Interrupt Requests

Bit 7 - Enable Count Mode on Decoder PRS Channels 0 and 1

Bit 8 - LESENSE Decoder Input Configuration

Bits 10:14 - LESENSE Decoder PRS Input 0 Configuration

Bits 15:19 - LESENSE Decoder PRS Input 1 Configuration

Bits 20:24 - LESENSE Decoder PRS Input 2 Configuration

Bits 25:29 - LESENSE Decoder PRS Input 3 Configuration