Struct efm32gg11b::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CTRL>>

pub fn addrfaulten(&mut self) -> ADDRFAULTEN_W<'_>

Bit 0 - Invalid Address Bus Fault Response Enable

pub fn clkdisfaulten(&mut self) -> CLKDISFAULTEN_W<'_>

Bit 1 - Clock-disabled Bus Fault Response Enable

pub fn pwrupondemand(&mut self) -> PWRUPONDEMAND_W<'_>

Bit 2 - Power Up on Demand During Wake Up

pub fn ifcreadclear(&mut self) -> IFCREADCLEAR_W<'_>

Bit 3 - IFC Read Clears IF

pub fn timeoutfaulten(&mut self) -> TIMEOUTFAULTEN_W<'_>

Bit 4 - Timeout Bus Fault Response Enable

pub fn rameccerrfaulten(&mut self) -> RAMECCERRFAULTEN_W<'_>

Bit 5 - Two Bit ECC Error Bus Fault Response Enable

pub fn ebifaulten(&mut self) -> EBIFAULTEN_W<'_>

Bit 6 - EBI Bus Fault Response Enable

pub fn waitmode(&mut self) -> WAITMODE_W<'_>

Bit 12 - Peripheral Access Wait Mode

impl W<u32, Reg<u32, _READCTRL>>

pub fn ifcdis(&mut self) -> IFCDIS_W<'_>

Bit 3 - Internal Flash Cache Disable

pub fn aidis(&mut self) -> AIDIS_W<'_>

Bit 4 - Automatic Invalidate Disable

pub fn iccdis(&mut self) -> ICCDIS_W<'_>

Bit 5 - Interrupt Context Cache Disable

pub fn ebicdis(&mut self) -> EBICDIS_W<'_>

Bit 6 - External Bus Interface Cache Disable

pub fn prefetch(&mut self) -> PREFETCH_W<'_>

Bit 8 - Prefetch Mode

pub fn usehprot(&mut self) -> USEHPROT_W<'_>

Bit 9 - AHB_HPROT Mode

pub fn qspicdis(&mut self) -> QSPICDIS_W<'_>

Bit 10 - QSPI Cache Disable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 24:25 - Read Mode

pub fn scbtp(&mut self) -> SCBTP_W<'_>

Bit 28 - Suppress Conditional Branch Target Perfetch

impl W<u32, Reg<u32, _WRITECTRL>>

pub fn wren(&mut self) -> WREN_W<'_>

Bit 0 - Enable Write/Erase Controller

pub fn irqeraseabort(&mut self) -> IRQERASEABORT_W<'_>

Bit 1 - Abort Page Erase on Interrupt

pub fn rwwen(&mut self) -> RWWEN_W<'_>

Bit 5 - Read-While-Write Enable

impl W<u32, Reg<u32, _WRITECMD>>

pub fn laddrim(&mut self) -> LADDRIM_W<'_>

Bit 0 - Load MSC_ADDRB Into ADDR

pub fn erasepage(&mut self) -> ERASEPAGE_W<'_>

Bit 1 - Erase Page

pub fn writeend(&mut self) -> WRITEEND_W<'_>

Bit 2 - End Write Mode

pub fn writeonce(&mut self) -> WRITEONCE_W<'_>

Bit 3 - Word Write-Once Trigger

pub fn writetrig(&mut self) -> WRITETRIG_W<'_>

Bit 4 - Word Write Sequence Trigger

pub fn eraseabort(&mut self) -> ERASEABORT_W<'_>

Bit 5 - Abort Erase Sequence

pub fn erasemain0(&mut self) -> ERASEMAIN0_W<'_>

Bit 8 - Mass Erase Region 0

pub fn erasemain1(&mut self) -> ERASEMAIN1_W<'_>

Bit 9 - Mass Erase Region 1

pub fn clearwdata(&mut self) -> CLEARWDATA_W<'_>

Bit 12 - Clear WDATA State

impl W<u32, Reg<u32, _ADDRB>>

pub fn addrb(&mut self) -> ADDRB_W<'_>

Bits 0:31 - Page Erase or Write Address Buffer

impl W<u32, Reg<u32, _WDATA>>

pub fn wdata(&mut self) -> WDATA_W<'_>

Bits 0:31 - Write Data

impl W<u32, Reg<u32, _IFS>>

pub fn erase(&mut self) -> ERASE_W<'_>

Bit 0 - Set ERASE Interrupt Flag

pub fn write(&mut self) -> WRITE_W<'_>

Bit 1 - Set WRITE Interrupt Flag

pub fn chof(&mut self) -> CHOF_W<'_>

Bit 2 - Set CHOF Interrupt Flag

pub fn cmof(&mut self) -> CMOF_W<'_>

Bit 3 - Set CMOF Interrupt Flag

pub fn pwrupf(&mut self) -> PWRUPF_W<'_>

Bit 4 - Set PWRUPF Interrupt Flag

pub fn icacherr(&mut self) -> ICACHERR_W<'_>

Bit 5 - Set ICACHERR Interrupt Flag

pub fn wdataov(&mut self) -> WDATAOV_W<'_>

Bit 6 - Set WDATAOV Interrupt Flag

pub fn lvewrite(&mut self) -> LVEWRITE_W<'_>

Bit 8 - Set LVEWRITE Interrupt Flag

pub fn ramerr1b(&mut self) -> RAMERR1B_W<'_>

Bit 16 - Set RAMERR1B Interrupt Flag

pub fn ramerr2b(&mut self) -> RAMERR2B_W<'_>

Bit 17 - Set RAMERR2B Interrupt Flag

pub fn ram1err1b(&mut self) -> RAM1ERR1B_W<'_>

Bit 18 - Set RAM1ERR1B Interrupt Flag

pub fn ram1err2b(&mut self) -> RAM1ERR2B_W<'_>

Bit 19 - Set RAM1ERR2B Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn erase(&mut self) -> ERASE_W<'_>

Bit 0 - Clear ERASE Interrupt Flag

pub fn write(&mut self) -> WRITE_W<'_>

Bit 1 - Clear WRITE Interrupt Flag

pub fn chof(&mut self) -> CHOF_W<'_>

Bit 2 - Clear CHOF Interrupt Flag

pub fn cmof(&mut self) -> CMOF_W<'_>

Bit 3 - Clear CMOF Interrupt Flag

pub fn pwrupf(&mut self) -> PWRUPF_W<'_>

Bit 4 - Clear PWRUPF Interrupt Flag

pub fn icacherr(&mut self) -> ICACHERR_W<'_>

Bit 5 - Clear ICACHERR Interrupt Flag

pub fn wdataov(&mut self) -> WDATAOV_W<'_>

Bit 6 - Clear WDATAOV Interrupt Flag

pub fn lvewrite(&mut self) -> LVEWRITE_W<'_>

Bit 8 - Clear LVEWRITE Interrupt Flag

pub fn ramerr1b(&mut self) -> RAMERR1B_W<'_>

Bit 16 - Clear RAMERR1B Interrupt Flag

pub fn ramerr2b(&mut self) -> RAMERR2B_W<'_>

Bit 17 - Clear RAMERR2B Interrupt Flag

pub fn ram1err1b(&mut self) -> RAM1ERR1B_W<'_>

Bit 18 - Clear RAM1ERR1B Interrupt Flag

pub fn ram1err2b(&mut self) -> RAM1ERR2B_W<'_>

Bit 19 - Clear RAM1ERR2B Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn erase(&mut self) -> ERASE_W<'_>

Bit 0 - ERASE Interrupt Enable

pub fn write(&mut self) -> WRITE_W<'_>

Bit 1 - WRITE Interrupt Enable

pub fn chof(&mut self) -> CHOF_W<'_>

Bit 2 - CHOF Interrupt Enable

pub fn cmof(&mut self) -> CMOF_W<'_>

Bit 3 - CMOF Interrupt Enable

pub fn pwrupf(&mut self) -> PWRUPF_W<'_>

Bit 4 - PWRUPF Interrupt Enable

pub fn icacherr(&mut self) -> ICACHERR_W<'_>

Bit 5 - ICACHERR Interrupt Enable

pub fn wdataov(&mut self) -> WDATAOV_W<'_>

Bit 6 - WDATAOV Interrupt Enable

pub fn lvewrite(&mut self) -> LVEWRITE_W<'_>

Bit 8 - LVEWRITE Interrupt Enable

pub fn ramerr1b(&mut self) -> RAMERR1B_W<'_>

Bit 16 - RAMERR1B Interrupt Enable

pub fn ramerr2b(&mut self) -> RAMERR2B_W<'_>

Bit 17 - RAMERR2B Interrupt Enable

pub fn ram1err1b(&mut self) -> RAM1ERR1B_W<'_>

Bit 18 - RAM1ERR1B Interrupt Enable

pub fn ram1err2b(&mut self) -> RAM1ERR2B_W<'_>

Bit 19 - RAM1ERR2B Interrupt Enable

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock

impl W<u32, Reg<u32, _CACHECMD>>

pub fn invcache(&mut self) -> INVCACHE_W<'_>

Bit 0 - Invalidate Instruction Cache

pub fn startpc(&mut self) -> STARTPC_W<'_>

Bit 1 - Start Performance Counters

pub fn stoppc(&mut self) -> STOPPC_W<'_>

Bit 2 - Stop Performance Counters

impl W<u32, Reg<u32, _MASSLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Mass Erase Lock

impl W<u32, Reg<u32, _STARTUP>>

pub fn stdly0(&mut self) -> STDLY0_W<'_>

Bits 0:9 - Startup Delay 0

pub fn stdly1(&mut self) -> STDLY1_W<'_>

Bits 12:21 - Startup Delay 0

pub fn astwait(&mut self) -> ASTWAIT_W<'_>

Bit 24 - Active Startup Wait

pub fn stwsen(&mut self) -> STWSEN_W<'_>

Bit 25 - Startup Waitstates Enable

pub fn stwsaen(&mut self) -> STWSAEN_W<'_>

Bit 26 - Startup Waitstates Always Enable

pub fn stws(&mut self) -> STWS_W<'_>

Bits 28:30 - Startup Waitstates

impl W<u32, Reg<u32, _BANKSWITCHLOCK>>

pub fn bankswitchlockkey(&mut self) -> BANKSWITCHLOCKKEY_W<'_>

Bits 0:15 - Bank Switching Lock

impl W<u32, Reg<u32, _CMD>>

pub fn pwrup(&mut self) -> PWRUP_W<'_>

Bit 0 - Flash Power Up Command

pub fn switchingbank(&mut self) -> SWITCHINGBANK_W<'_>

Bit 1 - BANK SWITCHING COMMAND

impl W<u32, Reg<u32, _BOOTLOADERCTRL>>

pub fn blrdis(&mut self) -> BLRDIS_W<'_>

Bit 0 - Flash Bootloader Read Disable

pub fn blwdis(&mut self) -> BLWDIS_W<'_>

Bit 1 - Flash Bootloader Write/Erase Disable

impl W<u32, Reg<u32, _AAPUNLOCKCMD>>

pub fn unlockaap(&mut self) -> UNLOCKAAP_W<'_>

Bit 0 - Software Unlock AAP Command

impl W<u32, Reg<u32, _CACHECONFIG0>>

pub fn cachelplevel(&mut self) -> CACHELPLEVEL_W<'_>

Bits 0:1 - Instruction Cache Low-Power Level

impl W<u32, Reg<u32, _RAMCTRL>>

pub fn ramwsen(&mut self) -> RAMWSEN_W<'_>

Bit 1 - RAM WAIT STATE Enable

pub fn ramprefetchen(&mut self) -> RAMPREFETCHEN_W<'_>

Bit 2 - RAM Prefetch Enable

pub fn ram1wsen(&mut self) -> RAM1WSEN_W<'_>

Bit 9 - RAM1 WAIT STATE Enable

pub fn ram1prefetchen(&mut self) -> RAM1PREFETCHEN_W<'_>

Bit 10 - RAM1 Prefetch Enable

pub fn ram2cacheen(&mut self) -> RAM2CACHEEN_W<'_>

Bit 16 - RAM2 CACHE Enable

pub fn ram2wsen(&mut self) -> RAM2WSEN_W<'_>

Bit 17 - RAM2 WAIT STATE Enable

pub fn ram2prefetchen(&mut self) -> RAM2PREFETCHEN_W<'_>

Bit 18 - RAM2 Prefetch Enable

impl W<u32, Reg<u32, _ECCCTRL>>

pub fn rameccewen(&mut self) -> RAMECCEWEN_W<'_>

Bit 0 - RAM ECC Write Enable

pub fn rameccchken(&mut self) -> RAMECCCHKEN_W<'_>

Bit 1 - RAM ECC Check Enable

pub fn ram1eccewen(&mut self) -> RAM1ECCEWEN_W<'_>

Bit 2 - RAM1 ECC Write Enable

pub fn ram1eccchken(&mut self) -> RAM1ECCCHKEN_W<'_>

Bit 3 - RAM1 ECC Check Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn em2block(&mut self) -> EM2BLOCK_W<'_>

Bit 1 - Energy Mode 2 Block

pub fn em2boddis(&mut self) -> EM2BODDIS_W<'_>

Bit 2 - Disable BOD in EM2

pub fn em01ld(&mut self) -> EM01LD_W<'_>

Bit 3 - Reserved for internal use. Do not change.

pub fn em23vscaleautowsen(&mut self) -> EM23VSCALEAUTOWSEN_W<'_>

Bit 4 - Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage

pub fn em23vscale(&mut self) -> EM23VSCALE_W<'_>

Bits 8:9 - EM23 Voltage Scale

pub fn em4hvscale(&mut self) -> EM4HVSCALE_W<'_>

Bits 16:17 - EM4H Voltage Scale

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock Key

impl W<u32, Reg<u32, _RAM0CTRL>>

pub fn rampowerdown(&mut self) -> RAMPOWERDOWN_W<'_>

Bits 0:6 - RAM0 Blockset Power-down

impl W<u32, Reg<u32, _CMD>>

pub fn em4unlatch(&mut self) -> EM4UNLATCH_W<'_>

Bit 0 - EM4 Unlatch

pub fn em01vscale0(&mut self) -> EM01VSCALE0_W<'_>

Bit 4 - EM01 Voltage Scale Command to Scale to Voltage Scale Level 0

pub fn em01vscale2(&mut self) -> EM01VSCALE2_W<'_>

Bit 6 - EM01 Voltage Scale Command to Scale to Voltage Scale Level 2

impl W<u32, Reg<u32, _EM4CTRL>>

pub fn em4state(&mut self) -> EM4STATE_W<'_>

Bit 0 - Energy Mode 4 State

pub fn retainlfrco(&mut self) -> RETAINLFRCO_W<'_>

Bit 1 - LFRCO Retain During EM4

pub fn retainlfxo(&mut self) -> RETAINLFXO_W<'_>

Bit 2 - LFXO Retain During EM4

pub fn retainulfrco(&mut self) -> RETAINULFRCO_W<'_>

Bit 3 - ULFRCO Retain During EM4S

pub fn em4ioretmode(&mut self) -> EM4IORETMODE_W<'_>

Bits 4:5 - EM4 IO Retention Disable

pub fn em4entry(&mut self) -> EM4ENTRY_W<'_>

Bits 16:17 - Energy Mode 4 Entry

impl W<u32, Reg<u32, _TEMPLIMITS>>

pub fn templow(&mut self) -> TEMPLOW_W<'_>

Bits 0:7 - Temperature Low Limit

pub fn temphigh(&mut self) -> TEMPHIGH_W<'_>

Bits 8:15 - Temperature High Limit

pub fn em4wuen(&mut self) -> EM4WUEN_W<'_>

Bit 16 - Enable EM4 Wakeup Due to Low/high Temperature

impl W<u32, Reg<u32, _IFS>>

pub fn vmonavddfall(&mut self) -> VMONAVDDFALL_W<'_>

Bit 0 - Set VMONAVDDFALL Interrupt Flag

pub fn vmonavddrise(&mut self) -> VMONAVDDRISE_W<'_>

Bit 1 - Set VMONAVDDRISE Interrupt Flag

pub fn vmonaltavddfall(&mut self) -> VMONALTAVDDFALL_W<'_>

Bit 2 - Set VMONALTAVDDFALL Interrupt Flag

pub fn vmonaltavddrise(&mut self) -> VMONALTAVDDRISE_W<'_>

Bit 3 - Set VMONALTAVDDRISE Interrupt Flag

pub fn vmondvddfall(&mut self) -> VMONDVDDFALL_W<'_>

Bit 4 - Set VMONDVDDFALL Interrupt Flag

pub fn vmondvddrise(&mut self) -> VMONDVDDRISE_W<'_>

Bit 5 - Set VMONDVDDRISE Interrupt Flag

pub fn vmonio0fall(&mut self) -> VMONIO0FALL_W<'_>

Bit 6 - Set VMONIO0FALL Interrupt Flag

pub fn vmonio0rise(&mut self) -> VMONIO0RISE_W<'_>

Bit 7 - Set VMONIO0RISE Interrupt Flag

pub fn vmonio1fall(&mut self) -> VMONIO1FALL_W<'_>

Bit 8 - Set VMONIO1FALL Interrupt Flag

pub fn vmonio1rise(&mut self) -> VMONIO1RISE_W<'_>

Bit 9 - Set VMONIO1RISE Interrupt Flag

pub fn r5vready(&mut self) -> R5VREADY_W<'_>

Bit 10 - Set R5VREADY Interrupt Flag

pub fn vmonbuvddfall(&mut self) -> VMONBUVDDFALL_W<'_>

Bit 12 - Set VMONBUVDDFALL Interrupt Flag

pub fn vmonbuvddrise(&mut self) -> VMONBUVDDRISE_W<'_>

Bit 13 - Set VMONBUVDDRISE Interrupt Flag

pub fn pfetovercurrentlimit(&mut self) -> PFETOVERCURRENTLIMIT_W<'_>

Bit 16 - Set PFETOVERCURRENTLIMIT Interrupt Flag

pub fn nfetovercurrentlimit(&mut self) -> NFETOVERCURRENTLIMIT_W<'_>

Bit 17 - Set NFETOVERCURRENTLIMIT Interrupt Flag

pub fn dcdclprunning(&mut self) -> DCDCLPRUNNING_W<'_>

Bit 18 - Set DCDCLPRUNNING Interrupt Flag

pub fn dcdclnrunning(&mut self) -> DCDCLNRUNNING_W<'_>

Bit 19 - Set DCDCLNRUNNING Interrupt Flag

pub fn dcdcinbypass(&mut self) -> DCDCINBYPASS_W<'_>

Bit 20 - Set DCDCINBYPASS Interrupt Flag

pub fn burdy(&mut self) -> BURDY_W<'_>

Bit 22 - Set BURDY Interrupt Flag

pub fn r5vvsint(&mut self) -> R5VVSINT_W<'_>

Bit 23 - Set R5VVSINT Interrupt Flag

pub fn em23wakeup(&mut self) -> EM23WAKEUP_W<'_>

Bit 24 - Set EM23WAKEUP Interrupt Flag

pub fn vscaledone(&mut self) -> VSCALEDONE_W<'_>

Bit 25 - Set VSCALEDONE Interrupt Flag

pub fn temp(&mut self) -> TEMP_W<'_>

Bit 29 - Set TEMP Interrupt Flag

pub fn templow(&mut self) -> TEMPLOW_W<'_>

Bit 30 - Set TEMPLOW Interrupt Flag

pub fn temphigh(&mut self) -> TEMPHIGH_W<'_>

Bit 31 - Set TEMPHIGH Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn vmonavddfall(&mut self) -> VMONAVDDFALL_W<'_>

Bit 0 - Clear VMONAVDDFALL Interrupt Flag

pub fn vmonavddrise(&mut self) -> VMONAVDDRISE_W<'_>

Bit 1 - Clear VMONAVDDRISE Interrupt Flag

pub fn vmonaltavddfall(&mut self) -> VMONALTAVDDFALL_W<'_>

Bit 2 - Clear VMONALTAVDDFALL Interrupt Flag

pub fn vmonaltavddrise(&mut self) -> VMONALTAVDDRISE_W<'_>

Bit 3 - Clear VMONALTAVDDRISE Interrupt Flag

pub fn vmondvddfall(&mut self) -> VMONDVDDFALL_W<'_>

Bit 4 - Clear VMONDVDDFALL Interrupt Flag

pub fn vmondvddrise(&mut self) -> VMONDVDDRISE_W<'_>

Bit 5 - Clear VMONDVDDRISE Interrupt Flag

pub fn vmonio0fall(&mut self) -> VMONIO0FALL_W<'_>

Bit 6 - Clear VMONIO0FALL Interrupt Flag

pub fn vmonio0rise(&mut self) -> VMONIO0RISE_W<'_>

Bit 7 - Clear VMONIO0RISE Interrupt Flag

pub fn vmonio1fall(&mut self) -> VMONIO1FALL_W<'_>

Bit 8 - Clear VMONIO1FALL Interrupt Flag

pub fn vmonio1rise(&mut self) -> VMONIO1RISE_W<'_>

Bit 9 - Clear VMONIO1RISE Interrupt Flag

pub fn r5vready(&mut self) -> R5VREADY_W<'_>

Bit 10 - Clear R5VREADY Interrupt Flag

pub fn vmonbuvddfall(&mut self) -> VMONBUVDDFALL_W<'_>

Bit 12 - Clear VMONBUVDDFALL Interrupt Flag

pub fn vmonbuvddrise(&mut self) -> VMONBUVDDRISE_W<'_>

Bit 13 - Clear VMONBUVDDRISE Interrupt Flag

pub fn pfetovercurrentlimit(&mut self) -> PFETOVERCURRENTLIMIT_W<'_>

Bit 16 - Clear PFETOVERCURRENTLIMIT Interrupt Flag

pub fn nfetovercurrentlimit(&mut self) -> NFETOVERCURRENTLIMIT_W<'_>

Bit 17 - Clear NFETOVERCURRENTLIMIT Interrupt Flag

pub fn dcdclprunning(&mut self) -> DCDCLPRUNNING_W<'_>

Bit 18 - Clear DCDCLPRUNNING Interrupt Flag

pub fn dcdclnrunning(&mut self) -> DCDCLNRUNNING_W<'_>

Bit 19 - Clear DCDCLNRUNNING Interrupt Flag

pub fn dcdcinbypass(&mut self) -> DCDCINBYPASS_W<'_>

Bit 20 - Clear DCDCINBYPASS Interrupt Flag

pub fn burdy(&mut self) -> BURDY_W<'_>

Bit 22 - Clear BURDY Interrupt Flag

pub fn r5vvsint(&mut self) -> R5VVSINT_W<'_>

Bit 23 - Clear R5VVSINT Interrupt Flag

pub fn em23wakeup(&mut self) -> EM23WAKEUP_W<'_>

Bit 24 - Clear EM23WAKEUP Interrupt Flag

pub fn vscaledone(&mut self) -> VSCALEDONE_W<'_>

Bit 25 - Clear VSCALEDONE Interrupt Flag

pub fn temp(&mut self) -> TEMP_W<'_>

Bit 29 - Clear TEMP Interrupt Flag

pub fn templow(&mut self) -> TEMPLOW_W<'_>

Bit 30 - Clear TEMPLOW Interrupt Flag

pub fn temphigh(&mut self) -> TEMPHIGH_W<'_>

Bit 31 - Clear TEMPHIGH Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn vmonavddfall(&mut self) -> VMONAVDDFALL_W<'_>

Bit 0 - VMONAVDDFALL Interrupt Enable

pub fn vmonavddrise(&mut self) -> VMONAVDDRISE_W<'_>

Bit 1 - VMONAVDDRISE Interrupt Enable

pub fn vmonaltavddfall(&mut self) -> VMONALTAVDDFALL_W<'_>

Bit 2 - VMONALTAVDDFALL Interrupt Enable

pub fn vmonaltavddrise(&mut self) -> VMONALTAVDDRISE_W<'_>

Bit 3 - VMONALTAVDDRISE Interrupt Enable

pub fn vmondvddfall(&mut self) -> VMONDVDDFALL_W<'_>

Bit 4 - VMONDVDDFALL Interrupt Enable

pub fn vmondvddrise(&mut self) -> VMONDVDDRISE_W<'_>

Bit 5 - VMONDVDDRISE Interrupt Enable

pub fn vmonio0fall(&mut self) -> VMONIO0FALL_W<'_>

Bit 6 - VMONIO0FALL Interrupt Enable

pub fn vmonio0rise(&mut self) -> VMONIO0RISE_W<'_>

Bit 7 - VMONIO0RISE Interrupt Enable

pub fn vmonio1fall(&mut self) -> VMONIO1FALL_W<'_>

Bit 8 - VMONIO1FALL Interrupt Enable

pub fn vmonio1rise(&mut self) -> VMONIO1RISE_W<'_>

Bit 9 - VMONIO1RISE Interrupt Enable

pub fn r5vready(&mut self) -> R5VREADY_W<'_>

Bit 10 - R5VREADY Interrupt Enable

pub fn vmonbuvddfall(&mut self) -> VMONBUVDDFALL_W<'_>

Bit 12 - VMONBUVDDFALL Interrupt Enable

pub fn vmonbuvddrise(&mut self) -> VMONBUVDDRISE_W<'_>

Bit 13 - VMONBUVDDRISE Interrupt Enable

pub fn pfetovercurrentlimit(&mut self) -> PFETOVERCURRENTLIMIT_W<'_>

Bit 16 - PFETOVERCURRENTLIMIT Interrupt Enable

pub fn nfetovercurrentlimit(&mut self) -> NFETOVERCURRENTLIMIT_W<'_>

Bit 17 - NFETOVERCURRENTLIMIT Interrupt Enable

pub fn dcdclprunning(&mut self) -> DCDCLPRUNNING_W<'_>

Bit 18 - DCDCLPRUNNING Interrupt Enable

pub fn dcdclnrunning(&mut self) -> DCDCLNRUNNING_W<'_>

Bit 19 - DCDCLNRUNNING Interrupt Enable

pub fn dcdcinbypass(&mut self) -> DCDCINBYPASS_W<'_>

Bit 20 - DCDCINBYPASS Interrupt Enable

pub fn burdy(&mut self) -> BURDY_W<'_>

Bit 22 - BURDY Interrupt Enable

pub fn r5vvsint(&mut self) -> R5VVSINT_W<'_>

Bit 23 - R5VVSINT Interrupt Enable

pub fn em23wakeup(&mut self) -> EM23WAKEUP_W<'_>

Bit 24 - EM23WAKEUP Interrupt Enable

pub fn vscaledone(&mut self) -> VSCALEDONE_W<'_>

Bit 25 - VSCALEDONE Interrupt Enable

pub fn temp(&mut self) -> TEMP_W<'_>

Bit 29 - TEMP Interrupt Enable

pub fn templow(&mut self) -> TEMPLOW_W<'_>

Bit 30 - TEMPLOW Interrupt Enable

pub fn temphigh(&mut self) -> TEMPHIGH_W<'_>

Bit 31 - TEMPHIGH Interrupt Enable

impl W<u32, Reg<u32, _PWRLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Regulator and Supply Configuration Lock Key

impl W<u32, Reg<u32, _PWRCTRL>>

pub fn anasw(&mut self) -> ANASW_W<'_>

Bit 5 - Analog Switch Selection

pub fn regpwrsel(&mut self) -> REGPWRSEL_W<'_>

Bit 10 - This Field Selects the Input Supply Pin for the Digital LDO

pub fn immediatepwrswitch(&mut self) -> IMMEDIATEPWRSWITCH_W<'_>

Bit 13 - Allows Immediate Switching of ANASW and REGPWRSEL Bitfields

impl W<u32, Reg<u32, _DCDCCTRL>>

pub fn dcdcmode(&mut self) -> DCDCMODE_W<'_>

Bits 0:1 - Regulator Mode

pub fn dcdcmodeem23(&mut self) -> DCDCMODEEM23_W<'_>

Bit 4 - DCDC Mode EM23

pub fn dcdcmodeem4(&mut self) -> DCDCMODEEM4_W<'_>

Bit 5 - DCDC Mode EM4H

impl W<u32, Reg<u32, _DCDCMISCCTRL>>

pub fn lnforceccm(&mut self) -> LNFORCECCM_W<'_>

Bit 0 - Force DCDC Into CCM Mode in Low Noise Operation

pub fn lpcmphysdis(&mut self) -> LPCMPHYSDIS_W<'_>

Bit 1 - Disable LP Mode Hysteresis in the State Machine Control

pub fn lpcmphyshi(&mut self) -> LPCMPHYSHI_W<'_>

Bit 2 - Comparator Threshold on the High Side

pub fn lnforceccmimm(&mut self) -> LNFORCECCMIMM_W<'_>

Bit 5 - Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM

pub fn pfetcnt(&mut self) -> PFETCNT_W<'_>

Bits 8:11 - PFET Switch Number Selection

pub fn nfetcnt(&mut self) -> NFETCNT_W<'_>

Bits 12:15 - NFET Switch Number Selection

pub fn byplimsel(&mut self) -> BYPLIMSEL_W<'_>

Bits 16:19 - Current Limit in Bypass Mode

pub fn lpclimilimsel(&mut self) -> LPCLIMILIMSEL_W<'_>

Bits 20:22 - Current Limit Level Selection for Current Limiter in LP Mode

pub fn lnclimilimsel(&mut self) -> LNCLIMILIMSEL_W<'_>

Bits 24:26 - Current Limit Level Selection for Current Limiter in LN Mode

pub fn lpcmpbiasem234h(&mut self) -> LPCMPBIASEM234H_W<'_>

Bits 28:29 - LP Mode Comparator Bias Selection for EM23 or EM4H

impl W<u32, Reg<u32, _DCDCZDETCTRL>>

pub fn zdetilimsel(&mut self) -> ZDETILIMSEL_W<'_>

Bits 4:6 - Reverse Current Limit Level Selection for Zero Detector

pub fn zdetblankdly(&mut self) -> ZDETBLANKDLY_W<'_>

Bits 8:9 - Reserved for internal use. Do not change.

impl W<u32, Reg<u32, _DCDCCLIMCTRL>>

pub fn climblankdly(&mut self) -> CLIMBLANKDLY_W<'_>

Bits 8:9 - Reserved for internal use. Do not change.

pub fn byplimen(&mut self) -> BYPLIMEN_W<'_>

Bit 13 - Bypass Current Limit Enable

impl W<u32, Reg<u32, _DCDCLNCOMPCTRL>>

pub fn compenr1(&mut self) -> COMPENR1_W<'_>

Bits 0:2 - Low Noise Mode Compensator R1 Trim Value

pub fn compenr2(&mut self) -> COMPENR2_W<'_>

Bits 4:8 - Low Noise Mode Compensator R2 Trim Value

pub fn compenr3(&mut self) -> COMPENR3_W<'_>

Bits 12:15 - Low Noise Mode Compensator R3 Trim Value

pub fn compenc1(&mut self) -> COMPENC1_W<'_>

Bits 20:21 - Low Noise Mode Compensator C1 Trim Value

pub fn compenc2(&mut self) -> COMPENC2_W<'_>

Bits 24:26 - Low Noise Mode Compensator C2 Trim Value

pub fn compenc3(&mut self) -> COMPENC3_W<'_>

Bits 28:31 - Low Noise Mode Compensator C3 Trim Value

impl W<u32, Reg<u32, _DCDCLNVCTRL>>

pub fn lnatt(&mut self) -> LNATT_W<'_>

Bit 1 - Low Noise Mode Feedback Attenuation

pub fn lnvref(&mut self) -> LNVREF_W<'_>

Bits 8:14 - Low Noise Mode VREF Trim

impl W<u32, Reg<u32, _DCDCLPVCTRL>>

pub fn lpatt(&mut self) -> LPATT_W<'_>

Bit 0 - Low Power Feedback Attenuation

pub fn lpvref(&mut self) -> LPVREF_W<'_>

Bits 1:8 - LP Mode Reference Selection for EM23 and EM4H

impl W<u32, Reg<u32, _DCDCLPCTRL>>

pub fn lpcmphysselem234h(&mut self) -> LPCMPHYSSELEM234H_W<'_>

Bits 12:15 - LP Mode Hysteresis Selection for EM23 and EM4H

pub fn lpvrefdutyen(&mut self) -> LPVREFDUTYEN_W<'_>

Bit 24 - LP Mode Duty Cycling Enable

pub fn lpblank(&mut self) -> LPBLANK_W<'_>

Bits 25:26 - Reserved for internal use. Do not change.

impl W<u32, Reg<u32, _DCDCLNFREQCTRL>>

pub fn rcoband(&mut self) -> RCOBAND_W<'_>

Bits 0:2 - LN Mode RCO Frequency Band Selection

pub fn rcotrim(&mut self) -> RCOTRIM_W<'_>

Bits 24:28 - Reserved for internal use. Do not change.

impl W<u32, Reg<u32, _VMONAVDDCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

pub fn risewu(&mut self) -> RISEWU_W<'_>

Bit 2 - Rise Wakeup

pub fn fallwu(&mut self) -> FALLWU_W<'_>

Bit 3 - Fall Wakeup

pub fn fallthresfine(&mut self) -> FALLTHRESFINE_W<'_>

Bits 8:11 - Falling Threshold Fine Adjust

pub fn fallthrescoarse(&mut self) -> FALLTHRESCOARSE_W<'_>

Bits 12:15 - Falling Threshold Coarse Adjust

pub fn risethresfine(&mut self) -> RISETHRESFINE_W<'_>

Bits 16:19 - Rising Threshold Fine Adjust

pub fn risethrescoarse(&mut self) -> RISETHRESCOARSE_W<'_>

Bits 20:23 - Rising Threshold Coarse Adjust

impl W<u32, Reg<u32, _VMONALTAVDDCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

pub fn risewu(&mut self) -> RISEWU_W<'_>

Bit 2 - Rise Wakeup

pub fn fallwu(&mut self) -> FALLWU_W<'_>

Bit 3 - Fall Wakeup

pub fn thresfine(&mut self) -> THRESFINE_W<'_>

Bits 8:11 - Threshold Fine Adjust

pub fn threscoarse(&mut self) -> THRESCOARSE_W<'_>

Bits 12:15 - Threshold Coarse Adjust

impl W<u32, Reg<u32, _VMONDVDDCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

pub fn risewu(&mut self) -> RISEWU_W<'_>

Bit 2 - Rise Wakeup

pub fn fallwu(&mut self) -> FALLWU_W<'_>

Bit 3 - Fall Wakeup

pub fn thresfine(&mut self) -> THRESFINE_W<'_>

Bits 8:11 - Threshold Fine Adjust

pub fn threscoarse(&mut self) -> THRESCOARSE_W<'_>

Bits 12:15 - Threshold Coarse Adjust

impl W<u32, Reg<u32, _VMONIO0CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

pub fn risewu(&mut self) -> RISEWU_W<'_>

Bit 2 - Rise Wakeup

pub fn fallwu(&mut self) -> FALLWU_W<'_>

Bit 3 - Fall Wakeup

pub fn retdis(&mut self) -> RETDIS_W<'_>

Bit 4 - EM4 IO0 Retention Disable

pub fn thresfine(&mut self) -> THRESFINE_W<'_>

Bits 8:11 - Threshold Fine Adjust

pub fn threscoarse(&mut self) -> THRESCOARSE_W<'_>

Bits 12:15 - Threshold Coarse Adjust

impl W<u32, Reg<u32, _VMONIO1CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

pub fn risewu(&mut self) -> RISEWU_W<'_>

Bit 2 - Rise Wakeup

pub fn fallwu(&mut self) -> FALLWU_W<'_>

Bit 3 - Fall Wakeup

pub fn retdis(&mut self) -> RETDIS_W<'_>

Bit 4 - EM4 IO1 Retention Disable

pub fn thresfine(&mut self) -> THRESFINE_W<'_>

Bits 8:11 - Threshold Fine Adjust

pub fn threscoarse(&mut self) -> THRESCOARSE_W<'_>

Bits 12:15 - Threshold Coarse Adjust

impl W<u32, Reg<u32, _VMONBUVDDCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

pub fn risewu(&mut self) -> RISEWU_W<'_>

Bit 2 - Rise Wakeup

pub fn fallwu(&mut self) -> FALLWU_W<'_>

Bit 3 - Fall Wakeup

pub fn thresfine(&mut self) -> THRESFINE_W<'_>

Bits 8:11 - Threshold Fine Adjust

pub fn threscoarse(&mut self) -> THRESCOARSE_W<'_>

Bits 12:15 - Threshold Coarse Adjust

impl W<u32, Reg<u32, _RAM1CTRL>>

pub fn rampowerdown(&mut self) -> RAMPOWERDOWN_W<'_>

Bits 0:7 - RAM1 Blockset Power-down

impl W<u32, Reg<u32, _RAM2CTRL>>

pub fn rampowerdown(&mut self) -> RAMPOWERDOWN_W<'_>

Bits 0:3 - RAM2 Blockset Power-down

impl W<u32, Reg<u32, _BUCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable Backup Mode

pub fn staten(&mut self) -> STATEN_W<'_>

Bit 1 - Enable Backup Mode Status Export

pub fn buvinprobeen(&mut self) -> BUVINPROBEEN_W<'_>

Bit 2 - Enable BU_VIN Probing

pub fn voutres(&mut self) -> VOUTRES_W<'_>

Bits 8:9 - BU_VOUT Resistor Select

pub fn pwrres(&mut self) -> PWRRES_W<'_>

Bits 12:13 - Power Domain Resistor Select

pub fn buactpwrcon(&mut self) -> BUACTPWRCON_W<'_>

Bits 16:17 - Power Connection Configuration in Backup Mode

pub fn buinactpwrcon(&mut self) -> BUINACTPWRCON_W<'_>

Bits 20:21 - Power Connection Configuration When Not in Backup Mode

pub fn dismaxcomp(&mut self) -> DISMAXCOMP_W<'_>

Bit 31 - Disable MAIN-BU Comparator

impl W<u32, Reg<u32, _R5VCTRL>>

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 0 - 5V Regulator Bypass

pub fn em4wuen(&mut self) -> EM4WUEN_W<'_>

Bit 1 - Enable EM4 Wakeup Due to VBUS Detection

pub fn imonen(&mut self) -> IMONEN_W<'_>

Bit 2 - Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS

pub fn inputmode(&mut self) -> INPUTMODE_W<'_>

Bits 8:9 - 5V Input Mode

impl W<u32, Reg<u32, _R5VADCCTRL>>

pub fn enamux(&mut self) -> ENAMUX_W<'_>

Bit 0 - Enable the 5V Subsystem ADC MUX

pub fn amuxsel(&mut self) -> AMUXSEL_W<'_>

Bits 12:15 - ADC Mux Selection

impl W<u32, Reg<u32, _R5VOUTLEVEL>>

pub fn outlevel(&mut self) -> OUTLEVEL_W<'_>

Bits 0:3 - 5V Regulator Voltage

impl W<u32, Reg<u32, _R5VDETCTRL>>

pub fn vregidetdis(&mut self) -> VREGIDETDIS_W<'_>

Bit 0 - VREGI Detector Disable

pub fn vbusdetdis(&mut self) -> VBUSDETDIS_W<'_>

Bit 1 - VBUS Detector Disable

pub fn vregodetdis(&mut self) -> VREGODETDIS_W<'_>

Bit 2 - VREGO Detector Disable

impl W<u32, Reg<u32, _DCDCLPEM01CFG>>

pub fn lpcmpbiasem01(&mut self) -> LPCMPBIASEM01_W<'_>

Bits 8:9 - LP Mode Comparator Bias Selection for EM01

pub fn lpcmphysselem01(&mut self) -> LPCMPHYSSELEM01_W<'_>

Bits 12:15 - LP Mode Hysteresis Selection for EM01

impl W<u32, Reg<u32, _EM23PERNORETAINCMD>>

pub fn acmp0unlock(&mut self) -> ACMP0UNLOCK_W<'_>

Bit 0 - Clears Status Bit of ACMP0 and Unlocks Access to It

pub fn acmp1unlock(&mut self) -> ACMP1UNLOCK_W<'_>

Bit 1 - Clears Status Bit of ACMP1 and Unlocks Access to It

pub fn pcnt0unlock(&mut self) -> PCNT0UNLOCK_W<'_>

Bit 2 - Clears Status Bit of PCNT0 and Unlocks Access to It

pub fn pcnt1unlock(&mut self) -> PCNT1UNLOCK_W<'_>

Bit 3 - Clears Status Bit of PCNT1 and Unlocks Access to It

pub fn pcnt2unlock(&mut self) -> PCNT2UNLOCK_W<'_>

Bit 4 - Clears Status Bit of PCNT2 and Unlocks Access to It

pub fn i2c0unlock(&mut self) -> I2C0UNLOCK_W<'_>

Bit 5 - Clears Status Bit of I2C0 and Unlocks Access to It

pub fn i2c1unlock(&mut self) -> I2C1UNLOCK_W<'_>

Bit 6 - Clears Status Bit of I2C1 and Unlocks Access to It

pub fn dac0unlock(&mut self) -> DAC0UNLOCK_W<'_>

Bit 7 - Clears Status Bit of DAC0 and Unlocks Access to It

pub fn idac0unlock(&mut self) -> IDAC0UNLOCK_W<'_>

Bit 8 - Clears Status Bit of IDAC0 and Unlocks Access to It

pub fn adc0unlock(&mut self) -> ADC0UNLOCK_W<'_>

Bit 9 - Clears Status Bit of ADC0 and Unlocks Access to It

pub fn letimer0unlock(&mut self) -> LETIMER0UNLOCK_W<'_>

Bit 10 - Clears Status Bit of LETIMER0 and Unlocks Access to It

pub fn wdog0unlock(&mut self) -> WDOG0UNLOCK_W<'_>

Bit 11 - Clears Status Bit of WDOG0 and Unlocks Access to It

pub fn wdog1unlock(&mut self) -> WDOG1UNLOCK_W<'_>

Bit 12 - Clears Status Bit of WDOG1 and Unlocks Access to It

pub fn lesense0unlock(&mut self) -> LESENSE0UNLOCK_W<'_>

Bit 13 - Clears Status Bit of LESENSE0 and Unlocks Access to It

pub fn csenunlock(&mut self) -> CSENUNLOCK_W<'_>

Bit 14 - Clears Status Bit of CSEN and Unlocks Access to It

pub fn leuart0unlock(&mut self) -> LEUART0UNLOCK_W<'_>

Bit 15 - Clears Status Bit of LEUART0 and Unlocks Access to It

pub fn leuart1unlock(&mut self) -> LEUART1UNLOCK_W<'_>

Bit 16 - Clears Status Bit of LEUART1 and Unlocks Access to It

pub fn lcdunlock(&mut self) -> LCDUNLOCK_W<'_>

Bit 17 - Clears Status Bit of LCD and Unlocks Access to It

pub fn letimer1unlock(&mut self) -> LETIMER1UNLOCK_W<'_>

Bit 18 - Clears Status Bit of LETIMER1 and Unlocks Access to It

pub fn i2c2unlock(&mut self) -> I2C2UNLOCK_W<'_>

Bit 19 - Clears Status Bit of I2C2 and Unlocks Access to It

pub fn adc1unlock(&mut self) -> ADC1UNLOCK_W<'_>

Bit 20 - Clears Status Bit of ADC1 and Unlocks Access to It

pub fn acmp2unlock(&mut self) -> ACMP2UNLOCK_W<'_>

Bit 21 - Clears Status Bit of ACMP2 and Unlocks Access to It

pub fn acmp3unlock(&mut self) -> ACMP3UNLOCK_W<'_>

Bit 22 - Clears Status Bit of ACMP3 and Unlocks Access to It

pub fn rtcunlock(&mut self) -> RTCUNLOCK_W<'_>

Bit 23 - Clears Status Bit of RTC and Unlocks Access to It

pub fn usbunlock(&mut self) -> USBUNLOCK_W<'_>

Bit 24 - Clears Status Bit of USB and Unlocks Access to It

impl W<u32, Reg<u32, _EM23PERNORETAINCTRL>>

pub fn acmp0dis(&mut self) -> ACMP0DIS_W<'_>

Bit 0 - Allow Power Down of ACMP0 During EM23

pub fn acmp1dis(&mut self) -> ACMP1DIS_W<'_>

Bit 1 - Allow Power Down of ACMP1 During EM23

pub fn pcnt0dis(&mut self) -> PCNT0DIS_W<'_>

Bit 2 - Allow Power Down of PCNT0 During EM23

pub fn pcnt1dis(&mut self) -> PCNT1DIS_W<'_>

Bit 3 - Allow Power Down of PCNT1 During EM23

pub fn pcnt2dis(&mut self) -> PCNT2DIS_W<'_>

Bit 4 - Allow Power Down of PCNT2 During EM23

pub fn i2c0dis(&mut self) -> I2C0DIS_W<'_>

Bit 5 - Allow Power Down of I2C0 During EM23

pub fn i2c1dis(&mut self) -> I2C1DIS_W<'_>

Bit 6 - Allow Power Down of I2C1 During EM23

pub fn vdac0dis(&mut self) -> VDAC0DIS_W<'_>

Bit 7 - Allow Power Down of DAC0 During EM23

pub fn idac0dis(&mut self) -> IDAC0DIS_W<'_>

Bit 8 - Allow Power Down of IDAC0 During EM23

pub fn adc0dis(&mut self) -> ADC0DIS_W<'_>

Bit 9 - Allow Power Down of ADC0 During EM23

pub fn letimer0dis(&mut self) -> LETIMER0DIS_W<'_>

Bit 10 - Allow Power Down of LETIMER0 During EM23

pub fn wdog0dis(&mut self) -> WDOG0DIS_W<'_>

Bit 11 - Allow Power Down of WDOG0 During EM23

pub fn wdog1dis(&mut self) -> WDOG1DIS_W<'_>

Bit 12 - Allow Power Down of WDOG1 During EM23

pub fn lesense0dis(&mut self) -> LESENSE0DIS_W<'_>

Bit 13 - Allow Power Down of LESENSE0 During EM23

pub fn csendis(&mut self) -> CSENDIS_W<'_>

Bit 14 - Allow Power Down of CSEN During EM23

pub fn leuart0dis(&mut self) -> LEUART0DIS_W<'_>

Bit 15 - Allow Power Down of LEUART0 During EM23

pub fn leuart1dis(&mut self) -> LEUART1DIS_W<'_>

Bit 16 - Allow Power Down of LEUART1 During EM23

pub fn lcddis(&mut self) -> LCDDIS_W<'_>

Bit 17 - Allow Power Down of LCD During EM23

pub fn letimer1dis(&mut self) -> LETIMER1DIS_W<'_>

Bit 18 - Allow Power Down of LETIMER1 During EM23

pub fn i2c2dis(&mut self) -> I2C2DIS_W<'_>

Bit 19 - Allow Power Down of I2C2 During EM23

pub fn adc1dis(&mut self) -> ADC1DIS_W<'_>

Bit 20 - Allow Power Down of ADC1 During EM23

pub fn acmp2dis(&mut self) -> ACMP2DIS_W<'_>

Bit 21 - Allow Power Down of ACMP2 During EM23

pub fn acmp3dis(&mut self) -> ACMP3DIS_W<'_>

Bit 22 - Allow Power Down of ACMP3 During EM23

pub fn rtcdis(&mut self) -> RTCDIS_W<'_>

Bit 23 - Allow Power Down of RTC During EM23

pub fn usbdis(&mut self) -> USBDIS_W<'_>

Bit 24 - Allow Power Down of USB During EM23

impl W<u32, Reg<u32, _CTRL>>

pub fn wdogrmode(&mut self) -> WDOGRMODE_W<'_>

Bits 0:2 - WDOG Reset Mode

pub fn lockuprmode(&mut self) -> LOCKUPRMODE_W<'_>

Bits 4:6 - Core LOCKUP Reset Mode

pub fn sysrmode(&mut self) -> SYSRMODE_W<'_>

Bits 8:10 - Core Sysreset Reset Mode

pub fn pinrmode(&mut self) -> PINRMODE_W<'_>

Bits 12:14 - PIN Reset Mode

pub fn resetstate(&mut self) -> RESETSTATE_W<'_>

Bits 24:25 - System Software Reset State

impl W<u32, Reg<u32, _CMD>>

pub fn rcclr(&mut self) -> RCCLR_W<'_>

Bit 0 - Reset Cause Clear

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn clkoutsel0(&mut self) -> CLKOUTSEL0_W<'_>

Bits 0:4 - Clock Output Select 0

pub fn clkoutsel1(&mut self) -> CLKOUTSEL1_W<'_>

Bits 5:9 - Clock Output Select 1

pub fn clkoutsel2(&mut self) -> CLKOUTSEL2_W<'_>

Bits 10:14 - Clock Output Select 2

pub fn wshfle(&mut self) -> WSHFLE_W<'_>

Bit 16 - Wait State for High-Frequency LE Interface

pub fn hfperclken(&mut self) -> HFPERCLKEN_W<'_>

Bit 20 - HFPERCLK Enable

impl W<u32, Reg<u32, _USHFRCOCTRL>>

pub fn tuning(&mut self) -> TUNING_W<'_>

Bits 0:6 - USHFRCO Tuning Value

pub fn finetuning(&mut self) -> FINETUNING_W<'_>

Bits 8:13 - USHFRCO Fine Tuning Value

pub fn freqrange(&mut self) -> FREQRANGE_W<'_>

Bits 16:20 - USHFRCO Frequency Range

pub fn cmpbias(&mut self) -> CMPBIAS_W<'_>

Bits 21:23 - USHFRCO Comparator Bias Current

pub fn ldohp(&mut self) -> LDOHP_W<'_>

Bit 24 - USHFRCO LDO High Power Mode

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 25:26 - Locally Divide USHFRCO Clock Output

pub fn finetuningen(&mut self) -> FINETUNINGEN_W<'_>

Bit 27 - Enable Reference for Fine Tuning

pub fn vreftc(&mut self) -> VREFTC_W<'_>

Bits 28:31 - USHFRCO Temperature Coefficient Trim on Comparator Reference

impl W<u32, Reg<u32, _HFRCOCTRL>>

pub fn tuning(&mut self) -> TUNING_W<'_>

Bits 0:6 - HFRCO Tuning Value

pub fn finetuning(&mut self) -> FINETUNING_W<'_>

Bits 8:13 - HFRCO Fine Tuning Value

pub fn freqrange(&mut self) -> FREQRANGE_W<'_>

Bits 16:20 - HFRCO Frequency Range

pub fn cmpbias(&mut self) -> CMPBIAS_W<'_>

Bits 21:23 - HFRCO Comparator Bias Current

pub fn ldohp(&mut self) -> LDOHP_W<'_>

Bit 24 - HFRCO LDO High Power Mode

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 25:26 - Locally Divide HFRCO Clock Output

pub fn finetuningen(&mut self) -> FINETUNINGEN_W<'_>

Bit 27 - Enable Reference for Fine Tuning

pub fn vreftc(&mut self) -> VREFTC_W<'_>

Bits 28:31 - HFRCO Temperature Coefficient Trim on Comparator Reference

impl W<u32, Reg<u32, _AUXHFRCOCTRL>>

pub fn tuning(&mut self) -> TUNING_W<'_>

Bits 0:6 - AUXHFRCO Tuning Value

pub fn finetuning(&mut self) -> FINETUNING_W<'_>

Bits 8:13 - AUXHFRCO Fine Tuning Value

pub fn freqrange(&mut self) -> FREQRANGE_W<'_>

Bits 16:20 - AUXHFRCO Frequency Range

pub fn cmpbias(&mut self) -> CMPBIAS_W<'_>

Bits 21:23 - AUXHFRCO Comparator Bias Current

pub fn ldohp(&mut self) -> LDOHP_W<'_>

Bit 24 - AUXHFRCO LDO High Power Mode

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 25:26 - Locally Divide AUXHFRCO Clock Output

pub fn finetuningen(&mut self) -> FINETUNINGEN_W<'_>

Bit 27 - Enable Reference for Fine Tuning

pub fn vreftc(&mut self) -> VREFTC_W<'_>

Bits 28:31 - AUXHFRCO Temperature Coefficient Trim on Comparator Reference

impl W<u32, Reg<u32, _LFRCOCTRL>>

pub fn tuning(&mut self) -> TUNING_W<'_>

Bits 0:8 - LFRCO Tuning Value

pub fn envref(&mut self) -> ENVREF_W<'_>

Bit 16 - Enable Duty Cycling of Vref

pub fn enchop(&mut self) -> ENCHOP_W<'_>

Bit 17 - Enable Comparator Chopping

pub fn endem(&mut self) -> ENDEM_W<'_>

Bit 18 - Enable Dynamic Element Matching

pub fn vrefupdate(&mut self) -> VREFUPDATE_W<'_>

Bits 20:21 - Control Vref Update Rate

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bits 24:25 - LFRCO Timeout

pub fn gmccurtune(&mut self) -> GMCCURTUNE_W<'_>

Bits 28:31 - Tuning of Gmc Current

impl W<u32, Reg<u32, _HFXOCTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - HFXO Mode

pub fn hfxox2en(&mut self) -> HFXOX2EN_W<'_>

Bit 3 - Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock)

pub fn peakdetmode(&mut self) -> PEAKDETMODE_W<'_>

Bits 4:5 - HFXO Automatic Peak Detection Mode

pub fn lftimeout(&mut self) -> LFTIMEOUT_W<'_>

Bits 24:26 - HFXO Low Frequency Timeout

pub fn autostartem0em1(&mut self) -> AUTOSTARTEM0EM1_W<'_>

Bit 28 - Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3

pub fn autostartselem0em1(&mut self) -> AUTOSTARTSELEM0EM1_W<'_>

Bit 29 - Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3

impl W<u32, Reg<u32, _HFXOCTRL1>>

pub fn peakdetthr(&mut self) -> PEAKDETTHR_W<'_>

Bits 12:14 - Sets the Amplitude Detection Level (mV)

impl W<u32, Reg<u32, _HFXOSTARTUPCTRL>>

pub fn ibtrimxocore(&mut self) -> IBTRIMXOCORE_W<'_>

Bits 0:10 - Sets the Startup Oscillator Core Bias Current

pub fn ctune(&mut self) -> CTUNE_W<'_>

Bits 11:19 - Sets Oscillator Tuning Capacitance

impl W<u32, Reg<u32, _HFXOSTEADYSTATECTRL>>

pub fn ibtrimxocore(&mut self) -> IBTRIMXOCORE_W<'_>

Bits 0:10 - Sets the Steady State Oscillator Core Bias Current.

pub fn ctune(&mut self) -> CTUNE_W<'_>

Bits 11:19 - Sets Oscillator Tuning Capacitance

pub fn peakdeten(&mut self) -> PEAKDETEN_W<'_>

Bit 26 - Enables Oscillator Peak Detectors

pub fn peakmonen(&mut self) -> PEAKMONEN_W<'_>

Bit 27 - Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO

impl W<u32, Reg<u32, _HFXOTIMEOUTCTRL>>

pub fn startuptimeout(&mut self) -> STARTUPTIMEOUT_W<'_>

Bits 0:3 - Wait Duration in HFXO Startup Enable Wait State

pub fn steadytimeout(&mut self) -> STEADYTIMEOUT_W<'_>

Bits 4:7 - Wait Duration in HFXO Startup Steady Wait State

pub fn peakdettimeout(&mut self) -> PEAKDETTIMEOUT_W<'_>

Bits 12:15 - Wait Duration in HFXO Peak Detection Wait State

impl W<u32, Reg<u32, _LFXOCTRL>>

pub fn tuning(&mut self) -> TUNING_W<'_>

Bits 0:6 - LFXO Internal Capacitor Array Tuning Value

pub fn mode(&mut self) -> MODE_W<'_>

Bits 8:9 - LFXO Mode

pub fn gain(&mut self) -> GAIN_W<'_>

Bits 11:12 - LFXO Startup Gain

pub fn highampl(&mut self) -> HIGHAMPL_W<'_>

Bit 14 - LFXO High XTAL Oscillation Amplitude Enable

pub fn agc(&mut self) -> AGC_W<'_>

Bit 15 - LFXO AGC Enable

pub fn cur(&mut self) -> CUR_W<'_>

Bits 16:17 - LFXO Current Trim

pub fn bufcur(&mut self) -> BUFCUR_W<'_>

Bit 20 - LFXO Buffer Bias Current

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bits 24:26 - LFXO Timeout

impl W<u32, Reg<u32, _DPLLCTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bit 0 - Operating Mode Control

pub fn edgesel(&mut self) -> EDGESEL_W<'_>

Bit 1 - Reference Edge Select

pub fn autorecover(&mut self) -> AUTORECOVER_W<'_>

Bit 2 - Automatic Recovery Ctrl

pub fn refsel(&mut self) -> REFSEL_W<'_>

Bits 3:4 - Reference Clock Selection Control

pub fn dithen(&mut self) -> DITHEN_W<'_>

Bit 6 - Dither Enable Control

impl W<u32, Reg<u32, _DPLLCTRL1>>

pub fn m(&mut self) -> M_W<'_>

Bits 0:11 - Factor M

pub fn n(&mut self) -> N_W<'_>

Bits 16:27 - Factor N

impl W<u32, Reg<u32, _CALCTRL>>

pub fn upsel(&mut self) -> UPSEL_W<'_>

Bits 0:2 - Calibration Up-counter Select

pub fn downsel(&mut self) -> DOWNSEL_W<'_>

Bits 4:7 - Calibration Down-counter Select

pub fn cont(&mut self) -> CONT_W<'_>

Bit 8 - Continuous Calibration

pub fn prsupsel(&mut self) -> PRSUPSEL_W<'_>

Bits 16:20 - PRS Select for PRS Input When Selected in UPSEL

pub fn prsdownsel(&mut self) -> PRSDOWNSEL_W<'_>

Bits 24:28 - PRS Select for PRS Input When Selected in DOWNSEL

impl W<u32, Reg<u32, _CALCNT>>

pub fn calcnt(&mut self) -> CALCNT_W<'_>

Bits 0:19 - Calibration Counter

impl W<u32, Reg<u32, _OSCENCMD>>

pub fn hfrcoen(&mut self) -> HFRCOEN_W<'_>

Bit 0 - HFRCO Enable

pub fn hfrcodis(&mut self) -> HFRCODIS_W<'_>

Bit 1 - HFRCO Disable

pub fn hfxoen(&mut self) -> HFXOEN_W<'_>

Bit 2 - HFXO Enable

pub fn hfxodis(&mut self) -> HFXODIS_W<'_>

Bit 3 - HFXO Disable

pub fn auxhfrcoen(&mut self) -> AUXHFRCOEN_W<'_>

Bit 4 - AUXHFRCO Enable

pub fn auxhfrcodis(&mut self) -> AUXHFRCODIS_W<'_>

Bit 5 - AUXHFRCO Disable

pub fn lfrcoen(&mut self) -> LFRCOEN_W<'_>

Bit 6 - LFRCO Enable

pub fn lfrcodis(&mut self) -> LFRCODIS_W<'_>

Bit 7 - LFRCO Disable

pub fn lfxoen(&mut self) -> LFXOEN_W<'_>

Bit 8 - LFXO Enable

pub fn lfxodis(&mut self) -> LFXODIS_W<'_>

Bit 9 - LFXO Disable

pub fn ushfrcoen(&mut self) -> USHFRCOEN_W<'_>

Bit 10 - USHFRCO Enable

pub fn ushfrcodis(&mut self) -> USHFRCODIS_W<'_>

Bit 11 - USHFRCO Disable

pub fn dpllen(&mut self) -> DPLLEN_W<'_>

Bit 12 - DPLL Enable

pub fn dplldis(&mut self) -> DPLLDIS_W<'_>

Bit 13 - DPLL Disable

impl W<u32, Reg<u32, _CMD>>

pub fn calstart(&mut self) -> CALSTART_W<'_>

Bit 0 - Calibration Start

pub fn calstop(&mut self) -> CALSTOP_W<'_>

Bit 1 - Calibration Stop

pub fn hfxopeakdetstart(&mut self) -> HFXOPEAKDETSTART_W<'_>

Bit 4 - HFXO Peak Detection Start

impl W<u32, Reg<u32, _DBGCLKSEL>>

pub fn dbg(&mut self) -> DBG_W<'_>

Bits 0:1 - Debug Trace Clock

impl W<u32, Reg<u32, _HFCLKSEL>>

pub fn hf(&mut self) -> HF_W<'_>

Bits 0:2 - HFCLK Select

impl W<u32, Reg<u32, _LFACLKSEL>>

pub fn lfa(&mut self) -> LFA_W<'_>

Bits 0:2 - Clock Select for LFA

impl W<u32, Reg<u32, _LFBCLKSEL>>

pub fn lfb(&mut self) -> LFB_W<'_>

Bits 0:2 - Clock Select for LFB

impl W<u32, Reg<u32, _LFECLKSEL>>

pub fn lfe(&mut self) -> LFE_W<'_>

Bits 0:2 - Clock Select for LFE

impl W<u32, Reg<u32, _LFCCLKSEL>>

pub fn lfc(&mut self) -> LFC_W<'_>

Bits 0:2 - Clock Select for LFC

impl W<u32, Reg<u32, _IFS>>

pub fn hfrcordy(&mut self) -> HFRCORDY_W<'_>

Bit 0 - Set HFRCORDY Interrupt Flag

pub fn hfxordy(&mut self) -> HFXORDY_W<'_>

Bit 1 - Set HFXORDY Interrupt Flag

pub fn lfrcordy(&mut self) -> LFRCORDY_W<'_>

Bit 2 - Set LFRCORDY Interrupt Flag

pub fn lfxordy(&mut self) -> LFXORDY_W<'_>

Bit 3 - Set LFXORDY Interrupt Flag

pub fn auxhfrcordy(&mut self) -> AUXHFRCORDY_W<'_>

Bit 4 - Set AUXHFRCORDY Interrupt Flag

pub fn calrdy(&mut self) -> CALRDY_W<'_>

Bit 5 - Set CALRDY Interrupt Flag

pub fn calof(&mut self) -> CALOF_W<'_>

Bit 6 - Set CALOF Interrupt Flag

pub fn ushfrcordy(&mut self) -> USHFRCORDY_W<'_>

Bit 7 - Set USHFRCORDY Interrupt Flag

pub fn hfxodiserr(&mut self) -> HFXODISERR_W<'_>

Bit 8 - Set HFXODISERR Interrupt Flag

pub fn hfxoautosw(&mut self) -> HFXOAUTOSW_W<'_>

Bit 9 - Set HFXOAUTOSW Interrupt Flag

pub fn hfxopeakdetrdy(&mut self) -> HFXOPEAKDETRDY_W<'_>

Bit 11 - Set HFXOPEAKDETRDY Interrupt Flag

pub fn hfrcodis(&mut self) -> HFRCODIS_W<'_>

Bit 13 - Set HFRCODIS Interrupt Flag

pub fn lftimeouterr(&mut self) -> LFTIMEOUTERR_W<'_>

Bit 14 - Set LFTIMEOUTERR Interrupt Flag

pub fn dpllrdy(&mut self) -> DPLLRDY_W<'_>

Bit 15 - Set DPLLRDY Interrupt Flag

pub fn dplllockfaillow(&mut self) -> DPLLLOCKFAILLOW_W<'_>

Bit 16 - Set DPLLLOCKFAILLOW Interrupt Flag

pub fn dplllockfailhigh(&mut self) -> DPLLLOCKFAILHIGH_W<'_>

Bit 17 - Set DPLLLOCKFAILHIGH Interrupt Flag

pub fn lfxoedge(&mut self) -> LFXOEDGE_W<'_>

Bit 27 - Set LFXOEDGE Interrupt Flag

pub fn lfrcoedge(&mut self) -> LFRCOEDGE_W<'_>

Bit 28 - Set LFRCOEDGE Interrupt Flag

pub fn ulfrcoedge(&mut self) -> ULFRCOEDGE_W<'_>

Bit 29 - Set ULFRCOEDGE Interrupt Flag

pub fn cmuerr(&mut self) -> CMUERR_W<'_>

Bit 31 - Set CMUERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn hfrcordy(&mut self) -> HFRCORDY_W<'_>

Bit 0 - Clear HFRCORDY Interrupt Flag

pub fn hfxordy(&mut self) -> HFXORDY_W<'_>

Bit 1 - Clear HFXORDY Interrupt Flag

pub fn lfrcordy(&mut self) -> LFRCORDY_W<'_>

Bit 2 - Clear LFRCORDY Interrupt Flag

pub fn lfxordy(&mut self) -> LFXORDY_W<'_>

Bit 3 - Clear LFXORDY Interrupt Flag

pub fn auxhfrcordy(&mut self) -> AUXHFRCORDY_W<'_>

Bit 4 - Clear AUXHFRCORDY Interrupt Flag

pub fn calrdy(&mut self) -> CALRDY_W<'_>

Bit 5 - Clear CALRDY Interrupt Flag

pub fn calof(&mut self) -> CALOF_W<'_>

Bit 6 - Clear CALOF Interrupt Flag

pub fn ushfrcordy(&mut self) -> USHFRCORDY_W<'_>

Bit 7 - Clear USHFRCORDY Interrupt Flag

pub fn hfxodiserr(&mut self) -> HFXODISERR_W<'_>

Bit 8 - Clear HFXODISERR Interrupt Flag

pub fn hfxoautosw(&mut self) -> HFXOAUTOSW_W<'_>

Bit 9 - Clear HFXOAUTOSW Interrupt Flag

pub fn hfxopeakdetrdy(&mut self) -> HFXOPEAKDETRDY_W<'_>

Bit 11 - Clear HFXOPEAKDETRDY Interrupt Flag

pub fn hfrcodis(&mut self) -> HFRCODIS_W<'_>

Bit 13 - Clear HFRCODIS Interrupt Flag

pub fn lftimeouterr(&mut self) -> LFTIMEOUTERR_W<'_>

Bit 14 - Clear LFTIMEOUTERR Interrupt Flag

pub fn dpllrdy(&mut self) -> DPLLRDY_W<'_>

Bit 15 - Clear DPLLRDY Interrupt Flag

pub fn dplllockfaillow(&mut self) -> DPLLLOCKFAILLOW_W<'_>

Bit 16 - Clear DPLLLOCKFAILLOW Interrupt Flag

pub fn dplllockfailhigh(&mut self) -> DPLLLOCKFAILHIGH_W<'_>

Bit 17 - Clear DPLLLOCKFAILHIGH Interrupt Flag

pub fn lfxoedge(&mut self) -> LFXOEDGE_W<'_>

Bit 27 - Clear LFXOEDGE Interrupt Flag

pub fn lfrcoedge(&mut self) -> LFRCOEDGE_W<'_>

Bit 28 - Clear LFRCOEDGE Interrupt Flag

pub fn ulfrcoedge(&mut self) -> ULFRCOEDGE_W<'_>

Bit 29 - Clear ULFRCOEDGE Interrupt Flag

pub fn cmuerr(&mut self) -> CMUERR_W<'_>

Bit 31 - Clear CMUERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn hfrcordy(&mut self) -> HFRCORDY_W<'_>

Bit 0 - HFRCORDY Interrupt Enable

pub fn hfxordy(&mut self) -> HFXORDY_W<'_>

Bit 1 - HFXORDY Interrupt Enable

pub fn lfrcordy(&mut self) -> LFRCORDY_W<'_>

Bit 2 - LFRCORDY Interrupt Enable

pub fn lfxordy(&mut self) -> LFXORDY_W<'_>

Bit 3 - LFXORDY Interrupt Enable

pub fn auxhfrcordy(&mut self) -> AUXHFRCORDY_W<'_>

Bit 4 - AUXHFRCORDY Interrupt Enable

pub fn calrdy(&mut self) -> CALRDY_W<'_>

Bit 5 - CALRDY Interrupt Enable

pub fn calof(&mut self) -> CALOF_W<'_>

Bit 6 - CALOF Interrupt Enable

pub fn ushfrcordy(&mut self) -> USHFRCORDY_W<'_>

Bit 7 - USHFRCORDY Interrupt Enable

pub fn hfxodiserr(&mut self) -> HFXODISERR_W<'_>

Bit 8 - HFXODISERR Interrupt Enable

pub fn hfxoautosw(&mut self) -> HFXOAUTOSW_W<'_>

Bit 9 - HFXOAUTOSW Interrupt Enable

pub fn hfxopeakdetrdy(&mut self) -> HFXOPEAKDETRDY_W<'_>

Bit 11 - HFXOPEAKDETRDY Interrupt Enable

pub fn hfrcodis(&mut self) -> HFRCODIS_W<'_>

Bit 13 - HFRCODIS Interrupt Enable

pub fn lftimeouterr(&mut self) -> LFTIMEOUTERR_W<'_>

Bit 14 - LFTIMEOUTERR Interrupt Enable

pub fn dpllrdy(&mut self) -> DPLLRDY_W<'_>

Bit 15 - DPLLRDY Interrupt Enable

pub fn dplllockfaillow(&mut self) -> DPLLLOCKFAILLOW_W<'_>

Bit 16 - DPLLLOCKFAILLOW Interrupt Enable

pub fn dplllockfailhigh(&mut self) -> DPLLLOCKFAILHIGH_W<'_>

Bit 17 - DPLLLOCKFAILHIGH Interrupt Enable

pub fn lfxoedge(&mut self) -> LFXOEDGE_W<'_>

Bit 27 - LFXOEDGE Interrupt Enable

pub fn lfrcoedge(&mut self) -> LFRCOEDGE_W<'_>

Bit 28 - LFRCOEDGE Interrupt Enable

pub fn ulfrcoedge(&mut self) -> ULFRCOEDGE_W<'_>

Bit 29 - ULFRCOEDGE Interrupt Enable

pub fn cmuerr(&mut self) -> CMUERR_W<'_>

Bit 31 - CMUERR Interrupt Enable

impl W<u32, Reg<u32, _HFBUSCLKEN0>>

pub fn le(&mut self) -> LE_W<'_>

Bit 0 - Low Energy Peripheral Interface Clock Enable

pub fn crypto0(&mut self) -> CRYPTO0_W<'_>

Bit 1 - Advanced Encryption Standard Accelerator Clock Enable

pub fn ebi(&mut self) -> EBI_W<'_>

Bit 2 - External Bus Interface Clock Enable

pub fn eth(&mut self) -> ETH_W<'_>

Bit 3 - Ethernet Controller Clock Enable

pub fn sdio(&mut self) -> SDIO_W<'_>

Bit 4 - SDIO Controller Clock Enable

pub fn gpio(&mut self) -> GPIO_W<'_>

Bit 5 - General purpose Input/Output Clock Enable

pub fn prs(&mut self) -> PRS_W<'_>

Bit 6 - Peripheral Reflex System Clock Enable

pub fn ldma(&mut self) -> LDMA_W<'_>

Bit 7 - Linked Direct Memory Access Controller Clock Enable

pub fn gpcrc(&mut self) -> GPCRC_W<'_>

Bit 8 - General Purpose CRC Clock Enable

pub fn qspi0(&mut self) -> QSPI0_W<'_>

Bit 9 - Quad-SPI Clock Enable

pub fn usb(&mut self) -> USB_W<'_>

Bit 10 - Universal Serial Bus Interface Clock Enable

impl W<u32, Reg<u32, _HFPERCLKEN0>>

pub fn timer0(&mut self) -> TIMER0_W<'_>

Bit 0 - Timer 0 Clock Enable

pub fn timer1(&mut self) -> TIMER1_W<'_>

Bit 1 - Timer 1 Clock Enable

pub fn timer2(&mut self) -> TIMER2_W<'_>

Bit 2 - Timer 2 Clock Enable

pub fn timer3(&mut self) -> TIMER3_W<'_>

Bit 3 - Timer 3 Clock Enable

pub fn timer4(&mut self) -> TIMER4_W<'_>

Bit 4 - Timer 4 Clock Enable

pub fn timer5(&mut self) -> TIMER5_W<'_>

Bit 5 - Timer 5 Clock Enable

pub fn timer6(&mut self) -> TIMER6_W<'_>

Bit 6 - Timer 6 Clock Enable

pub fn usart0(&mut self) -> USART0_W<'_>

Bit 7 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable

pub fn usart1(&mut self) -> USART1_W<'_>

Bit 8 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable

pub fn usart2(&mut self) -> USART2_W<'_>

Bit 9 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable

pub fn usart3(&mut self) -> USART3_W<'_>

Bit 10 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable

pub fn usart4(&mut self) -> USART4_W<'_>

Bit 11 - Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable

pub fn usart5(&mut self) -> USART5_W<'_>

Bit 12 - Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable

pub fn acmp0(&mut self) -> ACMP0_W<'_>

Bit 13 - Analog Comparator 0 Clock Enable

pub fn acmp1(&mut self) -> ACMP1_W<'_>

Bit 14 - Analog Comparator 1 Clock Enable

pub fn acmp2(&mut self) -> ACMP2_W<'_>

Bit 15 - Analog Comparator 1 Clock Enable

pub fn acmp3(&mut self) -> ACMP3_W<'_>

Bit 16 - Analog Comparator 3 Clock Enable

pub fn i2c0(&mut self) -> I2C0_W<'_>

Bit 17 - I2C 0 Clock Enable

pub fn i2c1(&mut self) -> I2C1_W<'_>

Bit 18 - I2C 1 Clock Enable

pub fn i2c2(&mut self) -> I2C2_W<'_>

Bit 19 - I2C 2 Clock Enable

pub fn adc0(&mut self) -> ADC0_W<'_>

Bit 20 - Analog to Digital Converter 0 Clock Enable

pub fn adc1(&mut self) -> ADC1_W<'_>

Bit 21 - Analog to Digital Converter 0 Clock Enable

pub fn cryotimer(&mut self) -> CRYOTIMER_W<'_>

Bit 22 - CRYOTIMER Clock Enable

pub fn idac0(&mut self) -> IDAC0_W<'_>

Bit 23 - Current Digital to Analog Converter 0 Clock Enable

pub fn trng0(&mut self) -> TRNG0_W<'_>

Bit 24 - True Random Number Generator 0 Clock Enable

impl W<u32, Reg<u32, _HFPERCLKEN1>>

pub fn wtimer0(&mut self) -> WTIMER0_W<'_>

Bit 0 - Wide Timer 0 Clock Enable

pub fn wtimer1(&mut self) -> WTIMER1_W<'_>

Bit 1 - Wide Timer 0 Clock Enable

pub fn wtimer2(&mut self) -> WTIMER2_W<'_>

Bit 2 - Wide Timer 2 Clock Enable

pub fn wtimer3(&mut self) -> WTIMER3_W<'_>

Bit 3 - Wide Timer 3 Clock Enable

pub fn uart0(&mut self) -> UART0_W<'_>

Bit 4 - Universal Asynchronous Receiver/Transmitter 0 Clock Enable

pub fn uart1(&mut self) -> UART1_W<'_>

Bit 5 - Universal Asynchronous Receiver/Transmitter 1 Clock Enable

pub fn can0(&mut self) -> CAN0_W<'_>

Bit 6 - CAN 0 Clock Enable

pub fn can1(&mut self) -> CAN1_W<'_>

Bit 7 - CAN 1 Clock Enable

pub fn vdac0(&mut self) -> VDAC0_W<'_>

Bit 8 - Digital to Analog Converter 0 Clock Enable

pub fn csen(&mut self) -> CSEN_W<'_>

Bit 9 - Capacitive touch sense module Clock Enable

impl W<u32, Reg<u32, _LFACLKEN0>>

pub fn letimer0(&mut self) -> LETIMER0_W<'_>

Bit 0 - Low Energy Timer 0 Clock Enable

pub fn letimer1(&mut self) -> LETIMER1_W<'_>

Bit 1 - Low Energy Timer 1 Clock Enable

pub fn lesense(&mut self) -> LESENSE_W<'_>

Bit 2 - Low Energy Sensor Interface Clock Enable

pub fn lcd(&mut self) -> LCD_W<'_>

Bit 3 - Liquid Crystal Display Controller Clock Enable

pub fn rtc(&mut self) -> RTC_W<'_>

Bit 4 - Real-Time Counter Clock Enable

impl W<u32, Reg<u32, _LFBCLKEN0>>

pub fn leuart0(&mut self) -> LEUART0_W<'_>

Bit 0 - Low Energy UART 0 Clock Enable

pub fn leuart1(&mut self) -> LEUART1_W<'_>

Bit 1 - Low Energy UART 1 Clock Enable

pub fn systick(&mut self) -> SYSTICK_W<'_>

Bit 2 - Clock Enable

pub fn csen(&mut self) -> CSEN_W<'_>

Bit 3 - Capacitive touch sense module Clock Enable

impl W<u32, Reg<u32, _LFCCLKEN0>>

pub fn usb(&mut self) -> USB_W<'_>

Bit 0 - Universal Serial Bus Interface Clock Enable

impl W<u32, Reg<u32, _LFECLKEN0>>

pub fn rtcc(&mut self) -> RTCC_W<'_>

Bit 0 - Real-Time Counter and Calendar Clock Enable

impl W<u32, Reg<u32, _HFPRESC>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:12 - HFCLK Prescaler

pub fn hfclklepresc(&mut self) -> HFCLKLEPRESC_W<'_>

Bits 24:25 - HFCLKLE Prescaler

impl W<u32, Reg<u32, _HFBUSPRESC>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:16 - HFBUSCLK Prescaler

impl W<u32, Reg<u32, _HFCOREPRESC>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:16 - HFCORECLK Prescaler

impl W<u32, Reg<u32, _HFPERPRESC>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:16 - HFPERCLK Prescaler

impl W<u32, Reg<u32, _HFEXPPRESC>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:12 - HFEXPCLK Prescaler

impl W<u32, Reg<u32, _HFPERPRESCB>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:16 - HFPERCLK Prescaler

impl W<u32, Reg<u32, _HFPERPRESCC>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:16 - HFPERCLK Prescaler

impl W<u32, Reg<u32, _LFAPRESC0>>

pub fn letimer0(&mut self) -> LETIMER0_W<'_>

Bits 0:3 - Low Energy Timer 0 Prescaler

pub fn letimer1(&mut self) -> LETIMER1_W<'_>

Bits 4:7 - Low Energy Timer 1 Prescaler

pub fn lesense(&mut self) -> LESENSE_W<'_>

Bits 8:9 - Low Energy Sensor Interface Prescaler

pub fn lcd(&mut self) -> LCD_W<'_>

Bits 12:14 - Liquid Crystal Display Controller Prescaler

pub fn rtc(&mut self) -> RTC_W<'_>

Bits 16:19 - Real-Time Counter Prescaler

impl W<u32, Reg<u32, _LFBPRESC0>>

pub fn leuart0(&mut self) -> LEUART0_W<'_>

Bits 0:1 - Low Energy UART 0 Prescaler

pub fn leuart1(&mut self) -> LEUART1_W<'_>

Bits 4:5 - Low Energy UART 1 Prescaler

pub fn csen(&mut self) -> CSEN_W<'_>

Bits 12:13 - Capacitive touch sense module Prescaler

impl W<u32, Reg<u32, _LFEPRESC0>>

pub fn rtcc(&mut self) -> RTCC_W<'_>

Bits 0:1 - Real-Time Counter and Calendar Prescaler

impl W<u32, Reg<u32, _FREEZE>>

pub fn regfreeze(&mut self) -> REGFREEZE_W<'_>

Bit 0 - Register Update Freeze

impl W<u32, Reg<u32, _PCNTCTRL>>

pub fn pcnt0clken(&mut self) -> PCNT0CLKEN_W<'_>

Bit 0 - PCNT0 Clock Enable

pub fn pcnt0clksel(&mut self) -> PCNT0CLKSEL_W<'_>

Bit 1 - PCNT0 Clock Select

pub fn pcnt1clken(&mut self) -> PCNT1CLKEN_W<'_>

Bit 2 - PCNT1 Clock Enable

pub fn pcnt1clksel(&mut self) -> PCNT1CLKSEL_W<'_>

Bit 3 - PCNT1 Clock Select

pub fn pcnt2clken(&mut self) -> PCNT2CLKEN_W<'_>

Bit 4 - PCNT2 Clock Enable

pub fn pcnt2clksel(&mut self) -> PCNT2CLKSEL_W<'_>

Bit 5 - PCNT2 Clock Select

impl W<u32, Reg<u32, _ADCCTRL>>

pub fn adc0clkdiv(&mut self) -> ADC0CLKDIV_W<'_>

Bits 0:1 - ADC0 Clock Prescaler

pub fn adc0clksel(&mut self) -> ADC0CLKSEL_W<'_>

Bits 4:5 - ADC0 Clock Select

pub fn adc0clkinv(&mut self) -> ADC0CLKINV_W<'_>

Bit 8 - Invert Clock Selected By ADC0CLKSEL

pub fn adc1clkdiv(&mut self) -> ADC1CLKDIV_W<'_>

Bits 16:17 - ADC1 Clock Prescaler

pub fn adc1clksel(&mut self) -> ADC1CLKSEL_W<'_>

Bits 20:21 - ADC1 Clock Select

pub fn adc1clkinv(&mut self) -> ADC1CLKINV_W<'_>

Bit 24 - Invert Clock Selected By ADC1CLKSEL

impl W<u32, Reg<u32, _SDIOCTRL>>

pub fn sdioclksel(&mut self) -> SDIOCLKSEL_W<'_>

Bits 0:1 - SDIO Reference Clock Select

pub fn sdioclkdis(&mut self) -> SDIOCLKDIS_W<'_>

Bit 7 - SDIO Reference Clock Disable

impl W<u32, Reg<u32, _QSPICTRL>>

pub fn qspi0clksel(&mut self) -> QSPI0CLKSEL_W<'_>

Bits 0:1 - QSPI0 Reference Clock Select

pub fn qspi0clkdis(&mut self) -> QSPI0CLKDIS_W<'_>

Bit 7 - QSPI0 Reference Clock Disable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn clkout0pen(&mut self) -> CLKOUT0PEN_W<'_>

Bit 0 - CLKOUT0 Pin Enable

pub fn clkout1pen(&mut self) -> CLKOUT1PEN_W<'_>

Bit 1 - CLKOUT1 Pin Enable

pub fn clkout2pen(&mut self) -> CLKOUT2PEN_W<'_>

Bit 2 - CLKOUT2 Pin Enable

pub fn clkin0pen(&mut self) -> CLKIN0PEN_W<'_>

Bit 28 - CLKIN0 Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn clkout0loc(&mut self) -> CLKOUT0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn clkout1loc(&mut self) -> CLKOUT1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn clkout2loc(&mut self) -> CLKOUT2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn clkin0loc(&mut self) -> CLKIN0LOC_W<'_>

Bits 0:5 - I/O Location

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock Key

impl W<u32, Reg<u32, _HFRCOSS>>

pub fn ssamp(&mut self) -> SSAMP_W<'_>

Bits 0:2 - Spread Spectrum Amplitude

pub fn ssinv(&mut self) -> SSINV_W<'_>

Bits 8:12 - Spread Spectrum Update Interval

impl W<u32, Reg<u32, _USBCTRL>>

pub fn usbclksel(&mut self) -> USBCLKSEL_W<'_>

Bits 0:2 - USB Rate Clock Select

pub fn usbclken(&mut self) -> USBCLKEN_W<'_>

Bit 7 - USB Rate Clock Enable

impl W<u32, Reg<u32, _USBCRCTRL>>

pub fn usbcren(&mut self) -> USBCREN_W<'_>

Bit 0 - Clock Recovery Enable

pub fn usblscrmd(&mut self) -> USBLSCRMD_W<'_>

Bit 1 - Low Speed Clock Recovery Mode

impl W<u32, Reg<u32, _CTRL>>

pub fn aes(&mut self) -> AES_W<'_>

Bit 0 - AES Mode

pub fn keybufdis(&mut self) -> KEYBUFDIS_W<'_>

Bit 1 - Key Buffer Disable

pub fn sha(&mut self) -> SHA_W<'_>

Bit 2 - SHA Mode

pub fn nobusystall(&mut self) -> NOBUSYSTALL_W<'_>

Bit 10 - No Stalling of Bus When Busy

pub fn incwidth(&mut self) -> INCWIDTH_W<'_>

Bits 14:15 - Increment Width

pub fn dma0mode(&mut self) -> DMA0MODE_W<'_>

Bits 16:17 - DMA0 Read Mode

pub fn dma0rsel(&mut self) -> DMA0RSEL_W<'_>

Bits 20:21 - DMA0 Read Register Select

pub fn dma1mode(&mut self) -> DMA1MODE_W<'_>

Bits 24:25 - DMA1 Read Mode

pub fn dma1rsel(&mut self) -> DMA1RSEL_W<'_>

Bits 28:29 - DATA0 DMA Unaligned Read Register Select

pub fn combdma0wereq(&mut self) -> COMBDMA0WEREQ_W<'_>

Bit 31 - Combined Data0 Write DMA Request

impl W<u32, Reg<u32, _WAC>>

pub fn modulus(&mut self) -> MODULUS_W<'_>

Bits 0:3 - Modular Operation Modulus

pub fn modop(&mut self) -> MODOP_W<'_>

Bit 4 - Modular Operation Field Type

pub fn mulwidth(&mut self) -> MULWIDTH_W<'_>

Bits 8:9 - Multiply Width

pub fn resultwidth(&mut self) -> RESULTWIDTH_W<'_>

Bits 10:11 - Result Width

impl W<u32, Reg<u32, _CMD>>

pub fn instr(&mut self) -> INSTR_W<'_>

Bits 0:7 - Execute Instruction

pub fn seqstart(&mut self) -> SEQSTART_W<'_>

Bit 9 - Encryption/Decryption SEQUENCE Start

pub fn seqstop(&mut self) -> SEQSTOP_W<'_>

Bit 10 - Sequence Stop

pub fn seqstep(&mut self) -> SEQSTEP_W<'_>

Bit 11 - Sequence Step

impl W<u32, Reg<u32, _KEY>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - Key Access

impl W<u32, Reg<u32, _KEYBUF>>

pub fn keybuf(&mut self) -> KEYBUF_W<'_>

Bits 0:31 - Key Buffer Access

impl W<u32, Reg<u32, _SEQCTRL>>

pub fn lengtha(&mut self) -> LENGTHA_W<'_>

Bits 0:13 - Buffer Length a in Bytes

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 20:21 - Size of Data Blocks

pub fn dma0skip(&mut self) -> DMA0SKIP_W<'_>

Bits 24:25 - DMA0 Skip

pub fn dma1skip(&mut self) -> DMA1SKIP_W<'_>

Bits 26:27 - DMA1 Skip

pub fn dma0presa(&mut self) -> DMA0PRESA_W<'_>

Bit 28 - DMA0 Preserve a

pub fn dma1presa(&mut self) -> DMA1PRESA_W<'_>

Bit 29 - DMA1 Preserve a

pub fn halt(&mut self) -> HALT_W<'_>

Bit 31 - Halt Sequence

impl W<u32, Reg<u32, _SEQCTRLB>>

pub fn lengthb(&mut self) -> LENGTHB_W<'_>

Bits 0:13 - Buffer Length B in Bytes

pub fn dma0presb(&mut self) -> DMA0PRESB_W<'_>

Bit 28 - DMA0 Preserve B

pub fn dma1presb(&mut self) -> DMA1PRESB_W<'_>

Bit 29 - DMA1 Preserve B

impl W<u32, Reg<u32, _IFS>>

pub fn instrdone(&mut self) -> INSTRDONE_W<'_>

Bit 0 - Set INSTRDONE Interrupt Flag

pub fn seqdone(&mut self) -> SEQDONE_W<'_>

Bit 1 - Set SEQDONE Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn instrdone(&mut self) -> INSTRDONE_W<'_>

Bit 0 - Clear INSTRDONE Interrupt Flag

pub fn seqdone(&mut self) -> SEQDONE_W<'_>

Bit 1 - Clear SEQDONE Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn instrdone(&mut self) -> INSTRDONE_W<'_>

Bit 0 - INSTRDONE Interrupt Enable

pub fn seqdone(&mut self) -> SEQDONE_W<'_>

Bit 1 - SEQDONE Interrupt Enable

impl W<u32, Reg<u32, _SEQ0>>

pub fn instr0(&mut self) -> INSTR0_W<'_>

Bits 0:7 - Sequence Instruction 0

pub fn instr1(&mut self) -> INSTR1_W<'_>

Bits 8:15 - Sequence Instruction 1

pub fn instr2(&mut self) -> INSTR2_W<'_>

Bits 16:23 - Sequence Instruction 2

pub fn instr3(&mut self) -> INSTR3_W<'_>

Bits 24:31 - Sequence Instruction 3

impl W<u32, Reg<u32, _SEQ1>>

pub fn instr4(&mut self) -> INSTR4_W<'_>

Bits 0:7 - Sequence Instruction 4

pub fn instr5(&mut self) -> INSTR5_W<'_>

Bits 8:15 - Sequence Instruction 5

pub fn instr6(&mut self) -> INSTR6_W<'_>

Bits 16:23 - Sequence Instruction 6

pub fn instr7(&mut self) -> INSTR7_W<'_>

Bits 24:31 - Sequence Instruction 7

impl W<u32, Reg<u32, _SEQ2>>

pub fn instr8(&mut self) -> INSTR8_W<'_>

Bits 0:7 - Sequence Instruction 8

pub fn instr9(&mut self) -> INSTR9_W<'_>

Bits 8:15 - Sequence Instruction 9

pub fn instr10(&mut self) -> INSTR10_W<'_>

Bits 16:23 - Sequence Instruction 10

pub fn instr11(&mut self) -> INSTR11_W<'_>

Bits 24:31 - Sequence Instruction 11

impl W<u32, Reg<u32, _SEQ3>>

pub fn instr12(&mut self) -> INSTR12_W<'_>

Bits 0:7 - Sequence Instruction 12

pub fn instr13(&mut self) -> INSTR13_W<'_>

Bits 8:15 - Sequence Instruction 13

pub fn instr14(&mut self) -> INSTR14_W<'_>

Bits 16:23 - Sequence Instruction 14

pub fn instr15(&mut self) -> INSTR15_W<'_>

Bits 24:31 - Sequence Instruction 15

impl W<u32, Reg<u32, _SEQ4>>

pub fn instr16(&mut self) -> INSTR16_W<'_>

Bits 0:7 - Sequence Instruction 16

pub fn instr17(&mut self) -> INSTR17_W<'_>

Bits 8:15 - Sequence Instruction 17

pub fn instr18(&mut self) -> INSTR18_W<'_>

Bits 16:23 - Sequence Instruction 18

pub fn instr19(&mut self) -> INSTR19_W<'_>

Bits 24:31 - Sequence Instruction 19

impl W<u32, Reg<u32, _DATA0>>

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:31 - Data 0 Access

impl W<u32, Reg<u32, _DATA1>>

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 0:31 - Data 1 Access

impl W<u32, Reg<u32, _DATA2>>

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 0:31 - Data 2 Access

impl W<u32, Reg<u32, _DATA3>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 0:31 - Data 3 Access

impl W<u32, Reg<u32, _DATA0XOR>>

pub fn data0xor(&mut self) -> DATA0XOR_W<'_>

Bits 0:31 - XOR Data 0 Access

impl W<u32, Reg<u32, _DATA0BYTE>>

pub fn data0byte(&mut self) -> DATA0BYTE_W<'_>

Bits 0:7 - Data 0 Byte Access

impl W<u32, Reg<u32, _DATA1BYTE>>

pub fn data1byte(&mut self) -> DATA1BYTE_W<'_>

Bits 0:7 - Data 1 Byte Access

impl W<u32, Reg<u32, _DATA0XORBYTE>>

pub fn data0xorbyte(&mut self) -> DATA0XORBYTE_W<'_>

Bits 0:7 - Data 0 XOR Byte Access

impl W<u32, Reg<u32, _DATA0BYTE12>>

pub fn data0byte12(&mut self) -> DATA0BYTE12_W<'_>

Bits 0:7 - Data 0 Byte 12 Access

impl W<u32, Reg<u32, _DATA0BYTE13>>

pub fn data0byte13(&mut self) -> DATA0BYTE13_W<'_>

Bits 0:7 - Data 0 Byte 13 Access

impl W<u32, Reg<u32, _DATA0BYTE14>>

pub fn data0byte14(&mut self) -> DATA0BYTE14_W<'_>

Bits 0:7 - Data 0 Byte 14 Access

impl W<u32, Reg<u32, _DATA0BYTE15>>

pub fn data0byte15(&mut self) -> DATA0BYTE15_W<'_>

Bits 0:7 - Data 0 Byte 15 Access

impl W<u32, Reg<u32, _DDATA0>>

pub fn ddata0(&mut self) -> DDATA0_W<'_>

Bits 0:31 - Double Data 0 Access

impl W<u32, Reg<u32, _DDATA1>>

pub fn ddata1(&mut self) -> DDATA1_W<'_>

Bits 0:31 - Double Data 0 Access

impl W<u32, Reg<u32, _DDATA2>>

pub fn ddata2(&mut self) -> DDATA2_W<'_>

Bits 0:31 - Double Data 0 Access

impl W<u32, Reg<u32, _DDATA3>>

pub fn ddata3(&mut self) -> DDATA3_W<'_>

Bits 0:31 - Double Data 0 Access

impl W<u32, Reg<u32, _DDATA4>>

pub fn ddata4(&mut self) -> DDATA4_W<'_>

Bits 0:31 - Double Data 0 Access

impl W<u32, Reg<u32, _DDATA0BIG>>

pub fn ddata0big(&mut self) -> DDATA0BIG_W<'_>

Bits 0:31 - Double Data 0 Big Endian Access

impl W<u32, Reg<u32, _DDATA0BYTE>>

pub fn ddata0byte(&mut self) -> DDATA0BYTE_W<'_>

Bits 0:7 - Ddata 0 Byte Access

impl W<u32, Reg<u32, _DDATA1BYTE>>

pub fn ddata1byte(&mut self) -> DDATA1BYTE_W<'_>

Bits 0:7 - Ddata 1 Byte Access

impl W<u32, Reg<u32, _DDATA0BYTE32>>

pub fn ddata0byte32(&mut self) -> DDATA0BYTE32_W<'_>

Bits 0:3 - Ddata 0 Byte 32 Access

impl W<u32, Reg<u32, _QDATA0>>

pub fn qdata0(&mut self) -> QDATA0_W<'_>

Bits 0:31 - Quad Data 0 Access

impl W<u32, Reg<u32, _QDATA1>>

pub fn qdata1(&mut self) -> QDATA1_W<'_>

Bits 0:31 - Quad Data 1 Access

impl W<u32, Reg<u32, _QDATA1BIG>>

pub fn qdata1big(&mut self) -> QDATA1BIG_W<'_>

Bits 0:31 - Quad Data 1 Big Endian Access

impl W<u32, Reg<u32, _QDATA0BYTE>>

pub fn qdata0byte(&mut self) -> QDATA0BYTE_W<'_>

Bits 0:7 - Qdata 0 Byte Access

impl W<u32, Reg<u32, _QDATA1BYTE>>

pub fn qdata1byte(&mut self) -> QDATA1BYTE_W<'_>

Bits 0:7 - Qdata 1 Byte Access

impl W<u32, Reg<u32, _CTRL>>

pub fn scanmode(&mut self) -> SCANMODE_W<'_>

Bits 0:1 - Configure Scan Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 2:6 - Scan Start PRS Select

pub fn scanconf(&mut self) -> SCANCONF_W<'_>

Bits 7:8 - Select Scan Configuration

pub fn altexmap(&mut self) -> ALTEXMAP_W<'_>

Bit 11 - Alternative Excitation Map

pub fn dualsample(&mut self) -> DUALSAMPLE_W<'_>

Bit 13 - Enable Dual Sample Mode

pub fn bufow(&mut self) -> BUFOW_W<'_>

Bit 16 - Result Buffer Overwrite

pub fn strscanres(&mut self) -> STRSCANRES_W<'_>

Bit 17 - Enable Storing of SCANRES

pub fn bufidl(&mut self) -> BUFIDL_W<'_>

Bit 19 - Result Buffer Interrupt and DMA Trigger Level

pub fn dmawu(&mut self) -> DMAWU_W<'_>

Bits 20:21 - DMA Wake-up From EM2

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 22 - Debug Mode Run Enable

impl W<u32, Reg<u32, _TIMCTRL>>

pub fn auxpresc(&mut self) -> AUXPRESC_W<'_>

Bits 0:1 - Prescaling Factor for High Frequency Timer

pub fn lfpresc(&mut self) -> LFPRESC_W<'_>

Bits 4:6 - Prescaling Factor for Low Frequency Timer

pub fn pcpresc(&mut self) -> PCPRESC_W<'_>

Bits 8:10 - Period Counter Prescaling

pub fn pctop(&mut self) -> PCTOP_W<'_>

Bits 12:19 - Period Counter Top Value

pub fn startdly(&mut self) -> STARTDLY_W<'_>

Bits 22:23 - Start Delay Configuration

pub fn auxstartup(&mut self) -> AUXSTARTUP_W<'_>

Bit 28 - AUXHFRCO Startup Configuration

impl W<u32, Reg<u32, _PERCTRL>>

pub fn dacch0en(&mut self) -> DACCH0EN_W<'_>

Bit 0 - VDAC CH0 Enable

pub fn dacch1en(&mut self) -> DACCH1EN_W<'_>

Bit 1 - VDAC CH1 Enable

pub fn dacch0data(&mut self) -> DACCH0DATA_W<'_>

Bit 2 - VDAC CH0 Data Selection

pub fn dacch1data(&mut self) -> DACCH1DATA_W<'_>

Bit 3 - VDAC CH1 Data Selection

pub fn dacstartup(&mut self) -> DACSTARTUP_W<'_>

Bit 6 - VDAC Startup Configuration

pub fn dacconvtrig(&mut self) -> DACCONVTRIG_W<'_>

Bit 8 - VDAC Conversion Trigger Configuration

pub fn acmp0mode(&mut self) -> ACMP0MODE_W<'_>

Bits 20:21 - ACMP0 Mode

pub fn acmp1mode(&mut self) -> ACMP1MODE_W<'_>

Bits 22:23 - ACMP1 Mode

pub fn acmp0inv(&mut self) -> ACMP0INV_W<'_>

Bit 24 - Invert Analog Comparator 0 Output

pub fn acmp1inv(&mut self) -> ACMP1INV_W<'_>

Bit 25 - Invert Analog Comparator 1 Output

pub fn acmp0hysten(&mut self) -> ACMP0HYSTEN_W<'_>

Bit 26 - ACMP0 Hysteresis Enable

pub fn acmp1hysten(&mut self) -> ACMP1HYSTEN_W<'_>

Bit 27 - ACMP1 Hysteresis Enable

pub fn warmupmode(&mut self) -> WARMUPMODE_W<'_>

Bits 28:29 - ACMP and VDAC Duty Cycle Mode

impl W<u32, Reg<u32, _DECCTRL>>

pub fn disable(&mut self) -> DISABLE_W<'_>

Bit 0 - Disable the Decoder

pub fn errchk(&mut self) -> ERRCHK_W<'_>

Bit 1 - Enable Check of Current State

pub fn intmap(&mut self) -> INTMAP_W<'_>

Bit 2 - Enable Decoder to Channel Interrupt Mapping

pub fn hystprs0(&mut self) -> HYSTPRS0_W<'_>

Bit 3 - Enable Decoder Hysteresis on PRS0 Output

pub fn hystprs1(&mut self) -> HYSTPRS1_W<'_>

Bit 4 - Enable Decoder Hysteresis on PRS1 Output

pub fn hystprs2(&mut self) -> HYSTPRS2_W<'_>

Bit 5 - Enable Decoder Hysteresis on PRS2 Output

pub fn hystirq(&mut self) -> HYSTIRQ_W<'_>

Bit 6 - Enable Decoder Hysteresis on Interrupt Requests

pub fn prscnt(&mut self) -> PRSCNT_W<'_>

Bit 7 - Enable Count Mode on Decoder PRS Channels 0 and 1

pub fn input(&mut self) -> INPUT_W<'_>

Bit 8 - LESENSE Decoder Input Configuration

pub fn prssel0(&mut self) -> PRSSEL0_W<'_>

Bits 10:14 - LESENSE Decoder PRS Input 0 Configuration

pub fn prssel1(&mut self) -> PRSSEL1_W<'_>

Bits 15:19 - LESENSE Decoder PRS Input 1 Configuration

pub fn prssel2(&mut self) -> PRSSEL2_W<'_>

Bits 20:24 - LESENSE Decoder PRS Input 2 Configuration

pub fn prssel3(&mut self) -> PRSSEL3_W<'_>

Bits 25:29 - LESENSE Decoder PRS Input 3 Configuration

impl W<u32, Reg<u32, _BIASCTRL>>

pub fn biasmode(&mut self) -> BIASMODE_W<'_>

Bits 0:1 - Select Bias Mode

impl W<u32, Reg<u32, _EVALCTRL>>

pub fn winsize(&mut self) -> WINSIZE_W<'_>

Bits 0:15 - Sliding Window and Step Detection Size

impl W<u32, Reg<u32, _PRSCTRL>>

pub fn deccmpval(&mut self) -> DECCMPVAL_W<'_>

Bits 0:4 - Decoder State Compare Value

pub fn deccmpmask(&mut self) -> DECCMPMASK_W<'_>

Bits 8:12 - Decoder State Compare Value Mask

pub fn deccmpen(&mut self) -> DECCMPEN_W<'_>

Bit 16 - Enable PRS Output DECCMP

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Scanning of Sensors

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Scanning of Sensors

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 2 - Start Decoder

pub fn clearbuf(&mut self) -> CLEARBUF_W<'_>

Bit 3 - Clear Result Buffer

impl W<u32, Reg<u32, _CHEN>>

pub fn chen(&mut self) -> CHEN_W<'_>

Bits 0:15 - Enable Scan Channel

impl W<u32, Reg<u32, _SCANRES>>

pub fn scanres(&mut self) -> SCANRES_W<'_>

Bits 0:15 - Scan Results

pub fn stepdir(&mut self) -> STEPDIR_W<'_>

Bits 16:31 - Direction of Previous Step Detection

impl W<u32, Reg<u32, _DECSTATE>>

pub fn decstate(&mut self) -> DECSTATE_W<'_>

Bits 0:4 - Current Decoder State

impl W<u32, Reg<u32, _SENSORSTATE>>

pub fn sensorstate(&mut self) -> SENSORSTATE_W<'_>

Bits 0:3 - Decoder Input Register

impl W<u32, Reg<u32, _IDLECONF>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bits 0:1 - Channel 0 Idle Phase Configuration

pub fn ch1(&mut self) -> CH1_W<'_>

Bits 2:3 - Channel 1 Idle Phase Configuration

pub fn ch2(&mut self) -> CH2_W<'_>

Bits 4:5 - Channel 2 Idle Phase Configuration

pub fn ch3(&mut self) -> CH3_W<'_>

Bits 6:7 - Channel 3 Idle Phase Configuration

pub fn ch4(&mut self) -> CH4_W<'_>

Bits 8:9 - Channel 4 Idle Phase Configuration

pub fn ch5(&mut self) -> CH5_W<'_>

Bits 10:11 - Channel 5 Idle Phase Configuration

pub fn ch6(&mut self) -> CH6_W<'_>

Bits 12:13 - Channel 6 Idle Phase Configuration

pub fn ch7(&mut self) -> CH7_W<'_>

Bits 14:15 - Channel 7 Idle Phase Configuration

pub fn ch8(&mut self) -> CH8_W<'_>

Bits 16:17 - Channel 8 Idle Phase Configuration

pub fn ch9(&mut self) -> CH9_W<'_>

Bits 18:19 - Channel 9 Idle Phase Configuration

pub fn ch10(&mut self) -> CH10_W<'_>

Bits 20:21 - Channel 10 Idle Phase Configuration

pub fn ch11(&mut self) -> CH11_W<'_>

Bits 22:23 - Channel 11 Idle Phase Configuration

pub fn ch12(&mut self) -> CH12_W<'_>

Bits 24:25 - Channel 12 Idle Phase Configuration

pub fn ch13(&mut self) -> CH13_W<'_>

Bits 26:27 - Channel 13 Idle Phase Configuration

pub fn ch14(&mut self) -> CH14_W<'_>

Bits 28:29 - Channel 14 Idle Phase Configuration

pub fn ch15(&mut self) -> CH15_W<'_>

Bits 30:31 - Channel 15 Idle Phase Configuration

impl W<u32, Reg<u32, _ALTEXCONF>>

pub fn idleconf0(&mut self) -> IDLECONF0_W<'_>

Bits 0:1 - ALTEX0 Idle Phase Configuration

pub fn idleconf1(&mut self) -> IDLECONF1_W<'_>

Bits 2:3 - ALTEX1 Idle Phase Configuration

pub fn idleconf2(&mut self) -> IDLECONF2_W<'_>

Bits 4:5 - ALTEX2 Idle Phase Configuration

pub fn idleconf3(&mut self) -> IDLECONF3_W<'_>

Bits 6:7 - ALTEX3 Idle Phase Configuration

pub fn idleconf4(&mut self) -> IDLECONF4_W<'_>

Bits 8:9 - ALTEX4 Idle Phase Configuration

pub fn idleconf5(&mut self) -> IDLECONF5_W<'_>

Bits 10:11 - ALTEX5 Idle Phase Configuration

pub fn idleconf6(&mut self) -> IDLECONF6_W<'_>

Bits 12:13 - ALTEX6 Idle Phase Configuration

pub fn idleconf7(&mut self) -> IDLECONF7_W<'_>

Bits 14:15 - ALTEX7 Idle Phase Configuration

pub fn aex0(&mut self) -> AEX0_W<'_>

Bit 16 - ALTEX0 Always Excite Enable

pub fn aex1(&mut self) -> AEX1_W<'_>

Bit 17 - ALTEX1 Always Excite Enable

pub fn aex2(&mut self) -> AEX2_W<'_>

Bit 18 - ALTEX2 Always Excite Enable

pub fn aex3(&mut self) -> AEX3_W<'_>

Bit 19 - ALTEX3 Always Excite Enable

pub fn aex4(&mut self) -> AEX4_W<'_>

Bit 20 - ALTEX4 Always Excite Enable

pub fn aex5(&mut self) -> AEX5_W<'_>

Bit 21 - ALTEX5 Always Excite Enable

pub fn aex6(&mut self) -> AEX6_W<'_>

Bit 22 - ALTEX6 Always Excite Enable

pub fn aex7(&mut self) -> AEX7_W<'_>

Bit 23 - ALTEX7 Always Excite Enable

impl W<u32, Reg<u32, _IFS>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Set CH0 Interrupt Flag

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Set CH1 Interrupt Flag

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Set CH2 Interrupt Flag

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Set CH3 Interrupt Flag

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Set CH4 Interrupt Flag

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Set CH5 Interrupt Flag

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Set CH6 Interrupt Flag

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Set CH7 Interrupt Flag

pub fn ch8(&mut self) -> CH8_W<'_>

Bit 8 - Set CH8 Interrupt Flag

pub fn ch9(&mut self) -> CH9_W<'_>

Bit 9 - Set CH9 Interrupt Flag

pub fn ch10(&mut self) -> CH10_W<'_>

Bit 10 - Set CH10 Interrupt Flag

pub fn ch11(&mut self) -> CH11_W<'_>

Bit 11 - Set CH11 Interrupt Flag

pub fn ch12(&mut self) -> CH12_W<'_>

Bit 12 - Set CH12 Interrupt Flag

pub fn ch13(&mut self) -> CH13_W<'_>

Bit 13 - Set CH13 Interrupt Flag

pub fn ch14(&mut self) -> CH14_W<'_>

Bit 14 - Set CH14 Interrupt Flag

pub fn ch15(&mut self) -> CH15_W<'_>

Bit 15 - Set CH15 Interrupt Flag

pub fn scancomplete(&mut self) -> SCANCOMPLETE_W<'_>

Bit 16 - Set SCANCOMPLETE Interrupt Flag

pub fn dec(&mut self) -> DEC_W<'_>

Bit 17 - Set DEC Interrupt Flag

pub fn decerr(&mut self) -> DECERR_W<'_>

Bit 18 - Set DECERR Interrupt Flag

pub fn bufdatav(&mut self) -> BUFDATAV_W<'_>

Bit 19 - Set BUFDATAV Interrupt Flag

pub fn buflevel(&mut self) -> BUFLEVEL_W<'_>

Bit 20 - Set BUFLEVEL Interrupt Flag

pub fn bufof(&mut self) -> BUFOF_W<'_>

Bit 21 - Set BUFOF Interrupt Flag

pub fn cntof(&mut self) -> CNTOF_W<'_>

Bit 22 - Set CNTOF Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Clear CH0 Interrupt Flag

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Clear CH1 Interrupt Flag

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Clear CH2 Interrupt Flag

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Clear CH3 Interrupt Flag

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Clear CH4 Interrupt Flag

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Clear CH5 Interrupt Flag

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Clear CH6 Interrupt Flag

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Clear CH7 Interrupt Flag

pub fn ch8(&mut self) -> CH8_W<'_>

Bit 8 - Clear CH8 Interrupt Flag

pub fn ch9(&mut self) -> CH9_W<'_>

Bit 9 - Clear CH9 Interrupt Flag

pub fn ch10(&mut self) -> CH10_W<'_>

Bit 10 - Clear CH10 Interrupt Flag

pub fn ch11(&mut self) -> CH11_W<'_>

Bit 11 - Clear CH11 Interrupt Flag

pub fn ch12(&mut self) -> CH12_W<'_>

Bit 12 - Clear CH12 Interrupt Flag

pub fn ch13(&mut self) -> CH13_W<'_>

Bit 13 - Clear CH13 Interrupt Flag

pub fn ch14(&mut self) -> CH14_W<'_>

Bit 14 - Clear CH14 Interrupt Flag

pub fn ch15(&mut self) -> CH15_W<'_>

Bit 15 - Clear CH15 Interrupt Flag

pub fn scancomplete(&mut self) -> SCANCOMPLETE_W<'_>

Bit 16 - Clear SCANCOMPLETE Interrupt Flag

pub fn dec(&mut self) -> DEC_W<'_>

Bit 17 - Clear DEC Interrupt Flag

pub fn decerr(&mut self) -> DECERR_W<'_>

Bit 18 - Clear DECERR Interrupt Flag

pub fn bufdatav(&mut self) -> BUFDATAV_W<'_>

Bit 19 - Clear BUFDATAV Interrupt Flag

pub fn buflevel(&mut self) -> BUFLEVEL_W<'_>

Bit 20 - Clear BUFLEVEL Interrupt Flag

pub fn bufof(&mut self) -> BUFOF_W<'_>

Bit 21 - Clear BUFOF Interrupt Flag

pub fn cntof(&mut self) -> CNTOF_W<'_>

Bit 22 - Clear CNTOF Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - CH0 Interrupt Enable

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - CH1 Interrupt Enable

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - CH2 Interrupt Enable

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - CH3 Interrupt Enable

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - CH4 Interrupt Enable

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - CH5 Interrupt Enable

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - CH6 Interrupt Enable

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - CH7 Interrupt Enable

pub fn ch8(&mut self) -> CH8_W<'_>

Bit 8 - CH8 Interrupt Enable

pub fn ch9(&mut self) -> CH9_W<'_>

Bit 9 - CH9 Interrupt Enable

pub fn ch10(&mut self) -> CH10_W<'_>

Bit 10 - CH10 Interrupt Enable

pub fn ch11(&mut self) -> CH11_W<'_>

Bit 11 - CH11 Interrupt Enable

pub fn ch12(&mut self) -> CH12_W<'_>

Bit 12 - CH12 Interrupt Enable

pub fn ch13(&mut self) -> CH13_W<'_>

Bit 13 - CH13 Interrupt Enable

pub fn ch14(&mut self) -> CH14_W<'_>

Bit 14 - CH14 Interrupt Enable

pub fn ch15(&mut self) -> CH15_W<'_>

Bit 15 - CH15 Interrupt Enable

pub fn scancomplete(&mut self) -> SCANCOMPLETE_W<'_>

Bit 16 - SCANCOMPLETE Interrupt Enable

pub fn dec(&mut self) -> DEC_W<'_>

Bit 17 - DEC Interrupt Enable

pub fn decerr(&mut self) -> DECERR_W<'_>

Bit 18 - DECERR Interrupt Enable

pub fn bufdatav(&mut self) -> BUFDATAV_W<'_>

Bit 19 - BUFDATAV Interrupt Enable

pub fn buflevel(&mut self) -> BUFLEVEL_W<'_>

Bit 20 - BUFLEVEL Interrupt Enable

pub fn bufof(&mut self) -> BUFOF_W<'_>

Bit 21 - BUFOF Interrupt Enable

pub fn cntof(&mut self) -> CNTOF_W<'_>

Bit 22 - CNTOF Interrupt Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn ch0pen(&mut self) -> CH0PEN_W<'_>

Bit 0 - CH0 Pin Enable

pub fn ch1pen(&mut self) -> CH1PEN_W<'_>

Bit 1 - CH1 Pin Enable

pub fn ch2pen(&mut self) -> CH2PEN_W<'_>

Bit 2 - CH2 Pin Enable

pub fn ch3pen(&mut self) -> CH3PEN_W<'_>

Bit 3 - CH3 Pin Enable

pub fn ch4pen(&mut self) -> CH4PEN_W<'_>

Bit 4 - CH4 Pin Enable

pub fn ch5pen(&mut self) -> CH5PEN_W<'_>

Bit 5 - CH5 Pin Enable

pub fn ch6pen(&mut self) -> CH6PEN_W<'_>

Bit 6 - CH6 Pin Enable

pub fn ch7pen(&mut self) -> CH7PEN_W<'_>

Bit 7 - CH7 Pin Enable

pub fn ch8pen(&mut self) -> CH8PEN_W<'_>

Bit 8 - CH8 Pin Enable

pub fn ch9pen(&mut self) -> CH9PEN_W<'_>

Bit 9 - CH9 Pin Enable

pub fn ch10pen(&mut self) -> CH10PEN_W<'_>

Bit 10 - CH10 Pin Enable

pub fn ch11pen(&mut self) -> CH11PEN_W<'_>

Bit 11 - CH11 Pin Enable

pub fn ch12pen(&mut self) -> CH12PEN_W<'_>

Bit 12 - CH12 Pin Enable

pub fn ch13pen(&mut self) -> CH13PEN_W<'_>

Bit 13 - CH13 Pin Enable

pub fn ch14pen(&mut self) -> CH14PEN_W<'_>

Bit 14 - CH14 Pin Enable

pub fn ch15pen(&mut self) -> CH15PEN_W<'_>

Bit 15 - CH15 Pin Enable

pub fn altex0pen(&mut self) -> ALTEX0PEN_W<'_>

Bit 16 - ALTEX0 Pin Enable

pub fn altex1pen(&mut self) -> ALTEX1PEN_W<'_>

Bit 17 - ALTEX1 Pin Enable

pub fn altex2pen(&mut self) -> ALTEX2PEN_W<'_>

Bit 18 - ALTEX2 Pin Enable

pub fn altex3pen(&mut self) -> ALTEX3PEN_W<'_>

Bit 19 - ALTEX3 Pin Enable

pub fn altex4pen(&mut self) -> ALTEX4PEN_W<'_>

Bit 20 - ALTEX4 Pin Enable

pub fn altex5pen(&mut self) -> ALTEX5PEN_W<'_>

Bit 21 - ALTEX5 Pin Enable

pub fn altex6pen(&mut self) -> ALTEX6PEN_W<'_>

Bit 22 - ALTEX6 Pin Enable

pub fn altex7pen(&mut self) -> ALTEX7PEN_W<'_>

Bit 23 - ALTEX7 Pin Enable

impl W<u32, Reg<u32, _ST0_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST0_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST1_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST1_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST2_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST2_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST3_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST3_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST4_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST4_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST5_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST5_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST6_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST6_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST7_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST7_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST8_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST8_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST9_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST9_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST10_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST10_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST11_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST11_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST12_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST12_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST13_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST13_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST14_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST14_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST15_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST15_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST16_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST16_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST17_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST17_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST18_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST18_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST19_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST19_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST20_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST20_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST21_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST21_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST22_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST22_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST23_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST23_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST24_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST24_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST25_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST25_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST26_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST26_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST27_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST27_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST28_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST28_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST29_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST29_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST30_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST30_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST31_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST31_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _BUF0_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF1_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF2_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF3_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF4_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF5_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF6_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF7_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF8_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF9_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF10_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF11_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF12_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF13_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF14_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF15_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _CH0_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH0_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH0_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH1_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH1_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH1_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH2_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH2_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH2_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH3_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH3_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH3_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH4_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH4_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH4_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH5_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH5_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH5_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH6_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH6_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH6_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH7_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH7_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH7_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH8_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH8_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH8_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH9_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH9_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH9_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH10_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH10_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH10_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH11_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH11_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH11_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH12_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH12_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH12_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH13_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH13_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH13_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH14_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH14_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH14_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH15_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH15_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH15_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 2:3 - Mode 1

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 4:5 - Mode 2

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 6:7 - Mode 3

pub fn bank0en(&mut self) -> BANK0EN_W<'_>

Bit 8 - Bank 0 Enable

pub fn bank1en(&mut self) -> BANK1EN_W<'_>

Bit 9 - Bank 1 Enable

pub fn bank2en(&mut self) -> BANK2EN_W<'_>

Bit 10 - Bank 2 Enable

pub fn bank3en(&mut self) -> BANK3EN_W<'_>

Bit 11 - Bank 3 Enable

pub fn noidle(&mut self) -> NOIDLE_W<'_>

Bit 12 - No Idle Cycle Insertion on Bank 0

pub fn noidle1(&mut self) -> NOIDLE1_W<'_>

Bit 13 - No Idle Cycle Insertion on Bank 1

pub fn noidle2(&mut self) -> NOIDLE2_W<'_>

Bit 14 - No Idle Cycle Insertion on Bank 2

pub fn noidle3(&mut self) -> NOIDLE3_W<'_>

Bit 15 - No Idle Cycle Insertion on Bank 3

pub fn ardyen(&mut self) -> ARDYEN_W<'_>

Bit 16 - ARDY Enable

pub fn ardytodis(&mut self) -> ARDYTODIS_W<'_>

Bit 17 - ARDY Timeout Disable

pub fn ardy1en(&mut self) -> ARDY1EN_W<'_>

Bit 18 - ARDY Enable for Bank 1

pub fn ardyto1dis(&mut self) -> ARDYTO1DIS_W<'_>

Bit 19 - ARDY Timeout Disable for Bank 1

pub fn ardy2en(&mut self) -> ARDY2EN_W<'_>

Bit 20 - ARDY Enable for Bank 2

pub fn ardyto2dis(&mut self) -> ARDYTO2DIS_W<'_>

Bit 21 - ARDY Timeout Disable for Bank 2

pub fn ardy3en(&mut self) -> ARDY3EN_W<'_>

Bit 22 - ARDY Enable for Bank 3

pub fn ardyto3dis(&mut self) -> ARDYTO3DIS_W<'_>

Bit 23 - ARDY Timeout Disable for Bank 3

pub fn bl(&mut self) -> BL_W<'_>

Bit 24 - Byte Lane Enable for Bank 0

pub fn bl1(&mut self) -> BL1_W<'_>

Bit 25 - Byte Lane Enable for Bank 1

pub fn bl2(&mut self) -> BL2_W<'_>

Bit 26 - Byte Lane Enable for Bank 2

pub fn bl3(&mut self) -> BL3_W<'_>

Bit 27 - Byte Lane Enable for Bank 3

pub fn its(&mut self) -> ITS_W<'_>

Bit 30 - Individual Timing Set, Line Polarity and Mode Definition Enable

pub fn altmap(&mut self) -> ALTMAP_W<'_>

Bit 31 - Alternative Address Map Enable

impl W<u32, Reg<u32, _ADDRTIMING>>

pub fn addrsetup(&mut self) -> ADDRSETUP_W<'_>

Bits 0:2 - Address Setup Time

pub fn addrhold(&mut self) -> ADDRHOLD_W<'_>

Bits 8:10 - Address Hold Time

pub fn halfale(&mut self) -> HALFALE_W<'_>

Bit 28 - Half Cycle ALE Strobe Duration Enable

impl W<u32, Reg<u32, _RDTIMING>>

pub fn rdsetup(&mut self) -> RDSETUP_W<'_>

Bits 0:2 - Read Setup Time

pub fn rdstrb(&mut self) -> RDSTRB_W<'_>

Bits 8:14 - Read Strobe Time

pub fn rdhold(&mut self) -> RDHOLD_W<'_>

Bits 16:18 - Read Hold Time

pub fn halfre(&mut self) -> HALFRE_W<'_>

Bit 28 - Half Cycle REn Strobe Duration Enable

pub fn prefetch(&mut self) -> PREFETCH_W<'_>

Bit 29 - Prefetch Enable

pub fn pagemode(&mut self) -> PAGEMODE_W<'_>

Bit 30 - Page Mode Access Enable

impl W<u32, Reg<u32, _WRTIMING>>

pub fn wrsetup(&mut self) -> WRSETUP_W<'_>

Bits 0:2 - Write Setup Time

pub fn wrstrb(&mut self) -> WRSTRB_W<'_>

Bits 8:14 - Write Strobe Time

pub fn wrhold(&mut self) -> WRHOLD_W<'_>

Bits 16:18 - Write Hold Time

pub fn halfwe(&mut self) -> HALFWE_W<'_>

Bit 28 - Half Cycle WEn Strobe Duration Enable

pub fn wbufdis(&mut self) -> WBUFDIS_W<'_>

Bit 29 - Write Buffer Disable

impl W<u32, Reg<u32, _POLARITY>>

pub fn cspol(&mut self) -> CSPOL_W<'_>

Bit 0 - Chip Select Polarity

pub fn repol(&mut self) -> REPOL_W<'_>

Bit 1 - Read Enable Polarity

pub fn wepol(&mut self) -> WEPOL_W<'_>

Bit 2 - Write Enable Polarity

pub fn alepol(&mut self) -> ALEPOL_W<'_>

Bit 3 - Address Latch Polarity

pub fn ardypol(&mut self) -> ARDYPOL_W<'_>

Bit 4 - ARDY Polarity

pub fn blpol(&mut self) -> BLPOL_W<'_>

Bit 5 - BL Polarity

impl W<u32, Reg<u32, _ADDRTIMING1>>

pub fn addrsetup(&mut self) -> ADDRSETUP_W<'_>

Bits 0:2 - Address Setup Time

pub fn addrhold(&mut self) -> ADDRHOLD_W<'_>

Bits 8:10 - Address Hold Time

pub fn halfale(&mut self) -> HALFALE_W<'_>

Bit 28 - Half Cycle ALE Strobe Duration Enable

impl W<u32, Reg<u32, _RDTIMING1>>

pub fn rdsetup(&mut self) -> RDSETUP_W<'_>

Bits 0:2 - Read Setup Time

pub fn rdstrb(&mut self) -> RDSTRB_W<'_>

Bits 8:14 - Read Strobe Time

pub fn rdhold(&mut self) -> RDHOLD_W<'_>

Bits 16:18 - Read Hold Time

pub fn halfre(&mut self) -> HALFRE_W<'_>

Bit 28 - Half Cycle REn Strobe Duration Enable

pub fn prefetch(&mut self) -> PREFETCH_W<'_>

Bit 29 - Prefetch Enable

pub fn pagemode(&mut self) -> PAGEMODE_W<'_>

Bit 30 - Page Mode Access Enable

impl W<u32, Reg<u32, _WRTIMING1>>

pub fn wrsetup(&mut self) -> WRSETUP_W<'_>

Bits 0:2 - Write Setup Time

pub fn wrstrb(&mut self) -> WRSTRB_W<'_>

Bits 8:14 - Write Strobe Time

pub fn wrhold(&mut self) -> WRHOLD_W<'_>

Bits 16:18 - Write Hold Time

pub fn halfwe(&mut self) -> HALFWE_W<'_>

Bit 28 - Half Cycle WEn Strobe Duration Enable

pub fn wbufdis(&mut self) -> WBUFDIS_W<'_>

Bit 29 - Write Buffer Disable

impl W<u32, Reg<u32, _POLARITY1>>

pub fn cspol(&mut self) -> CSPOL_W<'_>

Bit 0 - Chip Select Polarity

pub fn repol(&mut self) -> REPOL_W<'_>

Bit 1 - Read Enable Polarity

pub fn wepol(&mut self) -> WEPOL_W<'_>

Bit 2 - Write Enable Polarity

pub fn alepol(&mut self) -> ALEPOL_W<'_>

Bit 3 - Address Latch Polarity

pub fn ardypol(&mut self) -> ARDYPOL_W<'_>

Bit 4 - ARDY Polarity

pub fn blpol(&mut self) -> BLPOL_W<'_>

Bit 5 - BL Polarity

impl W<u32, Reg<u32, _ADDRTIMING2>>

pub fn addrsetup(&mut self) -> ADDRSETUP_W<'_>

Bits 0:2 - Address Setup Time

pub fn addrhold(&mut self) -> ADDRHOLD_W<'_>

Bits 8:10 - Address Hold Time

pub fn halfale(&mut self) -> HALFALE_W<'_>

Bit 28 - Half Cycle ALE Strobe Duration Enable

impl W<u32, Reg<u32, _RDTIMING2>>

pub fn rdsetup(&mut self) -> RDSETUP_W<'_>

Bits 0:2 - Read Setup Time

pub fn rdstrb(&mut self) -> RDSTRB_W<'_>

Bits 8:14 - Read Strobe Time

pub fn rdhold(&mut self) -> RDHOLD_W<'_>

Bits 16:18 - Read Hold Time

pub fn halfre(&mut self) -> HALFRE_W<'_>

Bit 28 - Half Cycle REn Strobe Duration Enable

pub fn prefetch(&mut self) -> PREFETCH_W<'_>

Bit 29 - Prefetch Enable

pub fn pagemode(&mut self) -> PAGEMODE_W<'_>

Bit 30 - Page Mode Access Enable

impl W<u32, Reg<u32, _WRTIMING2>>

pub fn wrsetup(&mut self) -> WRSETUP_W<'_>

Bits 0:2 - Write Setup Time

pub fn wrstrb(&mut self) -> WRSTRB_W<'_>

Bits 8:14 - Write Strobe Time

pub fn wrhold(&mut self) -> WRHOLD_W<'_>

Bits 16:18 - Write Hold Time

pub fn halfwe(&mut self) -> HALFWE_W<'_>

Bit 28 - Half Cycle WEn Strobe Duration Enable

pub fn wbufdis(&mut self) -> WBUFDIS_W<'_>

Bit 29 - Write Buffer Disable

impl W<u32, Reg<u32, _POLARITY2>>

pub fn cspol(&mut self) -> CSPOL_W<'_>

Bit 0 - Chip Select Polarity

pub fn repol(&mut self) -> REPOL_W<'_>

Bit 1 - Read Enable Polarity

pub fn wepol(&mut self) -> WEPOL_W<'_>

Bit 2 - Write Enable Polarity

pub fn alepol(&mut self) -> ALEPOL_W<'_>

Bit 3 - Address Latch Polarity

pub fn ardypol(&mut self) -> ARDYPOL_W<'_>

Bit 4 - ARDY Polarity

pub fn blpol(&mut self) -> BLPOL_W<'_>

Bit 5 - BL Polarity

impl W<u32, Reg<u32, _ADDRTIMING3>>

pub fn addrsetup(&mut self) -> ADDRSETUP_W<'_>

Bits 0:2 - Address Setup Time

pub fn addrhold(&mut self) -> ADDRHOLD_W<'_>

Bits 8:10 - Address Hold Time

pub fn halfale(&mut self) -> HALFALE_W<'_>

Bit 28 - Half Cycle ALE Strobe Duration Enable

impl W<u32, Reg<u32, _RDTIMING3>>

pub fn rdsetup(&mut self) -> RDSETUP_W<'_>

Bits 0:2 - Read Setup Time

pub fn rdstrb(&mut self) -> RDSTRB_W<'_>

Bits 8:14 - Read Strobe Time

pub fn rdhold(&mut self) -> RDHOLD_W<'_>

Bits 16:18 - Read Hold Time

pub fn halfre(&mut self) -> HALFRE_W<'_>

Bit 28 - Half Cycle REn Strobe Duration Enable

pub fn prefetch(&mut self) -> PREFETCH_W<'_>

Bit 29 - Prefetch Enable

pub fn pagemode(&mut self) -> PAGEMODE_W<'_>

Bit 30 - Page Mode Access Enable

impl W<u32, Reg<u32, _WRTIMING3>>

pub fn wrsetup(&mut self) -> WRSETUP_W<'_>

Bits 0:2 - Write Setup Time

pub fn wrstrb(&mut self) -> WRSTRB_W<'_>

Bits 8:14 - Write Strobe Time

pub fn wrhold(&mut self) -> WRHOLD_W<'_>

Bits 16:18 - Write Hold Time

pub fn halfwe(&mut self) -> HALFWE_W<'_>

Bit 28 - Half Cycle WEn Strobe Duration Enable

pub fn wbufdis(&mut self) -> WBUFDIS_W<'_>

Bit 29 - Write Buffer Disable

impl W<u32, Reg<u32, _POLARITY3>>

pub fn cspol(&mut self) -> CSPOL_W<'_>

Bit 0 - Chip Select Polarity

pub fn repol(&mut self) -> REPOL_W<'_>

Bit 1 - Read Enable Polarity

pub fn wepol(&mut self) -> WEPOL_W<'_>

Bit 2 - Write Enable Polarity

pub fn alepol(&mut self) -> ALEPOL_W<'_>

Bit 3 - Address Latch Polarity

pub fn ardypol(&mut self) -> ARDYPOL_W<'_>

Bit 4 - ARDY Polarity

pub fn blpol(&mut self) -> BLPOL_W<'_>

Bit 5 - BL Polarity

impl W<u32, Reg<u32, _PAGECTRL>>

pub fn pagelen(&mut self) -> PAGELEN_W<'_>

Bits 0:1 - Page Length

pub fn inchit(&mut self) -> INCHIT_W<'_>

Bit 4 - Intrapage Hit Only on Incremental Addresses

pub fn rdpa(&mut self) -> RDPA_W<'_>

Bits 8:11 - Page Read Access Time

pub fn keepopen(&mut self) -> KEEPOPEN_W<'_>

Bits 20:26 - Maximum Page Open Time

impl W<u32, Reg<u32, _NANDCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - NAND Flash Control Enable

pub fn banksel(&mut self) -> BANKSEL_W<'_>

Bits 4:5 - NAND Flash Bank

impl W<u32, Reg<u32, _CMD>>

pub fn eccstart(&mut self) -> ECCSTART_W<'_>

Bit 0 - Error Correction Code Generation Start

pub fn eccstop(&mut self) -> ECCSTOP_W<'_>

Bit 1 - Error Correction Code Generation Stop

pub fn eccclear(&mut self) -> ECCCLEAR_W<'_>

Bit 2 - Error Correction Code Clear

impl W<u32, Reg<u32, _TFTCTRL>>

pub fn dd(&mut self) -> DD_W<'_>

Bits 0:1 - TFT Direct Drive Mode

pub fn maskblend(&mut self) -> MASKBLEND_W<'_>

Bits 2:5 - TFT Mask and Blend Mode

pub fn shiftdclken(&mut self) -> SHIFTDCLKEN_W<'_>

Bit 8 - TFT EBI_DCLK Shift Enable

pub fn fbctrig(&mut self) -> FBCTRIG_W<'_>

Bit 9 - TFT Frame Base Copy Trigger

pub fn interleave(&mut self) -> INTERLEAVE_W<'_>

Bits 10:11 - Interleave Mode

pub fn color1src(&mut self) -> COLOR1SRC_W<'_>

Bit 12 - Masking/Alpha Blending Color1 Source

pub fn width(&mut self) -> WIDTH_W<'_>

Bits 16:17 - TFT Transaction Width

pub fn aliasbanken(&mut self) -> ALIASBANKEN_W<'_>

Bit 19 - Alias to Graphics Bank Enable

pub fn banksel(&mut self) -> BANKSEL_W<'_>

Bits 20:21 - Graphics Bank

pub fn aliasbank(&mut self) -> ALIASBANK_W<'_>

Bits 22:23 - Graphic Bank Select Aliasing

impl W<u32, Reg<u32, _TFTCOLORFORMAT>>

pub fn pixel0format(&mut self) -> PIXEL0FORMAT_W<'_>

Bits 0:2 - Sprite Pixel Color Format

pub fn pixel1format(&mut self) -> PIXEL1FORMAT_W<'_>

Bits 8:9 - Source and Destination Pixel Color Format

impl W<u32, Reg<u32, _TFTFRAMEBASE>>

pub fn framebase(&mut self) -> FRAMEBASE_W<'_>

Bits 0:27 - Frame Base Address

impl W<u32, Reg<u32, _TFTSTRIDE>>

pub fn hstride(&mut self) -> HSTRIDE_W<'_>

Bits 0:11 - Horizontal Stride

impl W<u32, Reg<u32, _TFTSIZE>>

pub fn hsz(&mut self) -> HSZ_W<'_>

Bits 0:9 - Horizontal Size (excluding Porches)

pub fn vsz(&mut self) -> VSZ_W<'_>

Bits 16:25 - Vertical Size (excluding Porches)

impl W<u32, Reg<u32, _TFTHPORCH>>

pub fn hsync(&mut self) -> HSYNC_W<'_>

Bits 0:6 - Horizontal Synchronization Pulse Width

pub fn hfporch(&mut self) -> HFPORCH_W<'_>

Bits 8:15 - Horizontal Front Porch Size

pub fn hbporch(&mut self) -> HBPORCH_W<'_>

Bits 18:25 - Horizontal Back Porch Size

pub fn hsyncstart(&mut self) -> HSYNCSTART_W<'_>

Bits 28:29 - HSYNC Start Delay

impl W<u32, Reg<u32, _TFTVPORCH>>

pub fn vsync(&mut self) -> VSYNC_W<'_>

Bits 0:6 - Vertical Synchronization Pulse Width

pub fn vfporch(&mut self) -> VFPORCH_W<'_>

Bits 8:19 - Vertical Front Porch Size

pub fn vbporch(&mut self) -> VBPORCH_W<'_>

Bits 20:31 - Vertical Back Porch Size

impl W<u32, Reg<u32, _TFTTIMING>>

pub fn dclkperiod(&mut self) -> DCLKPERIOD_W<'_>

Bits 0:11 - TFT Direct Drive Transaction (EBI_DCLK) Period

pub fn tftstart(&mut self) -> TFTSTART_W<'_>

Bits 12:23 - TFT Direct Drive Transaction Start

pub fn tftsetup(&mut self) -> TFTSETUP_W<'_>

Bits 24:26 - TFT Setup Time

pub fn tfthold(&mut self) -> TFTHOLD_W<'_>

Bits 28:30 - TFT Hold Time

impl W<u32, Reg<u32, _TFTPOLARITY>>

pub fn cspol(&mut self) -> CSPOL_W<'_>

Bit 0 - TFT Chip Select Polarity

pub fn dclkpol(&mut self) -> DCLKPOL_W<'_>

Bit 1 - TFT DCLK Polarity

pub fn dataenpol(&mut self) -> DATAENPOL_W<'_>

Bit 2 - TFT DATAEN Polarity

pub fn hsyncpol(&mut self) -> HSYNCPOL_W<'_>

Bit 3 - Address Latch Polarity

pub fn vsyncpol(&mut self) -> VSYNCPOL_W<'_>

Bit 4 - VSYNC Polarity

impl W<u32, Reg<u32, _TFTDD>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:23 - TFT Direct Drive Data From Internal Memory

impl W<u32, Reg<u32, _TFTALPHA>>

pub fn alpha(&mut self) -> ALPHA_W<'_>

Bits 0:8 - TFT Alpha Blending Factor

impl W<u32, Reg<u32, _TFTPIXEL0>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:23 - RGB Data

impl W<u32, Reg<u32, _TFTPIXEL1>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:23 - RGB Data

impl W<u32, Reg<u32, _TFTMASK>>

pub fn tftmask(&mut self) -> TFTMASK_W<'_>

Bits 0:23 - TFT Mask Value

impl W<u32, Reg<u32, _IFS>>

pub fn vsync(&mut self) -> VSYNC_W<'_>

Bit 0 - Vertical Sync Interrupt Flag Set

pub fn hsync(&mut self) -> HSYNC_W<'_>

Bit 1 - Horizontal Sync Interrupt Flag Set

pub fn vbporch(&mut self) -> VBPORCH_W<'_>

Bit 2 - Vertical Back Porch Interrupt Flag Set

pub fn vfporch(&mut self) -> VFPORCH_W<'_>

Bit 3 - Vertical Front Porch Interrupt Flag Set

pub fn ddempty(&mut self) -> DDEMPTY_W<'_>

Bit 4 - Direct Drive Data Empty Interrupt Flag Set

pub fn ddjit(&mut self) -> DDJIT_W<'_>

Bit 5 - Direct Drive Jitter Interrupt Flag Set

pub fn tftpixel0empty(&mut self) -> TFTPIXEL0EMPTY_W<'_>

Bit 6 - EBI_TFTPIXEL0 Empty Interrupt Flag Set

pub fn tftpixel1empty(&mut self) -> TFTPIXEL1EMPTY_W<'_>

Bit 7 - EBI_TFTPIXEL1 Empty Interrupt Flag Set

pub fn tftpixelfull(&mut self) -> TFTPIXELFULL_W<'_>

Bit 8 - EBI_TFTPIXEL Full Interrupt Flag Set

pub fn tftpixelof(&mut self) -> TFTPIXELOF_W<'_>

Bit 9 - EBI_TFTPIXEL Overflow Interrupt Flag Set

impl W<u32, Reg<u32, _IFC>>

pub fn vsync(&mut self) -> VSYNC_W<'_>

Bit 0 - Vertical Sync Interrupt Flag Clear

pub fn hsync(&mut self) -> HSYNC_W<'_>

Bit 1 - Horizontal Sync Interrupt Flag Clear

pub fn vbporch(&mut self) -> VBPORCH_W<'_>

Bit 2 - Vertical Back Porch Interrupt Flag Clear

pub fn vfporch(&mut self) -> VFPORCH_W<'_>

Bit 3 - Vertical Front Porch Interrupt Flag Clear

pub fn ddempty(&mut self) -> DDEMPTY_W<'_>

Bit 4 - Direct Drive Data Empty Interrupt Flag Clear

pub fn ddjit(&mut self) -> DDJIT_W<'_>

Bit 5 - Direct Drive Jitter Interrupt Flag Clear

pub fn tftpixel0empty(&mut self) -> TFTPIXEL0EMPTY_W<'_>

Bit 6 - EBI_TFTPIXEL0 Empty Interrupt Flag Clear

pub fn tftpixel1empty(&mut self) -> TFTPIXEL1EMPTY_W<'_>

Bit 7 - EBI_TFTPIXEL1 Empty Interrupt Flag Clear

pub fn tftpixelfull(&mut self) -> TFTPIXELFULL_W<'_>

Bit 8 - EBI_TFTPIXEL Full Interrupt Flag Clear

pub fn tftpixelof(&mut self) -> TFTPIXELOF_W<'_>

Bit 9 - EBI_TFTPIXEL Overflow Interrupt Flag Clear

impl W<u32, Reg<u32, _IEN>>

pub fn vsync(&mut self) -> VSYNC_W<'_>

Bit 0 - Vertical Sync Interrupt Enable

pub fn hsync(&mut self) -> HSYNC_W<'_>

Bit 1 - Horizontal Sync Interrupt Enable

pub fn vbporch(&mut self) -> VBPORCH_W<'_>

Bit 2 - Vertical Back Porch Interrupt Enable

pub fn vfporch(&mut self) -> VFPORCH_W<'_>

Bit 3 - Vertical Front Porch Interrupt Enable

pub fn ddempty(&mut self) -> DDEMPTY_W<'_>

Bit 4 - Direct Drive Data Empty Interrupt Enable

pub fn ddjit(&mut self) -> DDJIT_W<'_>

Bit 5 - Direct Drive Jitter Interrupt Enable

pub fn tftpixel0empty(&mut self) -> TFTPIXEL0EMPTY_W<'_>

Bit 6 - EBI_TFTPIXEL0 Empty Interrupt Enable

pub fn tftpixel1empty(&mut self) -> TFTPIXEL1EMPTY_W<'_>

Bit 7 - EBI_TFTPIXEL1 Empty Interrupt Enable

pub fn tftpixelfull(&mut self) -> TFTPIXELFULL_W<'_>

Bit 8 - EBI_TFTPIXEL Full Interrupt Enable

pub fn tftpixelof(&mut self) -> TFTPIXELOF_W<'_>

Bit 9 - EBI_TFTPIXEL Overflow Interrupt Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn ebipen(&mut self) -> EBIPEN_W<'_>

Bit 0 - EBI Pin Enable

pub fn cs0pen(&mut self) -> CS0PEN_W<'_>

Bit 1 - EBI_CS0 Pin Enable

pub fn cs1pen(&mut self) -> CS1PEN_W<'_>

Bit 2 - EBI_CS1 Pin Enable

pub fn cs2pen(&mut self) -> CS2PEN_W<'_>

Bit 3 - EBI_CS2 Pin Enable

pub fn cs3pen(&mut self) -> CS3PEN_W<'_>

Bit 4 - EBI_CS3 Pin Enable

pub fn alepen(&mut self) -> ALEPEN_W<'_>

Bit 5 - EBI_ALE Pin Enable

pub fn ardypen(&mut self) -> ARDYPEN_W<'_>

Bit 6 - EBI_ARDY Pin Enable

pub fn blpen(&mut self) -> BLPEN_W<'_>

Bit 7 - EBI_BL[1:0] Pin Enable

pub fn nandpen(&mut self) -> NANDPEN_W<'_>

Bit 12 - NANDRE and NANDWE Pin Enable

pub fn alb(&mut self) -> ALB_W<'_>

Bits 16:17 - Sets the Lower Bound for EBI_A Enabling

pub fn apen(&mut self) -> APEN_W<'_>

Bits 18:22 - EBI_A Pin Enable

pub fn tftpen(&mut self) -> TFTPEN_W<'_>

Bit 24 - EBI_TFT Pin Enable

pub fn dataenpen(&mut self) -> DATAENPEN_W<'_>

Bit 25 - EBI_DATA Pin Enable

pub fn cstftpen(&mut self) -> CSTFTPEN_W<'_>

Bit 26 - EBI_CSTFT Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn ebiloc(&mut self) -> EBILOC_W<'_>

Bits 0:5 - I/O Location

pub fn csloc(&mut self) -> CSLOC_W<'_>

Bits 8:13 - I/O Location

pub fn nandloc(&mut self) -> NANDLOC_W<'_>

Bits 16:21 - I/O Location

pub fn tftloc(&mut self) -> TFTLOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn adloc(&mut self) -> ADLOC_W<'_>

Bits 0:5 - I/O Location

pub fn aloc(&mut self) -> ALOC_W<'_>

Bits 8:13 - I/O Location

pub fn rdyloc(&mut self) -> RDYLOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _NETWORKCTRL>>

pub fn loopbacklocal(&mut self) -> LOOPBACKLOCAL_W<'_>

Bit 1 - Loopback local

pub fn enbrx(&mut self) -> ENBRX_W<'_>

Bit 2 - Receive enable

pub fn enbtx(&mut self) -> ENBTX_W<'_>

Bit 3 - Transmit enable

pub fn manporten(&mut self) -> MANPORTEN_W<'_>

Bit 4 - Management port enable

pub fn clrallstatsregs(&mut self) -> CLRALLSTATSREGS_W<'_>

Bit 5 - Clear statistics registers

pub fn incallstatsregs(&mut self) -> INCALLSTATSREGS_W<'_>

Bit 6 - Incremental statistics registers

pub fn statswren(&mut self) -> STATSWREN_W<'_>

Bit 7 - Write enable for statistics registers

pub fn backpressure(&mut self) -> BACKPRESSURE_W<'_>

Bit 8 - Back pressure will force collisions on all received frames

pub fn txstrt(&mut self) -> TXSTRT_W<'_>

Bit 9 - Start transmission

pub fn txhalt(&mut self) -> TXHALT_W<'_>

Bit 10 - Transmit halt

pub fn txpfrmreq(&mut self) -> TXPFRMREQ_W<'_>

Bit 11 - Transmit pause frame

pub fn txpfrmzero(&mut self) -> TXPFRMZERO_W<'_>

Bit 12 - Transmit zero quantum pause frame

pub fn storerxts(&mut self) -> STORERXTS_W<'_>

Bit 15 - Store receive time stamp to memory.

pub fn pfcenb(&mut self) -> PFCENB_W<'_>

Bit 16 - Enable PFC Priority Based Pause Reception capabilities.

pub fn txpfcpriorpfrm(&mut self) -> TXPFCPRIORPFRM_W<'_>

Bit 17 - Write a one to transmit PFC priority based pause frame.

pub fn flushrxpkt(&mut self) -> FLUSHRXPKT_W<'_>

Bit 18 - Flush the next packet from the external RX DPRAM.

pub fn txlpien(&mut self) -> TXLPIEN_W<'_>

Bit 19 - Enable LPI transmission when set LPI (low power idle) is immediately transmitted.

pub fn ptpunicasten(&mut self) -> PTPUNICASTEN_W<'_>

Bit 20 - Enable detection of unicast PTP unicast frames.

pub fn storeudpoffset(&mut self) -> STOREUDPOFFSET_W<'_>

Bit 22 - Store UDP / TCP offset to memory.

pub fn onestepsyncmode(&mut self) -> ONESTEPSYNCMODE_W<'_>

Bit 24 - 1588 One Step Sync Mode.

pub fn pfcctrl(&mut self) -> PFCCTRL_W<'_>

Bit 25 - Enable multiple PFC pause quantums, one per pause priority

impl W<u32, Reg<u32, _NETWORKCFG>>

pub fn speed(&mut self) -> SPEED_W<'_>

Bit 0 - Speed

pub fn fullduplex(&mut self) -> FULLDUPLEX_W<'_>

Bit 1 - Full duplex

pub fn discrdnonvlanframes(&mut self) -> DISCRDNONVLANFRAMES_W<'_>

Bit 2 - Discard non-VLAN frames

pub fn jumboframes(&mut self) -> JUMBOFRAMES_W<'_>

Bit 3 - Jumbo frames enable

pub fn copyallframes(&mut self) -> COPYALLFRAMES_W<'_>

Bit 4 - Copy all frames

pub fn nobroadcast(&mut self) -> NOBROADCAST_W<'_>

Bit 5 - No broadcast

pub fn multicasthashen(&mut self) -> MULTICASTHASHEN_W<'_>

Bit 6 - Multicast hash enable

pub fn unicasthashen(&mut self) -> UNICASTHASHEN_W<'_>

Bit 7 - Unicast hash enable

pub fn rx1536byteframes(&mut self) -> RX1536BYTEFRAMES_W<'_>

Bit 8 - Receive 1536 byte frames

pub fn retrytest(&mut self) -> RETRYTEST_W<'_>

Bit 12 - Retry test

pub fn pauseen(&mut self) -> PAUSEEN_W<'_>

Bit 13 - Pause enable

pub fn rxbuffoffset(&mut self) -> RXBUFFOFFSET_W<'_>

Bits 14:15 - Receive buffer offset

pub fn lenfielderrfrmdiscrd(&mut self) -> LENFIELDERRFRMDISCRD_W<'_>

Bit 16 - Length field error frame discard

pub fn fcsremove(&mut self) -> FCSREMOVE_W<'_>

Bit 17 - FCS remove

pub fn mdcclkdiv(&mut self) -> MDCCLKDIV_W<'_>

Bits 18:20 - MDC clock division

pub fn discopyofpframes(&mut self) -> DISCOPYOFPFRAMES_W<'_>

Bit 23 - Disable copy of pause frames

pub fn rxchksumoffloaden(&mut self) -> RXCHKSUMOFFLOADEN_W<'_>

Bit 24 - Receive checksum offload enable

pub fn enhalfduplexrx(&mut self) -> ENHALFDUPLEXRX_W<'_>

Bit 25 - Enable frames to be received in half-duplex mode while transmitting.

pub fn ignorerxfcs(&mut self) -> IGNORERXFCS_W<'_>

Bit 26 - Ignore RX FCS

pub fn ipgstrtchen(&mut self) -> IPGSTRTCHEN_W<'_>

Bit 28 - IPG stretch enable

pub fn nspchange(&mut self) -> NSPCHANGE_W<'_>

Bit 29 - Receive bad preamble.

pub fn ignoreipgrxer(&mut self) -> IGNOREIPGRXER_W<'_>

Bit 30 - Ignore IPG rx_er.

impl W<u32, Reg<u32, _DMACFG>>

pub fn ambabrstlen(&mut self) -> AMBABRSTLEN_W<'_>

Bits 0:4 - Selects the burst length to use on the AMBA (AHB) when transferring frame data.

pub fn hdrdataspliten(&mut self) -> HDRDATASPLITEN_W<'_>

Bit 5 - Enable header data Splitting.

pub fn rxpbufsize(&mut self) -> RXPBUFSIZE_W<'_>

Bits 8:9 - Receiver packet buffer memory size select.

pub fn txpbufsize(&mut self) -> TXPBUFSIZE_W<'_>

Bit 10 - Transmitter packet buffer memory size select.

pub fn txpbuftcpen(&mut self) -> TXPBUFTCPEN_W<'_>

Bit 11 - Transmitter IP, TCP and UDP checksum generation offload enable

pub fn inflastdbufsizeen(&mut self) -> INFLASTDBUFSIZEEN_W<'_>

Bit 12 - Forces the DMA

pub fn rxbufsize(&mut self) -> RXBUFSIZE_W<'_>

Bits 16:23 - DMA receive buffer size in external AMBA (AHB) system memory.

pub fn frcdiscardonerr(&mut self) -> FRCDISCARDONERR_W<'_>

Bit 24 - Auto Discard RX pkts during lack of resource.

pub fn frcmaxambabrstrx(&mut self) -> FRCMAXAMBABRSTRX_W<'_>

Bit 25 - Force max length bursts on RX.

pub fn frcmaxambabrsttx(&mut self) -> FRCMAXAMBABRSTTX_W<'_>

Bit 26 - Force max length bursts on TX.

pub fn rxbdextndmodeen(&mut self) -> RXBDEXTNDMODEEN_W<'_>

Bit 28 - Enable RX extended BD mode.

pub fn txbdextendmodeen(&mut self) -> TXBDEXTENDMODEEN_W<'_>

Bit 29 - Enable TX extended BD mode.

impl W<u32, Reg<u32, _TXSTATUS>>

pub fn usedbitread(&mut self) -> USEDBITREAD_W<'_>

Bit 0 - Used bit read

pub fn coloccrd(&mut self) -> COLOCCRD_W<'_>

Bit 1 - Collision occurred

pub fn retrylmtexcd(&mut self) -> RETRYLMTEXCD_W<'_>

Bit 2 - Retry limit exceeded

pub fn ambaerr(&mut self) -> AMBAERR_W<'_>

Bit 4 - Transmit frame corruption due to AMBA (AHB) errors.

pub fn txcmplt(&mut self) -> TXCMPLT_W<'_>

Bit 5 - Transmit complete

pub fn txunderrun(&mut self) -> TXUNDERRUN_W<'_>

Bit 6 - Transmit under run

pub fn latecoloccrd(&mut self) -> LATECOLOCCRD_W<'_>

Bit 7 - Late collision occurred

pub fn respnotok(&mut self) -> RESPNOTOK_W<'_>

Bit 8 - bresp/hresp not OK

impl W<u32, Reg<u32, _RXQPTR>>

pub fn dmarxqptr(&mut self) -> DMARXQPTR_W<'_>

Bits 2:31 - Receive buffer queue base address

impl W<u32, Reg<u32, _TXQPTR>>

pub fn dmatxqptr(&mut self) -> DMATXQPTR_W<'_>

Bits 2:31 - Transmit buffer queue base address

impl W<u32, Reg<u32, _RXSTATUS>>

pub fn buffnotavail(&mut self) -> BUFFNOTAVAIL_W<'_>

Bit 0 - Buffer not available

pub fn frmrx(&mut self) -> FRMRX_W<'_>

Bit 1 - Frame received

pub fn rxoverrun(&mut self) -> RXOVERRUN_W<'_>

Bit 2 - Receive overrun

pub fn respnotok(&mut self) -> RESPNOTOK_W<'_>

Bit 3 - bresp/hresp not OK

impl W<u32, Reg<u32, _IFCR>>

pub fn mngmntdone(&mut self) -> MNGMNTDONE_W<'_>

Bit 0 - Management frame sent

pub fn rxcmplt(&mut self) -> RXCMPLT_W<'_>

Bit 1 - Receive complete

pub fn rxusedbitread(&mut self) -> RXUSEDBITREAD_W<'_>

Bit 2 - RX used bit read

pub fn txusedbitread(&mut self) -> TXUSEDBITREAD_W<'_>

Bit 3 - TX used bit read

pub fn txunderrun(&mut self) -> TXUNDERRUN_W<'_>

Bit 4 - Transmit under run

pub fn rtrylmtorlatecol(&mut self) -> RTRYLMTORLATECOL_W<'_>

Bit 5 - Retry limit exceeded or late collision

pub fn ambaerr(&mut self) -> AMBAERR_W<'_>

Bit 6 - Transmit frame corruption due to AMBA (AHB) error.

pub fn txcmplt(&mut self) -> TXCMPLT_W<'_>

Bit 7 - Transmit complete

pub fn rxoverrun(&mut self) -> RXOVERRUN_W<'_>

Bit 10 - Receive overrun

pub fn respnotok(&mut self) -> RESPNOTOK_W<'_>

Bit 11 - Hresp not OK

pub fn nonzeropfrmquant(&mut self) -> NONZEROPFRMQUANT_W<'_>

Bit 12 - Pause frame with non-zero pause quantum received

pub fn pausetimezero(&mut self) -> PAUSETIMEZERO_W<'_>

Bit 13 - Pause Time zero

pub fn pfrmtx(&mut self) -> PFRMTX_W<'_>

Bit 14 - Pause frame transmitted

pub fn ptpdlyreqfrmrx(&mut self) -> PTPDLYREQFRMRX_W<'_>

Bit 18 - PTP delay_req frame received

pub fn ptpsyncfrmrx(&mut self) -> PTPSYNCFRMRX_W<'_>

Bit 19 - PTP sync frame received

pub fn ptpdlyreqfrmtx(&mut self) -> PTPDLYREQFRMTX_W<'_>

Bit 20 - PTP delay_req frame transmitted

pub fn ptpsyncfrmtx(&mut self) -> PTPSYNCFRMTX_W<'_>

Bit 21 - PTP sync frame transmitted

pub fn ptppdlyreqfrmrx(&mut self) -> PTPPDLYREQFRMRX_W<'_>

Bit 22 - PTP pdelay_req frame received

pub fn ptppdlyrespfrmrx(&mut self) -> PTPPDLYRESPFRMRX_W<'_>

Bit 23 - PTP pdelay_resp frame received

pub fn ptppdlyreqfrmtx(&mut self) -> PTPPDLYREQFRMTX_W<'_>

Bit 24 - PTP pdelay_req frame transmitted

pub fn ptppdlyrespfrmtx(&mut self) -> PTPPDLYRESPFRMTX_W<'_>

Bit 25 - PTP pdelay_resp frame transmitted

pub fn tsusecregincr(&mut self) -> TSUSECREGINCR_W<'_>

Bit 26 - TSU seconds register increment

pub fn rxlpiindc(&mut self) -> RXLPIINDC_W<'_>

Bit 27 - Receive LPI indication status bit change

pub fn wolevntrx(&mut self) -> WOLEVNTRX_W<'_>

Bit 28 - WOL event received interrupt.

pub fn tsutimercomp(&mut self) -> TSUTIMERCOMP_W<'_>

Bit 29 - TSU timer comparison interrupt.

impl W<u32, Reg<u32, _IENS>>

pub fn mngmntdone(&mut self) -> MNGMNTDONE_W<'_>

Bit 0 - Enable management done interrupt

pub fn rxcmplt(&mut self) -> RXCMPLT_W<'_>

Bit 1 - Enable receive complete interrupt

pub fn rxusedbitread(&mut self) -> RXUSEDBITREAD_W<'_>

Bit 2 - Enable receive used bit read interrupt

pub fn txusedbitread(&mut self) -> TXUSEDBITREAD_W<'_>

Bit 3 - Enable transmit used bit read interrupt

pub fn txunderrun(&mut self) -> TXUNDERRUN_W<'_>

Bit 4 - Enable transmit buffer under run interrupt

pub fn rtrylmtorlatecol(&mut self) -> RTRYLMTORLATECOL_W<'_>

Bit 5 - Enable retry limit exceeded or late collision interrupt

pub fn ambaerr(&mut self) -> AMBAERR_W<'_>

Bit 6 - Enable transmit frame corruption due to AMBA (AHB) error interrupt

pub fn txcmplt(&mut self) -> TXCMPLT_W<'_>

Bit 7 - Enable transmit complete interrupt

pub fn rxoverrun(&mut self) -> RXOVERRUN_W<'_>

Bit 10 - Enable receive overrun interrupt

pub fn respnotok(&mut self) -> RESPNOTOK_W<'_>

Bit 11 - Enable bresp/hresp not OK interrupt

pub fn nonzeropfrmquant(&mut self) -> NONZEROPFRMQUANT_W<'_>

Bit 12 - Enable pause frame with non-zero pause quantum interrupt

pub fn pausetimezero(&mut self) -> PAUSETIMEZERO_W<'_>

Bit 13 - Enable pause time zero interrupt

pub fn pfrmtx(&mut self) -> PFRMTX_W<'_>

Bit 14 - Enable pause frame transmitted interrupt

pub fn ptpdlyreqfrmrx(&mut self) -> PTPDLYREQFRMRX_W<'_>

Bit 18 - Enable PTP delay_req frame received interrupt

pub fn ptpsyncfrmrx(&mut self) -> PTPSYNCFRMRX_W<'_>

Bit 19 - Enable PTP sync frame received interrupt

pub fn ptpdlyreqfrmtx(&mut self) -> PTPDLYREQFRMTX_W<'_>

Bit 20 - Enable PTP delay_req frame transmitted interrupt

pub fn ptpsyncfrmtx(&mut self) -> PTPSYNCFRMTX_W<'_>

Bit 21 - Enable PTP sync frame transmitted interrupt

pub fn ptppdlyreqfrmrx(&mut self) -> PTPPDLYREQFRMRX_W<'_>

Bit 22 - Enable PTP pdelay_req frame received interrupt

pub fn ptppdlyrespfrmrx(&mut self) -> PTPPDLYRESPFRMRX_W<'_>

Bit 23 - Enable PTP pdelay_resp frame received interrupt

pub fn ptppdlyreqfrmtx(&mut self) -> PTPPDLYREQFRMTX_W<'_>

Bit 24 - Enable PTP pdelay_req frame transmitted interrupt

pub fn ptppdlyrespfrmtx(&mut self) -> PTPPDLYRESPFRMTX_W<'_>

Bit 25 - Enable PTP pdelay_resp frame transmitted interrupt

pub fn tsusecregincr(&mut self) -> TSUSECREGINCR_W<'_>

Bit 26 - Enable TSU seconds register increment interrupt

pub fn rxlpiindc(&mut self) -> RXLPIINDC_W<'_>

Bit 27 - Enable RX LPI indication interrupt

pub fn wolevntrx(&mut self) -> WOLEVNTRX_W<'_>

Bit 28 - Enable WOL event received interrupt

pub fn tsutimercomp(&mut self) -> TSUTIMERCOMP_W<'_>

Bit 29 - Enable TSU timer comparison interrupt.

impl W<u32, Reg<u32, _IENC>>

pub fn mngmntdone(&mut self) -> MNGMNTDONE_W<'_>

Bit 0 - Disable management done interrupt

pub fn rxcmplt(&mut self) -> RXCMPLT_W<'_>

Bit 1 - Disable receive complete interrupt

pub fn rxusedbitread(&mut self) -> RXUSEDBITREAD_W<'_>

Bit 2 - Disable receive used bit read interrupt

pub fn txusedbitread(&mut self) -> TXUSEDBITREAD_W<'_>

Bit 3 - Disable transmit used bit read interrupt

pub fn txunderrun(&mut self) -> TXUNDERRUN_W<'_>

Bit 4 - Disable transmit buffer under run interrupt

pub fn rtrylmtorlatecol(&mut self) -> RTRYLMTORLATECOL_W<'_>

Bit 5 - Disable retry limit exceeded or late collision interrupt

pub fn ambaerr(&mut self) -> AMBAERR_W<'_>

Bit 6 - Disable transmit frame corruption due to AMBA (AHB) error interrupt

pub fn txcmplt(&mut self) -> TXCMPLT_W<'_>

Bit 7 - Disable transmit complete interrupt

pub fn rxoverrun(&mut self) -> RXOVERRUN_W<'_>

Bit 10 - Disable receive overrun interrupt

pub fn respnotok(&mut self) -> RESPNOTOK_W<'_>

Bit 11 - Disable bresp/hresp not OK interrupt

pub fn nonzeropfrmquant(&mut self) -> NONZEROPFRMQUANT_W<'_>

Bit 12 - Disable pause frame with non-zero pause quantum interrupt

pub fn pausetimezero(&mut self) -> PAUSETIMEZERO_W<'_>

Bit 13 - Disable pause time zero interrupt

pub fn pfrmtx(&mut self) -> PFRMTX_W<'_>

Bit 14 - Disable pause frame transmitted interrupt

pub fn ptpdlyreqfrmrx(&mut self) -> PTPDLYREQFRMRX_W<'_>

Bit 18 - Disable PTP delay_req frame received interrupt

pub fn ptpsyncfrmrx(&mut self) -> PTPSYNCFRMRX_W<'_>

Bit 19 - Disable PTP sync frame received interrupt

pub fn ptpdlyreqfrmtx(&mut self) -> PTPDLYREQFRMTX_W<'_>

Bit 20 - Disable PTP delay_req frame transmitted interrupt

pub fn ptpsyncfrmtx(&mut self) -> PTPSYNCFRMTX_W<'_>

Bit 21 - Disable PTP sync frame transmitted interrupt

pub fn ptppdlyreqfrmrx(&mut self) -> PTPPDLYREQFRMRX_W<'_>

Bit 22 - Disable PTP pdelay_req frame received interrupt

pub fn ptppdlyrespfrmrx(&mut self) -> PTPPDLYRESPFRMRX_W<'_>

Bit 23 - Disable PTP pdelay_resp frame received interrupt

pub fn ptppdlyreqfrmtx(&mut self) -> PTPPDLYREQFRMTX_W<'_>

Bit 24 - Disable PTP pdelay_req frame transmitted interrupt

pub fn ptppdlyrespfrmtx(&mut self) -> PTPPDLYRESPFRMTX_W<'_>

Bit 25 - Disable PTP pdelay_resp frame transmitted interrupt

pub fn tsusecregincr(&mut self) -> TSUSECREGINCR_W<'_>

Bit 26 - Disable TSU seconds register increment interrupt

pub fn rxlpiindc(&mut self) -> RXLPIINDC_W<'_>

Bit 27 - Disable RX LPI indication interrupt

pub fn wolevntrx(&mut self) -> WOLEVNTRX_W<'_>

Bit 28 - Disable WOL event received interrupt

pub fn tsutimercomp(&mut self) -> TSUTIMERCOMP_W<'_>

Bit 29 - Disable TSU timer comparison interrupt.

impl W<u32, Reg<u32, _IENRO>>

pub fn mngmntdone(&mut self) -> MNGMNTDONE_W<'_>

Bit 0 - management done interrupt mask

pub fn rxcmplt(&mut self) -> RXCMPLT_W<'_>

Bit 1 - receive complete interrupt mask

pub fn rxusedbitread(&mut self) -> RXUSEDBITREAD_W<'_>

Bit 2 - receive used bit read interrupt mask

pub fn txusedbitread(&mut self) -> TXUSEDBITREAD_W<'_>

Bit 3 - transmit used bit read interrupt mask

pub fn txunderrun(&mut self) -> TXUNDERRUN_W<'_>

Bit 4 - transmit buffer under run interrupt mask

pub fn rtrylmtorlatecol(&mut self) -> RTRYLMTORLATECOL_W<'_>

Bit 5 - Retry limit exceeded or late collision (gigabit mode only) interrupt mask

pub fn ambaerr(&mut self) -> AMBAERR_W<'_>

Bit 6 - Transmit frame corruption due to AMBA (AHB) error interrupt mask

pub fn txcmplt(&mut self) -> TXCMPLT_W<'_>

Bit 7 - Transmit complete interrupt mask

pub fn unused(&mut self) -> UNUSED_W<'_>

Bit 8 - Unused

pub fn rxoverrun(&mut self) -> RXOVERRUN_W<'_>

Bit 10 - Receive overrun interrupt mask

pub fn respnotok(&mut self) -> RESPNOTOK_W<'_>

Bit 11 - bresp/hresp not OK interrupt mask

pub fn nonzeropfrmquant(&mut self) -> NONZEROPFRMQUANT_W<'_>

Bit 12 - Pause frame with non-zero pause quantum interrupt mask

pub fn pausetimezero(&mut self) -> PAUSETIMEZERO_W<'_>

Bit 13 - pause time zero interrupt mask

pub fn pfrmtx(&mut self) -> PFRMTX_W<'_>

Bit 14 - pause frame transmitted interrupt mask

pub fn ptpdlyreqfrmrx(&mut self) -> PTPDLYREQFRMRX_W<'_>

Bit 18 - PTP delay_req frame received mask

pub fn ptpsyncfrmrx(&mut self) -> PTPSYNCFRMRX_W<'_>

Bit 19 - PTP sync frame received mask

pub fn ptpdlyreqfrmtx(&mut self) -> PTPDLYREQFRMTX_W<'_>

Bit 20 - PTP delay_req frame transmitted mask

pub fn ptpsyncfrmtx(&mut self) -> PTPSYNCFRMTX_W<'_>

Bit 21 - PTP sync frame transmitted mask

pub fn ptppdlyreqfrmrx(&mut self) -> PTPPDLYREQFRMRX_W<'_>

Bit 22 - PTP pdelay_req frame received mask

pub fn ptppdlyrespfrmrx(&mut self) -> PTPPDLYRESPFRMRX_W<'_>

Bit 23 - PTP pdelay_resp frame received mask

pub fn ptppdlyreqfrmtx(&mut self) -> PTPPDLYREQFRMTX_W<'_>

Bit 24 - PTP pdelay_req frame transmitted mask

pub fn ptppdlyrespfrmtx(&mut self) -> PTPPDLYRESPFRMTX_W<'_>

Bit 25 - PTP pdelay_resp frame transmitted mask

pub fn tsusecregincr(&mut self) -> TSUSECREGINCR_W<'_>

Bit 26 - TSU seconds register increment mask

pub fn rxlpiindc(&mut self) -> RXLPIINDC_W<'_>

Bit 27 - RX LPI indication mask

pub fn wolevntrx(&mut self) -> WOLEVNTRX_W<'_>

Bit 28 - WOL event received mask

pub fn tsutimercomp(&mut self) -> TSUTIMERCOMP_W<'_>

Bit 29 - TSU timer comparison interrupt mask.

impl W<u32, Reg<u32, _PHYMNGMNT>>

pub fn phyrwdata(&mut self) -> PHYRWDATA_W<'_>

Bits 0:15 - PHY read write data

pub fn write10(&mut self) -> WRITE10_W<'_>

Bits 16:17 - Must be written with 10.

pub fn regaddr(&mut self) -> REGADDR_W<'_>

Bits 18:22 - Register address - specifies the register in the PHY to access.

pub fn phyaddr(&mut self) -> PHYADDR_W<'_>

Bits 23:27 - PHY address.

pub fn operation(&mut self) -> OPERATION_W<'_>

Bits 28:29 - Operation. For a Clause 45 frame: 00 is an addr, 01 is a write, 10 is a post read increment, 11 is a read frame. For a Clause 22 frame: 10 is a read, 01 is a write.

pub fn write1(&mut self) -> WRITE1_W<'_>

Bit 30 - Must be written to 1 for a valid Clause 22 frame and to 0 for a valid Clause 45 frame.

pub fn write0(&mut self) -> WRITE0_W<'_>

Bit 31 - Must be written with 0.

impl W<u32, Reg<u32, _TXPAUSEQUANT>>

pub fn quant(&mut self) -> QUANT_W<'_>

Bits 0:15 - Transmit pause quantum

pub fn quantp1(&mut self) -> QUANTP1_W<'_>

Bits 16:31 - Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 1.

impl W<u32, Reg<u32, _PBUFTXCUTTHRU>>

pub fn dmatxcutthruthr(&mut self) -> DMATXCUTTHRUTHR_W<'_>

Bits 0:9 - Watermark value

pub fn dmatxcutthru(&mut self) -> DMATXCUTTHRU_W<'_>

Bit 31 - Enable TX partial store and forward operation

impl W<u32, Reg<u32, _PBUFRXCUTTHRU>>

pub fn dmarxcutthruthr(&mut self) -> DMARXCUTTHRUTHR_W<'_>

Bits 0:9 - Watermark value

pub fn dmarxcutthru(&mut self) -> DMARXCUTTHRU_W<'_>

Bit 31 - Enable RX partial store and forward operation

impl W<u32, Reg<u32, _JUMBOMAXLEN>>

pub fn jumbomaxlen(&mut self) -> JUMBOMAXLEN_W<'_>

Bits 0:13 - Maximum Jumbo Frame Size - resets to the gem_jumbo_max_length define value.

impl W<u32, Reg<u32, _IMOD>>

pub fn rxintmod(&mut self) -> RXINTMOD_W<'_>

Bits 0:7 - Count of 800ns periods before bit 1 is set in the interrupt status register after a frame is received

pub fn txintmod(&mut self) -> TXINTMOD_W<'_>

Bits 16:23 - Count of 800ns periods before bit 7 is set in the interrupt status register after a frame is transmitted

impl W<u32, Reg<u32, _SYSWAKETIME>>

pub fn syswaketime(&mut self) -> SYSWAKETIME_W<'_>

Bits 0:15 - Count of 64ns, 320ns or 3200ns intervals before transmission starts after deassertion of tx_lpi_en

impl W<u32, Reg<u32, _HASHBOTTOM>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - The first 32 bits of the hash address register.

impl W<u32, Reg<u32, _HASHTOP>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - The remaining 32 bits of the hash address register.

impl W<u32, Reg<u32, _SPECADDR1BOTTOM>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Least significant 32 bits of the destination address

impl W<u32, Reg<u32, _SPECADDR1TOP>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:15 - Specific address 1 MSB

pub fn filtertype(&mut self) -> FILTERTYPE_W<'_>

Bit 16 - MAC SA or DA selection

impl W<u32, Reg<u32, _SPECADDR2BOTTOM>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Least significant 32 bits of the destination address

impl W<u32, Reg<u32, _SPECADDR2TOP>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:15 - Specific address 2 MSB

pub fn filtertype(&mut self) -> FILTERTYPE_W<'_>

Bit 16 - MAC SA or DA selection

pub fn filterbytemask(&mut self) -> FILTERBYTEMASK_W<'_>

Bits 24:29 - Filter byte Mask

impl W<u32, Reg<u32, _SPECADDR3BOTTOM>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Least significant 32 bits of the destination address

impl W<u32, Reg<u32, _SPECADDR3TOP>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:15 - Specific address 3 MSB

pub fn filtertype(&mut self) -> FILTERTYPE_W<'_>

Bit 16 - MAC SA or DA selection

pub fn filterbytemask(&mut self) -> FILTERBYTEMASK_W<'_>

Bits 24:29 - Filter byte Mask

impl W<u32, Reg<u32, _SPECADDR4BOTTOM>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Least significant 32 bits of the destination address

impl W<u32, Reg<u32, _SPECADDR4TOP>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:15 - Specific address 4 MSB

pub fn filtertype(&mut self) -> FILTERTYPE_W<'_>

Bit 16 - MAC SA or DA selection

pub fn filterbytemask(&mut self) -> FILTERBYTEMASK_W<'_>

Bits 24:29 - Filter byte Mask

impl W<u32, Reg<u32, _SPECTYPE1>>

pub fn match_(&mut self) -> MATCH_W<'_>

Bits 0:15 - Type ID match 1

pub fn enbcopy(&mut self) -> ENBCOPY_W<'_>

Bit 31 - Enable copying of type ID match 1 matched frames.

impl W<u32, Reg<u32, _SPECTYPE2>>

pub fn match_(&mut self) -> MATCH_W<'_>

Bits 0:15 - Type ID match 2

pub fn enbcopy(&mut self) -> ENBCOPY_W<'_>

Bit 31 - Enable copying of type ID match 2 matched frames.

impl W<u32, Reg<u32, _SPECTYPE3>>

pub fn match_(&mut self) -> MATCH_W<'_>

Bits 0:15 - Type ID match 3

pub fn enbcopy(&mut self) -> ENBCOPY_W<'_>

Bit 31 - Enable copying of type ID match 3 matched frames.

impl W<u32, Reg<u32, _SPECTYPE4>>

pub fn match_(&mut self) -> MATCH_W<'_>

Bits 0:15 - Type ID match 4

pub fn enbcopy(&mut self) -> ENBCOPY_W<'_>

Bit 31 - Enable copying of type ID match 4 matched frames.

impl W<u32, Reg<u32, _WOLREG>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:15 - Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame.

pub fn wolmask0(&mut self) -> WOLMASK0_W<'_>

Bit 16 - Wake on LAN magic packet event enable

pub fn wolmask1(&mut self) -> WOLMASK1_W<'_>

Bit 17 - Wake on LAN ARP request event enable

pub fn wolmask2(&mut self) -> WOLMASK2_W<'_>

Bit 18 - Wake on LAN specific address register 1 event enable

pub fn wolmask3(&mut self) -> WOLMASK3_W<'_>

Bit 19 - Wake on LAN multicast hash event enable

impl W<u32, Reg<u32, _STRETCHRATIO>>

pub fn ipgstretch(&mut self) -> IPGSTRETCH_W<'_>

Bits 0:15 - IPG Stretch

impl W<u32, Reg<u32, _STACKEDVLAN>>

pub fn match_(&mut self) -> MATCH_W<'_>

Bits 0:15 - User defined VLAN_TYPE field

pub fn enbprocessing(&mut self) -> ENBPROCESSING_W<'_>

Bit 31 - Enable stacked VLAN processing mode

impl W<u32, Reg<u32, _TXPFCPAUSE>>

pub fn vectorenb(&mut self) -> VECTORENB_W<'_>

Bits 0:7 - Priority Vector Enable. If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0].

pub fn vector(&mut self) -> VECTOR_W<'_>

Bits 8:15 - Priority Vector Pause Size. If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frame’s pause quantum field associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero.

impl W<u32, Reg<u32, _MASKADD1BOTTOM>>

pub fn addrmask(&mut self) -> ADDRMASK_W<'_>

Bits 0:31 - Specific Address Mask

impl W<u32, Reg<u32, _MASKADD1TOP>>

pub fn addrmask(&mut self) -> ADDRMASK_W<'_>

Bits 0:15 - Specific Address Mask

impl W<u32, Reg<u32, _RXPTPUNICAST>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Unicast IP destination address

impl W<u32, Reg<u32, _TXPTPUNICAST>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Unicast IP destination address

impl W<u32, Reg<u32, _TSUNSECCMP>>

pub fn compval(&mut self) -> COMPVAL_W<'_>

Bits 0:21 - TSU timer comparison value (ns)

impl W<u32, Reg<u32, _TSUSECCMP>>

pub fn compval(&mut self) -> COMPVAL_W<'_>

Bits 0:31 - TSU timer comparison value (s)

impl W<u32, Reg<u32, _TSUMSBSECCMP>>

pub fn compval(&mut self) -> COMPVAL_W<'_>

Bits 0:15 - TSU timer comparison value (s)

impl W<u32, Reg<u32, _OCTETSTXEDBOTTOM>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Transmitted octets in frame without errors [31:0]

impl W<u32, Reg<u32, _OCTETSTXEDTOP>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Transmitted octets in frame without errors [47:32]

impl W<u32, Reg<u32, _FRAMESTXEDOK>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Frames transmitted without error

impl W<u32, Reg<u32, _BROADCASTTXED>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Broadcast frames transmitted without error

impl W<u32, Reg<u32, _MULTICASTTXED>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Multicast frames transmitted without error

impl W<u32, Reg<u32, _PFRAMESTXED>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Transmitted pause frames

impl W<u32, Reg<u32, _FRAMESTXED64>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 64 byte frames transmitted without error

impl W<u32, Reg<u32, _FRAMESTXED65>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 65 to127 byte frames transmitted without error

impl W<u32, Reg<u32, _FRAMESTXED128>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 128 to 255 byte frames transmitted without error

impl W<u32, Reg<u32, _FRAMESTXED256>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 256 to 511 byte frames transmitted without error

impl W<u32, Reg<u32, _FRAMESTXED512>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 512 to 1023 byte frames transmitted without error

impl W<u32, Reg<u32, _FRAMESTXED1024>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 1024 to 1518 byte frames transmitted without error

impl W<u32, Reg<u32, _FRAMESTXED1519>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Greater than 1518 byte frames transmitted without error

impl W<u32, Reg<u32, _TXUNDERRUNS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Transmit under runs

impl W<u32, Reg<u32, _SINGLECOLS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:17 - Single collision frames

impl W<u32, Reg<u32, _MULTICOLS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:17 - Multiple collision frames

impl W<u32, Reg<u32, _EXCESSCOLS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Excessive collisions

impl W<u32, Reg<u32, _LATECOLS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Late collisions

impl W<u32, Reg<u32, _DEFERREDFRAMES>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:17 - Deferred transmission frames

impl W<u32, Reg<u32, _CRSERRS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Carrier sense errors

impl W<u32, Reg<u32, _OCTETSRXEDBOTTOM>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Received octets in frame without errors

impl W<u32, Reg<u32, _OCTETSRXEDTOP>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Received octets in frame without errors

impl W<u32, Reg<u32, _FRAMESRXEDOK>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Frames received without error

impl W<u32, Reg<u32, _BROADCASTRXED>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Broadcast frames received without error

impl W<u32, Reg<u32, _MULTICASTRXED>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Multicast frames received without error

impl W<u32, Reg<u32, _PFRAMESRXED>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Received pause frames

impl W<u32, Reg<u32, _FRAMESRXED64>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 64 byte frames received without error

impl W<u32, Reg<u32, _FRAMESRXED65>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 65 to 127 byte frames received without error

impl W<u32, Reg<u32, _FRAMESRXED128>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 128 to 255 byte frames received without error

impl W<u32, Reg<u32, _FRAMESRXED256>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 256 to 511 byte frames received without error

impl W<u32, Reg<u32, _FRAMESRXED512>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 512 to 1023 byte frames received without error

impl W<u32, Reg<u32, _FRAMESRXED1024>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 1024 to 1518 byte frames received without error

impl W<u32, Reg<u32, _FRAMESRXED1519>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - 1519 to maximum byte frames received without error

impl W<u32, Reg<u32, _UNDERSIZEFRAMES>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Undersize frames received

impl W<u32, Reg<u32, _EXCESSIVERXLEN>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Oversize frames received

impl W<u32, Reg<u32, _RXJABBERS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Jabbers received

impl W<u32, Reg<u32, _FCSERRS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Frame check sequence errors

impl W<u32, Reg<u32, _RXLENERRS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Length field frame errors

impl W<u32, Reg<u32, _RXSYMBOLERRS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Receive symbol errors

impl W<u32, Reg<u32, _ALIGNERRS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Alignment errors

impl W<u32, Reg<u32, _RXRESOURCEERRS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:17 - Receive resource errors

impl W<u32, Reg<u32, _RXOVERRUNS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:9 - Receive overruns

impl W<u32, Reg<u32, _RXIPCKERRS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:7 - IP header checksum errors

impl W<u32, Reg<u32, _RXTCPCKERRS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:7 - TCP checksum errors

impl W<u32, Reg<u32, _RXUDPCKERRS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:7 - UDP checksum errors

impl W<u32, Reg<u32, _AUTOFLUSHEDPKTS>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Flushed RX pkts counter

impl W<u32, Reg<u32, _TSUTIMERINCRSUBNSEC>>

pub fn subnsincr(&mut self) -> SUBNSINCR_W<'_>

Bits 0:15 - MSB [23:8] of the subscript-ns value

pub fn subnsincrlsb(&mut self) -> SUBNSINCRLSB_W<'_>

Bits 24:31 - LSB [7:0] of the subscript-ns value

impl W<u32, Reg<u32, _TSUTIMERMSBSEC>>

pub fn timer(&mut self) -> TIMER_W<'_>

Bits 0:15 - MSB 16 bits of seconds timer count.

impl W<u32, Reg<u32, _TSUTIMERSEC>>

pub fn timer(&mut self) -> TIMER_W<'_>

Bits 0:31 - 1588 Timer Seconds Register

impl W<u32, Reg<u32, _TSUTIMERNSEC>>

pub fn timer(&mut self) -> TIMER_W<'_>

Bits 0:29 - Timer count in nanoseconds

impl W<u32, Reg<u32, _TSUTIMERADJUST>>

pub fn incrementval(&mut self) -> INCREMENTVAL_W<'_>

Bits 0:29 - Timer increment value

pub fn addsubtract(&mut self) -> ADDSUBTRACT_W<'_>

Bit 31 - Write as one to subtract from the 1588 timer

impl W<u32, Reg<u32, _TSUTIMERINCR>>

pub fn nsincrement(&mut self) -> NSINCREMENT_W<'_>

Bits 0:7 - A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle

pub fn altnsincr(&mut self) -> ALTNSINCR_W<'_>

Bits 8:15 - Alternative nanoseconds count

pub fn numincs(&mut self) -> NUMINCS_W<'_>

Bits 16:23 - Number of incs before alt inc

impl W<u32, Reg<u32, _TXPAUSEQUANT1>>

pub fn quantp2(&mut self) -> QUANTP2_W<'_>

Bits 0:15 - Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 2.

pub fn quantp3(&mut self) -> QUANTP3_W<'_>

Bits 16:31 - Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 3.

impl W<u32, Reg<u32, _TXPAUSEQUANT2>>

pub fn quantp4(&mut self) -> QUANTP4_W<'_>

Bits 0:15 - Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 4.

pub fn quantp5(&mut self) -> QUANTP5_W<'_>

Bits 16:31 - Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 5.

impl W<u32, Reg<u32, _TXPAUSEQUANT3>>

pub fn quantp6(&mut self) -> QUANTP6_W<'_>

Bits 0:15 - Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 6.

pub fn quantp7(&mut self) -> QUANTP7_W<'_>

Bits 16:31 - Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 7.

impl W<u32, Reg<u32, _RXLPI>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Count of RX LPI transitions

impl W<u32, Reg<u32, _RXLPITIME>>

pub fn lpitime(&mut self) -> LPITIME_W<'_>

Bits 0:23 - Time in LPI

impl W<u32, Reg<u32, _TXLPI>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Count of LPI transmitions

impl W<u32, Reg<u32, _TXLPITIME>>

pub fn lpitime(&mut self) -> LPITIME_W<'_>

Bits 0:23 - Time in LPI

impl W<u32, Reg<u32, _TXBDCTRL>>

pub fn txbdtsmode(&mut self) -> TXBDTSMODE_W<'_>

Bits 4:5 - TX Descriptor Timestamp Insertion mode, 00: TS insertion disable, 01: TS inserted for PTP Event Frames only, 10: TS inserted for All PTP Frames only, 11: TS insertion for All Frames

impl W<u32, Reg<u32, _RXBDCTRL>>

pub fn rxbdtsmode(&mut self) -> RXBDTSMODE_W<'_>

Bits 4:5 - RX Descriptor Timestamp Insertion mode, 00: TS insertion disable, 01: TS inserted for PTP Event Frames only, 10: TS inserted for All PTP Frames only, 11: TS insertion for All Frames

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn mdiopen(&mut self) -> MDIOPEN_W<'_>

Bit 0 - MDIO I/O Enable

pub fn miitxerpen(&mut self) -> MIITXERPEN_W<'_>

Bit 1 - MII TX ER I/O Enable

pub fn miirxerpen(&mut self) -> MIIRXERPEN_W<'_>

Bit 2 - MII TX ER I/O Enable

pub fn miipen(&mut self) -> MIIPEN_W<'_>

Bit 3 - MII I/O Enable

pub fn rmiipen(&mut self) -> RMIIPEN_W<'_>

Bit 4 - RMII I/O Enable

pub fn tsutmrtogpen(&mut self) -> TSUTMRTOGPEN_W<'_>

Bit 5 - TSU_TMR_CNT_SEC Output Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn miitxloc(&mut self) -> MIITXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn miirxloc(&mut self) -> MIIRXLOC_W<'_>

Bits 8:13 - I/O Location

pub fn miicrsloc(&mut self) -> MIICRSLOC_W<'_>

Bits 16:21 - I/O Location

pub fn miicolloc(&mut self) -> MIICOLLOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn tsuextclkloc(&mut self) -> TSUEXTCLKLOC_W<'_>

Bits 0:5 - I/O Location

pub fn tsutmrtogloc(&mut self) -> TSUTMRTOGLOC_W<'_>

Bits 8:13 - I/O Location

pub fn mdioloc(&mut self) -> MDIOLOC_W<'_>

Bits 16:21 - I/O Location

pub fn rmiiloc(&mut self) -> RMIILOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn tsuclksel(&mut self) -> TSUCLKSEL_W<'_>

Bits 0:2 - TSU Clock selection value

pub fn tsupresc(&mut self) -> TSUPRESC_W<'_>

Bits 4:7 - Clock division factor of TSUPRESC+1

pub fn miisel(&mut self) -> MIISEL_W<'_>

Bit 8 - MII select signal

pub fn gblclken(&mut self) -> GBLCLKEN_W<'_>

Bit 9 - Global Clock Enable signal for Ethernet clocks tsu_clk, tx_clk, rx_clk and ref_clk

pub fn txrefclksel(&mut self) -> TXREFCLKSEL_W<'_>

Bit 10 - REFCLK source select for RMII_TXD and RMII_TX_EN

impl W<u32, Reg<u32, _SDMASYSADDR>>

pub fn sdmasysaddrarg(&mut self) -> SDMASYSADDRARG_W<'_>

Bits 0:31 - Physical SYS Memory ADDR Used for DMA Transfers or the Second Argument for the Auto CMD23

impl W<u32, Reg<u32, _BLKSIZE>>

pub fn tfrblksize(&mut self) -> TFRBLKSIZE_W<'_>

Bits 0:11 - Transfer Block Size, Specifies the Block Size for Block Data Transfers for CMD17, CMD18, CMD24, CMD25, and CMD53

pub fn hstsdmabufsize(&mut self) -> HSTSDMABUFSIZE_W<'_>

Bits 12:14 - Host SDMA Buffer Size

pub fn blkscntforcurrtfr(&mut self) -> BLKSCNTFORCURRTFR_W<'_>

Bits 16:31 - Blocks Count for Current Transfer

impl W<u32, Reg<u32, _CMDARG1>>

pub fn cmdarg1(&mut self) -> CMDARG1_W<'_>

Bits 0:31 - Command Argument 1

impl W<u32, Reg<u32, _TFRMODE>>

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMA Enable

pub fn blkcnten(&mut self) -> BLKCNTEN_W<'_>

Bit 1 - Block Count Enable

pub fn autocmden(&mut self) -> AUTOCMDEN_W<'_>

Bits 2:3 - Auto Command Enable

pub fn datdirsel(&mut self) -> DATDIRSEL_W<'_>

Bit 4 - Data Transfer Direction Select

pub fn multsingblksel(&mut self) -> MULTSINGBLKSEL_W<'_>

Bit 5 - Multiple or Single Block Data Transfer Selection

pub fn resptypesel(&mut self) -> RESPTYPESEL_W<'_>

Bits 16:17 - Response Type Select

pub fn cmdcrcchken(&mut self) -> CMDCRCCHKEN_W<'_>

Bit 19 - Command CRC Check Enable

pub fn cmdindxchken(&mut self) -> CMDINDXCHKEN_W<'_>

Bit 20 - Command Index Check Enable

pub fn datpressel(&mut self) -> DATPRESSEL_W<'_>

Bit 21 - Data Present Select

pub fn cmdtype(&mut self) -> CMDTYPE_W<'_>

Bits 22:23 - Command Type

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>

Bits 24:29 - Command Index

impl W<u32, Reg<u32, _BUFDATPORT>>

pub fn bufdat(&mut self) -> BUFDAT_W<'_>

Bits 0:31 - Buffer Data

impl W<u32, Reg<u32, _HOSTCTRL1>>

pub fn ledctrl(&mut self) -> LEDCTRL_W<'_>

Bit 0 - LED Control

pub fn dattranwd(&mut self) -> DATTRANWD_W<'_>

Bit 1 - Data Transfer Width 1-bit or 4-bit Mode

pub fn hsen(&mut self) -> HSEN_W<'_>

Bit 2 - High Speed Enable

pub fn dmasel(&mut self) -> DMASEL_W<'_>

Bits 3:4 - DMA Select

pub fn extdattranwd(&mut self) -> EXTDATTRANWD_W<'_>

Bit 5 - Extended Data Transfer Width

pub fn cdtstlvl(&mut self) -> CDTSTLVL_W<'_>

Bit 6 - Card Detect Test Level

pub fn cdsigdet(&mut self) -> CDSIGDET_W<'_>

Bit 7 - Card Detetct Signal Detection

pub fn sdbuspower(&mut self) -> SDBUSPOWER_W<'_>

Bit 8 - SD Bus Power

pub fn sdbusvoltsel(&mut self) -> SDBUSVOLTSEL_W<'_>

Bits 9:11 - SD Bus Voltage Select

pub fn hrdrst(&mut self) -> HRDRST_W<'_>

Bit 12 - Hardware Reset Signal

pub fn stopatblkgapreq(&mut self) -> STOPATBLKGAPREQ_W<'_>

Bit 16 - Stop at Block Gap Request

pub fn continuereq(&mut self) -> CONTINUEREQ_W<'_>

Bit 17 - Continue Request

pub fn rdwaitctrl(&mut self) -> RDWAITCTRL_W<'_>

Bit 18 - Read Wait Control

pub fn intatblkgap(&mut self) -> INTATBLKGAP_W<'_>

Bit 19 - Interrupt at Block Gap

pub fn spimode(&mut self) -> SPIMODE_W<'_>

Bit 20 - SPI Mode Enable

pub fn booten(&mut self) -> BOOTEN_W<'_>

Bit 21 - Boot Enable

pub fn altbooten(&mut self) -> ALTBOOTEN_W<'_>

Bit 22 - Alternate Boot Enable

pub fn bootackchk(&mut self) -> BOOTACKCHK_W<'_>

Bit 23 - Boot Ack Check

pub fn wkupevntenoncardint(&mut self) -> WKUPEVNTENONCARDINT_W<'_>

Bit 24 - Wakeup Event Enable on Card Interrupt

pub fn wkupevntenoncins(&mut self) -> WKUPEVNTENONCINS_W<'_>

Bit 25 - Wakeup Event Enable on SD Card Insertion

pub fn wkupevntenoncrm(&mut self) -> WKUPEVNTENONCRM_W<'_>

Bit 26 - Wakeup Event Enable on SD Card Removal

impl W<u32, Reg<u32, _CLOCKCTRL>>

pub fn intclken(&mut self) -> INTCLKEN_W<'_>

Bit 0 - Internal Clock Enable

pub fn sdclken(&mut self) -> SDCLKEN_W<'_>

Bit 2 - SDIO_CLK Pin Clock Enable

pub fn clkgensel(&mut self) -> CLKGENSEL_W<'_>

Bit 5 - Clock Generator Select

pub fn uppsdclkfre(&mut self) -> UPPSDCLKFRE_W<'_>

Bits 6:7 - Upper Bits of SD_CLK Frequency Select

pub fn sdclkfreqsel(&mut self) -> SDCLKFREQSEL_W<'_>

Bits 8:15 - SD_CLK Frequency Select

pub fn dattoutcntval(&mut self) -> DATTOUTCNTVAL_W<'_>

Bits 16:19 - Data Timeout Counter Value

pub fn sftrsta(&mut self) -> SFTRSTA_W<'_>

Bit 24 - Software Reset for All

pub fn sftrstcmd(&mut self) -> SFTRSTCMD_W<'_>

Bit 25 - Software Reset for CMD Line

pub fn sftrstdat(&mut self) -> SFTRSTDAT_W<'_>

Bit 26 - Software Reset for DAT Line

impl W<u32, Reg<u32, _IFCR>>

pub fn cmdcom(&mut self) -> CMDCOM_W<'_>

Bit 0 - Command Complete

pub fn trancom(&mut self) -> TRANCOM_W<'_>

Bit 1 - Transfer Complete

pub fn blkgapevt(&mut self) -> BLKGAPEVT_W<'_>

Bit 2 - Block Gap Event

pub fn dmaint(&mut self) -> DMAINT_W<'_>

Bit 3 - DMA Interrupt

pub fn bfrwrrdy(&mut self) -> BFRWRRDY_W<'_>

Bit 4 - Buffer Write Ready

pub fn bfrrdrdy(&mut self) -> BFRRDRDY_W<'_>

Bit 5 - Buffer Read Ready

pub fn cardins(&mut self) -> CARDINS_W<'_>

Bit 6 - Card Insertion

pub fn cardrm(&mut self) -> CARDRM_W<'_>

Bit 7 - Card Removal

pub fn bootackrcv(&mut self) -> BOOTACKRCV_W<'_>

Bit 13 - Boot Ack Received

pub fn bootterminate(&mut self) -> BOOTTERMINATE_W<'_>

Bit 14 - Boot Terminate Interrupt

pub fn cmdtouterr(&mut self) -> CMDTOUTERR_W<'_>

Bit 16 - Command Timeout Error

pub fn cmdcrcerr(&mut self) -> CMDCRCERR_W<'_>

Bit 17 - CMD CRC Error

pub fn cmdendbiterr(&mut self) -> CMDENDBITERR_W<'_>

Bit 18 - Command End Bit Error

pub fn cmdindexerr(&mut self) -> CMDINDEXERR_W<'_>

Bit 19 - Command Index Error

pub fn dattouterr(&mut self) -> DATTOUTERR_W<'_>

Bit 20 - Data Time-out Error

pub fn datcrcerr(&mut self) -> DATCRCERR_W<'_>

Bit 21 - Data CRC Error

pub fn datendbiterr(&mut self) -> DATENDBITERR_W<'_>

Bit 22 - Data End Bit Error

pub fn currentlimiterr(&mut self) -> CURRENTLIMITERR_W<'_>

Bit 23 - Current Limit Error

pub fn autocmderr(&mut self) -> AUTOCMDERR_W<'_>

Bit 24 - Auto CMD Error

pub fn admaerr(&mut self) -> ADMAERR_W<'_>

Bit 25 - ADMA Error

pub fn targetresp(&mut self) -> TARGETRESP_W<'_>

Bit 28 - Specific Error STAT

impl W<u32, Reg<u32, _IFENC>>

pub fn cmdcomen(&mut self) -> CMDCOMEN_W<'_>

Bit 0 - Command Complete Signal Enable

pub fn trancomen(&mut self) -> TRANCOMEN_W<'_>

Bit 1 - Transfer Complete Signal Enable

pub fn blkgapevten(&mut self) -> BLKGAPEVTEN_W<'_>

Bit 2 - Block Gap Event Signal Enable

pub fn dmainten(&mut self) -> DMAINTEN_W<'_>

Bit 3 - DMA Interrupt Signal Enable

pub fn bufwrrdyen(&mut self) -> BUFWRRDYEN_W<'_>

Bit 4 - Buffer Write Ready Signal Enable

pub fn bufrdrdyen(&mut self) -> BUFRDRDYEN_W<'_>

Bit 5 - Buffer Read Ready Signal Enable

pub fn cardinsen(&mut self) -> CARDINSEN_W<'_>

Bit 6 - Card Insertion Signal Enable

pub fn cardrmen(&mut self) -> CARDRMEN_W<'_>

Bit 7 - Card Removal Signal Enable

pub fn cardinten(&mut self) -> CARDINTEN_W<'_>

Bit 8 - Card Interrupt Signal Enable

pub fn retuningevten(&mut self) -> RETUNINGEVTEN_W<'_>

Bit 12 - Re-Tunning Event Signal Enable

pub fn bootackrcven(&mut self) -> BOOTACKRCVEN_W<'_>

Bit 13 - Boot Ack Received Signal Enable

pub fn bootterminateen(&mut self) -> BOOTTERMINATEEN_W<'_>

Bit 14 - Boot Terminate Interrupt Signal Enable

pub fn cmdtouterren(&mut self) -> CMDTOUTERREN_W<'_>

Bit 16 - Command Time-out Error Status Enable

pub fn cmdcrcerren(&mut self) -> CMDCRCERREN_W<'_>

Bit 17 - Command CRC Error Status Enable

pub fn cmdendbiterren(&mut self) -> CMDENDBITERREN_W<'_>

Bit 18 - Command End Bit Error Status Enable

pub fn cmdindexerren(&mut self) -> CMDINDEXERREN_W<'_>

Bit 19 - Command Index Error Status Enable

pub fn dattouterren(&mut self) -> DATTOUTERREN_W<'_>

Bit 20 - Data Timeout Error Status Enable

pub fn datcrcerren(&mut self) -> DATCRCERREN_W<'_>

Bit 21 - Data CRC Error Status Enable

pub fn datendbiterren(&mut self) -> DATENDBITERREN_W<'_>

Bit 22 - Data End Bit Error Status Enable

pub fn currentlimiterren(&mut self) -> CURRENTLIMITERREN_W<'_>

Bit 23 - Current Limit Error Status Enable

pub fn autocmderren(&mut self) -> AUTOCMDERREN_W<'_>

Bit 24 - Auto CMD12 Error Status Enable

pub fn admaerren(&mut self) -> ADMAERREN_W<'_>

Bit 25 - ADMA Error Status Enable

pub fn tuningerren(&mut self) -> TUNINGERREN_W<'_>

Bit 26 - Tuning Error Status Enable

pub fn targetrespen(&mut self) -> TARGETRESPEN_W<'_>

Bit 28 - Target Response/Host Error Status Enable

impl W<u32, Reg<u32, _IEN>>

pub fn cmdcomsen(&mut self) -> CMDCOMSEN_W<'_>

Bit 0 - Command Complete Signal Enable

pub fn trancomsen(&mut self) -> TRANCOMSEN_W<'_>

Bit 1 - Transfer Complete Signal Enable

pub fn blkgapevtsen(&mut self) -> BLKGAPEVTSEN_W<'_>

Bit 2 - Block Gap Event Signal Enable

pub fn dmaintsen(&mut self) -> DMAINTSEN_W<'_>

Bit 3 - DMA Interrupt Signal Enable

pub fn bufwrrdysen(&mut self) -> BUFWRRDYSEN_W<'_>

Bit 4 - Buffer Write Ready Signal Enable

pub fn bufrdrdysen(&mut self) -> BUFRDRDYSEN_W<'_>

Bit 5 - Buffer Read Ready Signal Enable

pub fn cardinssen(&mut self) -> CARDINSSEN_W<'_>

Bit 6 - Card Insertion Signal Enable

pub fn cardremsen(&mut self) -> CARDREMSEN_W<'_>

Bit 7 - Card Removal Signal Enable

pub fn cardintsen(&mut self) -> CARDINTSEN_W<'_>

Bit 8 - Card Interrupt Signal Enable

pub fn retuningevtsen(&mut self) -> RETUNINGEVTSEN_W<'_>

Bit 12 - Re-Tuning Event Signal Enable

pub fn bootackrcvsen(&mut self) -> BOOTACKRCVSEN_W<'_>

Bit 13 - Boot Ack Received Signal Enable

pub fn bootterminatesen(&mut self) -> BOOTTERMINATESEN_W<'_>

Bit 14 - Boot Terminate Interrupt Signal Enable

pub fn cmdtouterrsen(&mut self) -> CMDTOUTERRSEN_W<'_>

Bit 16 - Command Timeout Error Signal Enable

pub fn cmdcrcerrsen(&mut self) -> CMDCRCERRSEN_W<'_>

Bit 17 - Command CRC Error Signal Enable

pub fn cmdendbiterrsen(&mut self) -> CMDENDBITERRSEN_W<'_>

Bit 18 - Command End Bit Error Signal Enable

pub fn cmdindexerrsen(&mut self) -> CMDINDEXERRSEN_W<'_>

Bit 19 - Command Index Error Signal Enable

pub fn dattouterrsen(&mut self) -> DATTOUTERRSEN_W<'_>

Bit 20 - Data Timeout Error Signal Enable

pub fn datcrcerrsen(&mut self) -> DATCRCERRSEN_W<'_>

Bit 21 - Data CRC Error Signal Enable

pub fn datendbiterrsen(&mut self) -> DATENDBITERRSEN_W<'_>

Bit 22 - Data End Bit Error Signal Enable

pub fn currentlimiterrsen(&mut self) -> CURRENTLIMITERRSEN_W<'_>

Bit 23 - Current Limit Error Signal Enable

pub fn autocmderrsen(&mut self) -> AUTOCMDERRSEN_W<'_>

Bit 24 - Auto CMD12 Error Signal Enable

pub fn admaerrsen(&mut self) -> ADMAERRSEN_W<'_>

Bit 25 - ADMA Error Signal Enable

pub fn tuningerrsignalenable(&mut self) -> TUNINGERRSIGNALENABLE_W<'_>

Bit 26 - Tuning Error Signal Enable

pub fn targetresperrsen(&mut self) -> TARGETRESPERRSEN_W<'_>

Bit 28 - Target Response Error Signal Enable

impl W<u32, Reg<u32, _AC12ERRSTAT>>

pub fn uhsmodesel(&mut self) -> UHSMODESEL_W<'_>

Bits 16:18 - UHS Mode Select

pub fn sigen1p8v(&mut self) -> SIGEN1P8V_W<'_>

Bit 19 - Voltage 1.8V Signal Enable

pub fn drvstnsel(&mut self) -> DRVSTNSEL_W<'_>

Bits 20:21 - Driver Strength Select

pub fn exetuning(&mut self) -> EXETUNING_W<'_>

Bit 22 - Execute Tuning

pub fn sampclksel(&mut self) -> SAMPCLKSEL_W<'_>

Bit 23 - Sampling Clock Select

pub fn asyncinten(&mut self) -> ASYNCINTEN_W<'_>

Bit 30 - Asynchronous Interrupt Enable

pub fn prstvalen(&mut self) -> PRSTVALEN_W<'_>

Bit 31 - Preset Value Enable

impl W<u32, Reg<u32, _FEVTERRSTAT>>

pub fn ac12nex(&mut self) -> AC12NEX_W<'_>

Bit 0 - Force Event for Command Not Issued By Auto CM12 Not Executed

pub fn ac12toe(&mut self) -> AC12TOE_W<'_>

Bit 1 - Force Event for Auto CMD Timeout Error

pub fn ac12crce(&mut self) -> AC12CRCE_W<'_>

Bit 2 - Force Event for Auto CMD CRC Error

pub fn ac12ebe(&mut self) -> AC12EBE_W<'_>

Bit 3 - Force Event for Auto CMD End Bit Error

pub fn ac12indxe(&mut self) -> AC12INDXE_W<'_>

Bit 4 - Force Event for Auto CMD Index Error

pub fn cnibac12e(&mut self) -> CNIBAC12E_W<'_>

Bit 7 - Force Event for Command Not Issued By Auto CMD12 Error

pub fn cmdtoe(&mut self) -> CMDTOE_W<'_>

Bit 16 - Force Event for Command Timeout Error

pub fn cmdcrce(&mut self) -> CMDCRCE_W<'_>

Bit 17 - Force Event for Command CRC Error

pub fn cmdebe(&mut self) -> CMDEBE_W<'_>

Bit 18 - Force Event for Command End Bit Error

pub fn cmdindxe(&mut self) -> CMDINDXE_W<'_>

Bit 19 - Force Event for Command Index Error

pub fn dattoe(&mut self) -> DATTOE_W<'_>

Bit 20 - Force Event for Data Timeout Error

pub fn datcrce(&mut self) -> DATCRCE_W<'_>

Bit 21 - Force Event for Data CRC Error

pub fn datebe(&mut self) -> DATEBE_W<'_>

Bit 22 - Force Event for Data End Bit Error

pub fn curlimite(&mut self) -> CURLIMITE_W<'_>

Bit 23 - Force Event for Current Limit Error

pub fn ac12e(&mut self) -> AC12E_W<'_>

Bit 24 - Force Event for Auto CMD Error

pub fn admae(&mut self) -> ADMAE_W<'_>

Bit 25 - Force Event for ADMA Error

impl W<u32, Reg<u32, _ADSADDR>>

pub fn adsaddr(&mut self) -> ADSADDR_W<'_>

Bits 0:31 - ADMA System Address

impl W<u32, Reg<u32, _BOOTTOCTRL>>

pub fn bootdattocnt(&mut self) -> BOOTDATTOCNT_W<'_>

Bits 0:31 - Boot Data Timeout Counter Value

impl W<u32, Reg<u32, _CTRL>>

pub fn itapdlyen(&mut self) -> ITAPDLYEN_W<'_>

Bit 0 - Selective Tap Delay Line Enable on Rxclk_in

pub fn itapdlysel(&mut self) -> ITAPDLYSEL_W<'_>

Bits 1:5 - Selects One of 32 Taps on the Rxclk_in Line

pub fn itapchgwin(&mut self) -> ITAPCHGWIN_W<'_>

Bit 6 - Gating Signal for Tap Delay Change

pub fn otapdlyen(&mut self) -> OTAPDLYEN_W<'_>

Bit 7 - Selective Tap Delay Line Enable on SDIO_CLK Pin

pub fn otapdlysel(&mut self) -> OTAPDLYSEL_W<'_>

Bits 8:11 - Selects One of 32 Taps on the SDIO_CLK Pin

pub fn txdlymuxsel(&mut self) -> TXDLYMUXSEL_W<'_>

Bits 16:17 - TX Delay Mux Selection

impl W<u32, Reg<u32, _CFG0>>

pub fn tuningcnt(&mut self) -> TUNINGCNT_W<'_>

Bits 0:5 - Tuning Counter Value

pub fn toutclkfreq(&mut self) -> TOUTCLKFREQ_W<'_>

Bits 6:11 - Timeout Clock Frequency

pub fn toutclkunit(&mut self) -> TOUTCLKUNIT_W<'_>

Bit 12 - Timeout Clock Unit in kHz or MHz

pub fn baseclkfreq(&mut self) -> BASECLKFREQ_W<'_>

Bits 13:20 - Base Clock Frequency for SD_CLK

pub fn maxblklen(&mut self) -> MAXBLKLEN_W<'_>

Bits 21:22 - MAX Block Length of Transfer

pub fn c8bitsup(&mut self) -> C8BITSUP_W<'_>

Bit 23 - 8-bit Interface Support

pub fn cadma2sup(&mut self) -> CADMA2SUP_W<'_>

Bit 24 - ADMA2 Mode Support

pub fn chssup(&mut self) -> CHSSUP_W<'_>

Bit 25 - High Speed Mode Support

pub fn csdmasup(&mut self) -> CSDMASUP_W<'_>

Bit 26 - SDMA Mode Support

pub fn csuspressup(&mut self) -> CSUSPRESSUP_W<'_>

Bit 27 - Suspend/Resume Support

pub fn c3p3vsup(&mut self) -> C3P3VSUP_W<'_>

Bit 28 - Core 3P3V Support

pub fn c3p0vsup(&mut self) -> C3P0VSUP_W<'_>

Bit 29 - 3P0V Support

pub fn c1p8vsup(&mut self) -> C1P8VSUP_W<'_>

Bit 30 - 1P8V Support

impl W<u32, Reg<u32, _CFG1>>

pub fn asyncintrsup(&mut self) -> ASYNCINTRSUP_W<'_>

Bit 0 - Asynchronous Interrupt Support

pub fn slottype(&mut self) -> SLOTTYPE_W<'_>

Bits 1:2 - Slot Type

pub fn csdr50sup(&mut self) -> CSDR50SUP_W<'_>

Bit 3 - Core Support SDR50

pub fn csdr104sup(&mut self) -> CSDR104SUP_W<'_>

Bit 4 - Support SDR104

pub fn cddr50sup(&mut self) -> CDDR50SUP_W<'_>

Bit 5 - Support DDR50

pub fn cdrvasup(&mut self) -> CDRVASUP_W<'_>

Bit 6 - Support Type a Driver

pub fn cdrvcsup(&mut self) -> CDRVCSUP_W<'_>

Bit 7 - Support Type C Driver

pub fn cdrvdsup(&mut self) -> CDRVDSUP_W<'_>

Bit 8 - Support Type D Driver

pub fn retuntmrctl(&mut self) -> RETUNTMRCTL_W<'_>

Bits 9:12 - Retuning Timer Control

pub fn tunsdr50(&mut self) -> TUNSDR50_W<'_>

Bit 13 - Tuning for SDR50

pub fn retunmodes(&mut self) -> RETUNMODES_W<'_>

Bits 14:15 - Retuning Modes

pub fn spisup(&mut self) -> SPISUP_W<'_>

Bit 16 - SPI Support

pub fn asyncwkupen(&mut self) -> ASYNCWKUPEN_W<'_>

Bit 18 - Asynchronous Wakeup Enable

impl W<u32, Reg<u32, _CFGPRESETVAL0>>

pub fn initsdclkfreq(&mut self) -> INITSDCLKFREQ_W<'_>

Bits 0:9 - Initial SD_CLK Frequency

pub fn initclkgenen(&mut self) -> INITCLKGENEN_W<'_>

Bit 10 - Initial Clock Gen Enable

pub fn initdrvst(&mut self) -> INITDRVST_W<'_>

Bits 11:12 - Initial Drive Strength

pub fn dspsdclkfreq(&mut self) -> DSPSDCLKFREQ_W<'_>

Bits 16:25 - Preset Value for Default Speed of SD_CLK

pub fn dspclkgenen(&mut self) -> DSPCLKGENEN_W<'_>

Bit 26 - Default Speed Clock Gen Enable

pub fn dspdrvst(&mut self) -> DSPDRVST_W<'_>

Bits 27:28 - Default Speed Drive Strength

impl W<u32, Reg<u32, _CFGPRESETVAL1>>

pub fn hspsdclkfreq(&mut self) -> HSPSDCLKFREQ_W<'_>

Bits 0:9 - High Speed SD_CLK Frequency

pub fn hspclkgenen(&mut self) -> HSPCLKGENEN_W<'_>

Bit 10 - High Speed SD_CLK Gen Enable

pub fn hspdrvst(&mut self) -> HSPDRVST_W<'_>

Bits 11:12 - High Speed SD Drive Strength

pub fn sdr12sdclkfreq(&mut self) -> SDR12SDCLKFREQ_W<'_>

Bits 16:25 - Preset Value for SDR12 Speed of SD_CLK

pub fn sdr12clkgenen(&mut self) -> SDR12CLKGENEN_W<'_>

Bit 26 - SDR12 Speed Clock Gen Enable

pub fn sdr12drvst(&mut self) -> SDR12DRVST_W<'_>

Bits 27:28 - SDR12 Speed Drive Strength

impl W<u32, Reg<u32, _CFGPRESETVAL2>>

pub fn sdr25sdclkfreq(&mut self) -> SDR25SDCLKFREQ_W<'_>

Bits 0:9 - SDR25 SD_CLK Frequency

pub fn sdr25clkgenen(&mut self) -> SDR25CLKGENEN_W<'_>

Bit 10 - SDR25 SD_CLK Gen Enable

pub fn sdr25drvst(&mut self) -> SDR25DRVST_W<'_>

Bits 11:12 - SDR25 SD Drive Strength

pub fn sdr50sdclkfreq(&mut self) -> SDR50SDCLKFREQ_W<'_>

Bits 16:25 - Preset Value for SDR50 Speed of SD_CLK

pub fn sdr50clkgenen(&mut self) -> SDR50CLKGENEN_W<'_>

Bit 26 - SDR50 Speed Clock Gen Enable

pub fn sdr50drvst(&mut self) -> SDR50DRVST_W<'_>

Bits 27:28 - SDR50 Speed Drive Strength

impl W<u32, Reg<u32, _CFGPRESETVAL3>>

pub fn sdr104sdclkfreq(&mut self) -> SDR104SDCLKFREQ_W<'_>

Bits 0:9 - SDR104 SD_CLK Frequency

pub fn sdr104clkgenen(&mut self) -> SDR104CLKGENEN_W<'_>

Bit 10 - SDR104 SD_CLK Gen Enable

pub fn sdr104drvst(&mut self) -> SDR104DRVST_W<'_>

Bits 11:12 - SDR104 SD Drive Strength

pub fn ddr50sdclkfreq(&mut self) -> DDR50SDCLKFREQ_W<'_>

Bits 16:25 - Preset Value for DDR50 Speed of SD_CLK

pub fn ddr50clkgenen(&mut self) -> DDR50CLKGENEN_W<'_>

Bit 26 - DDR50 Speed Clock Gen Enable

pub fn ddr50drvst(&mut self) -> DDR50DRVST_W<'_>

Bits 27:28 - DDR50 Speed Drive Strength

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn datloc(&mut self) -> DATLOC_W<'_>

Bits 0:5 - I/O Location for D0-7 Pins

pub fn cdloc(&mut self) -> CDLOC_W<'_>

Bits 8:13 - I/O Location for CD

pub fn wploc(&mut self) -> WPLOC_W<'_>

Bits 16:21 - I/O Location for WP

pub fn clkloc(&mut self) -> CLKLOC_W<'_>

Bits 24:29 - I/O Location for CLK

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn cmdloc(&mut self) -> CMDLOC_W<'_>

Bits 0:5 - I/O Location for CMD Pin

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn clkpen(&mut self) -> CLKPEN_W<'_>

Bit 0 - CLK I/O Enable

pub fn cmdpen(&mut self) -> CMDPEN_W<'_>

Bit 1 - CMD I/O Enable

pub fn d0pen(&mut self) -> D0PEN_W<'_>

Bit 2 - Dat0 I/O Enable

pub fn d1pen(&mut self) -> D1PEN_W<'_>

Bit 3 - Dat1 I/O Enable

pub fn d2pen(&mut self) -> D2PEN_W<'_>

Bit 4 - Dat2 I/O Enable

pub fn d3pen(&mut self) -> D3PEN_W<'_>

Bit 5 - Dat3 I/O Enable

pub fn d4pen(&mut self) -> D4PEN_W<'_>

Bit 6 - Dat4 I/O Enable

pub fn d5pen(&mut self) -> D5PEN_W<'_>

Bit 7 - Dat5 Enable

pub fn d6pen(&mut self) -> D6PEN_W<'_>

Bit 8 - Dat6 Enable

pub fn d7pen(&mut self) -> D7PEN_W<'_>

Bit 9 - Data7 I/O Enable

impl W<u32, Reg<u32, _PA_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PA_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PA_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PA_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PA_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PA_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PA_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PB_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PB_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PB_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PB_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PB_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PB_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PB_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PC_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PC_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PC_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PC_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PC_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PC_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PC_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PD_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PD_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PD_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PD_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PD_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PD_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PD_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PE_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PE_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PE_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PE_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PE_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PE_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PE_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PF_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PF_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PF_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PF_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PF_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PF_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PF_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PG_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PG_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PG_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PG_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PG_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PG_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PG_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PH_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PH_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PH_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PH_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PH_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PH_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PH_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PI_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PI_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PI_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PI_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PI_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PI_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PI_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PJ_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PJ_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PJ_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PJ_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PJ_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PJ_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PJ_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PK_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PK_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PK_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PK_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PK_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PK_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PK_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PL_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PL_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PL_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PL_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PL_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PL_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PL_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _EXTIPSELL>>

pub fn extipsel0(&mut self) -> EXTIPSEL0_W<'_>

Bits 0:3 - External Interrupt 0 Port Select

pub fn extipsel1(&mut self) -> EXTIPSEL1_W<'_>

Bits 4:7 - External Interrupt 1 Port Select

pub fn extipsel2(&mut self) -> EXTIPSEL2_W<'_>

Bits 8:11 - External Interrupt 2 Port Select

pub fn extipsel3(&mut self) -> EXTIPSEL3_W<'_>

Bits 12:15 - External Interrupt 3 Port Select

pub fn extipsel4(&mut self) -> EXTIPSEL4_W<'_>

Bits 16:19 - External Interrupt 4 Port Select

pub fn extipsel5(&mut self) -> EXTIPSEL5_W<'_>

Bits 20:23 - External Interrupt 5 Port Select

pub fn extipsel6(&mut self) -> EXTIPSEL6_W<'_>

Bits 24:27 - External Interrupt 6 Port Select

pub fn extipsel7(&mut self) -> EXTIPSEL7_W<'_>

Bits 28:31 - External Interrupt 7 Port Select

impl W<u32, Reg<u32, _EXTIPSELH>>

pub fn extipsel8(&mut self) -> EXTIPSEL8_W<'_>

Bits 0:3 - External Interrupt 8 Port Select

pub fn extipsel9(&mut self) -> EXTIPSEL9_W<'_>

Bits 4:7 - External Interrupt 9 Port Select

pub fn extipsel10(&mut self) -> EXTIPSEL10_W<'_>

Bits 8:11 - External Interrupt 10 Port Select

pub fn extipsel11(&mut self) -> EXTIPSEL11_W<'_>

Bits 12:15 - External Interrupt 11 Port Select

pub fn extipsel12(&mut self) -> EXTIPSEL12_W<'_>

Bits 16:19 - External Interrupt 12 Port Select

pub fn extipsel13(&mut self) -> EXTIPSEL13_W<'_>

Bits 20:23 - External Interrupt 13 Port Select

pub fn extipsel14(&mut self) -> EXTIPSEL14_W<'_>

Bits 24:27 - External Interrupt 14 Port Select

pub fn extipsel15(&mut self) -> EXTIPSEL15_W<'_>

Bits 28:31 - External Interrupt 15 Port Select

impl W<u32, Reg<u32, _EXTIPINSELL>>

pub fn extipinsel0(&mut self) -> EXTIPINSEL0_W<'_>

Bits 0:1 - External Interrupt 0 Pin Select

pub fn extipinsel1(&mut self) -> EXTIPINSEL1_W<'_>

Bits 4:5 - External Interrupt 1 Pin Select

pub fn extipinsel2(&mut self) -> EXTIPINSEL2_W<'_>

Bits 8:9 - External Interrupt 2 Pin Select

pub fn extipinsel3(&mut self) -> EXTIPINSEL3_W<'_>

Bits 12:13 - External Interrupt 3 Pin Select

pub fn extipinsel4(&mut self) -> EXTIPINSEL4_W<'_>

Bits 16:17 - External Interrupt 4 Pin Select

pub fn extipinsel5(&mut self) -> EXTIPINSEL5_W<'_>

Bits 20:21 - External Interrupt 5 Pin Select

pub fn extipinsel6(&mut self) -> EXTIPINSEL6_W<'_>

Bits 24:25 - External Interrupt 6 Pin Select

pub fn extipinsel7(&mut self) -> EXTIPINSEL7_W<'_>

Bits 28:29 - External Interrupt 7 Pin Select

impl W<u32, Reg<u32, _EXTIPINSELH>>

pub fn extipinsel8(&mut self) -> EXTIPINSEL8_W<'_>

Bits 0:1 - External Interrupt 8 Pin Select

pub fn extipinsel9(&mut self) -> EXTIPINSEL9_W<'_>

Bits 4:5 - External Interrupt 9 Pin Select

pub fn extipinsel10(&mut self) -> EXTIPINSEL10_W<'_>

Bits 8:9 - External Interrupt 10 Pin Select

pub fn extipinsel11(&mut self) -> EXTIPINSEL11_W<'_>

Bits 12:13 - External Interrupt 11 Pin Select

pub fn extipinsel12(&mut self) -> EXTIPINSEL12_W<'_>

Bits 16:17 - External Interrupt 12 Pin Select

pub fn extipinsel13(&mut self) -> EXTIPINSEL13_W<'_>

Bits 20:21 - External Interrupt 13 Pin Select

pub fn extipinsel14(&mut self) -> EXTIPINSEL14_W<'_>

Bits 24:25 - External Interrupt 14 Pin Select

pub fn extipinsel15(&mut self) -> EXTIPINSEL15_W<'_>

Bits 28:29 - External Interrupt 15 Pin Select

impl W<u32, Reg<u32, _EXTIRISE>>

pub fn extirise(&mut self) -> EXTIRISE_W<'_>

Bits 0:15 - External Interrupt N Rising Edge Trigger Enable

impl W<u32, Reg<u32, _EXTIFALL>>

pub fn extifall(&mut self) -> EXTIFALL_W<'_>

Bits 0:15 - External Interrupt N Falling Edge Trigger Enable

impl W<u32, Reg<u32, _EXTILEVEL>>

pub fn em4wu0(&mut self) -> EM4WU0_W<'_>

Bit 16 - EM4 Wake Up Level for EM4WU0 Pin

pub fn em4wu1(&mut self) -> EM4WU1_W<'_>

Bit 17 - EM4 Wake Up Level for EM4WU1 Pin

pub fn em4wu2(&mut self) -> EM4WU2_W<'_>

Bit 18 - EM4 Wake Up Level for EM4WU2 Pin

pub fn em4wu3(&mut self) -> EM4WU3_W<'_>

Bit 19 - EM4 Wake Up Level for EM4WU3 Pin

pub fn em4wu4(&mut self) -> EM4WU4_W<'_>

Bit 20 - EM4 Wake Up Level for EM4WU4 Pin

pub fn em4wu5(&mut self) -> EM4WU5_W<'_>

Bit 21 - EM4 Wake Up Level for EM4WU5 Pin

pub fn em4wu6(&mut self) -> EM4WU6_W<'_>

Bit 22 - EM4 Wake Up Level for EM4WU6 Pin

pub fn em4wu7(&mut self) -> EM4WU7_W<'_>

Bit 23 - EM4 Wake Up Level for EM4WU7 Pin

pub fn em4wu8(&mut self) -> EM4WU8_W<'_>

Bit 24 - EM4 Wake Up Level for EM4WU8 Pin

pub fn em4wu9(&mut self) -> EM4WU9_W<'_>

Bit 25 - EM4 Wake Up Level for EM4WU9 Pin

impl W<u32, Reg<u32, _IFS>>

pub fn ext(&mut self) -> EXT_W<'_>

Bits 0:15 - Set EXT Interrupt Flag

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bits 16:31 - Set EM4WU Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn ext(&mut self) -> EXT_W<'_>

Bits 0:15 - Clear EXT Interrupt Flag

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bits 16:31 - Clear EM4WU Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn ext(&mut self) -> EXT_W<'_>

Bits 0:15 - EXT Interrupt Enable

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bits 16:31 - EM4WU Interrupt Enable

impl W<u32, Reg<u32, _EM4WUEN>>

pub fn em4wuen(&mut self) -> EM4WUEN_W<'_>

Bits 16:31 - EM4 Wake Up Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn swclktckpen(&mut self) -> SWCLKTCKPEN_W<'_>

Bit 0 - Serial Wire Clock and JTAG Test Clock Pin Enable

pub fn swdiotmspen(&mut self) -> SWDIOTMSPEN_W<'_>

Bit 1 - Serial Wire Data and JTAG Test Mode Select Pin Enable

pub fn tdopen(&mut self) -> TDOPEN_W<'_>

Bit 2 - JTAG Test Debug Output Pin Enable

pub fn tdipen(&mut self) -> TDIPEN_W<'_>

Bit 3 - JTAG Test Debug Input Pin Enable

pub fn swvpen(&mut self) -> SWVPEN_W<'_>

Bit 4 - Serial Wire Viewer Output Pin Enable

pub fn etmtclkpen(&mut self) -> ETMTCLKPEN_W<'_>

Bit 16 - ETM Trace Clock Pin Enable

pub fn etmtd0pen(&mut self) -> ETMTD0PEN_W<'_>

Bit 17 - ETM Trace Data Pin Enable

pub fn etmtd1pen(&mut self) -> ETMTD1PEN_W<'_>

Bit 18 - ETM Trace Data Pin Enable

pub fn etmtd2pen(&mut self) -> ETMTD2PEN_W<'_>

Bit 19 - ETM Trace Data Pin Enable

pub fn etmtd3pen(&mut self) -> ETMTD3PEN_W<'_>

Bit 20 - ETM Trace Data Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn swvloc(&mut self) -> SWVLOC_W<'_>

Bits 0:5 - I/O Location

pub fn etmloc(&mut self) -> ETMLOC_W<'_>

Bits 6:11 - I/O Location

impl W<u32, Reg<u32, _INSENSE>>

pub fn int(&mut self) -> INT_W<'_>

Bit 0 - Interrupt Sense Enable

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bit 1 - EM4WU Interrupt Sense Enable

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock Key

impl W<u32, Reg<u32, _SWPULSE>>

pub fn ch0pulse(&mut self) -> CH0PULSE_W<'_>

Bit 0 - Channel 0 Pulse Generation

pub fn ch1pulse(&mut self) -> CH1PULSE_W<'_>

Bit 1 - Channel 1 Pulse Generation

pub fn ch2pulse(&mut self) -> CH2PULSE_W<'_>

Bit 2 - Channel 2 Pulse Generation

pub fn ch3pulse(&mut self) -> CH3PULSE_W<'_>

Bit 3 - Channel 3 Pulse Generation

pub fn ch4pulse(&mut self) -> CH4PULSE_W<'_>

Bit 4 - Channel 4 Pulse Generation

pub fn ch5pulse(&mut self) -> CH5PULSE_W<'_>

Bit 5 - Channel 5 Pulse Generation

pub fn ch6pulse(&mut self) -> CH6PULSE_W<'_>

Bit 6 - Channel 6 Pulse Generation

pub fn ch7pulse(&mut self) -> CH7PULSE_W<'_>

Bit 7 - Channel 7 Pulse Generation

pub fn ch8pulse(&mut self) -> CH8PULSE_W<'_>

Bit 8 - Channel 8 Pulse Generation

pub fn ch9pulse(&mut self) -> CH9PULSE_W<'_>

Bit 9 - Channel 9 Pulse Generation

pub fn ch10pulse(&mut self) -> CH10PULSE_W<'_>

Bit 10 - Channel 10 Pulse Generation

pub fn ch11pulse(&mut self) -> CH11PULSE_W<'_>

Bit 11 - Channel 11 Pulse Generation

pub fn ch12pulse(&mut self) -> CH12PULSE_W<'_>

Bit 12 - Channel 12 Pulse Generation

pub fn ch13pulse(&mut self) -> CH13PULSE_W<'_>

Bit 13 - Channel 13 Pulse Generation

pub fn ch14pulse(&mut self) -> CH14PULSE_W<'_>

Bit 14 - Channel 14 Pulse Generation

pub fn ch15pulse(&mut self) -> CH15PULSE_W<'_>

Bit 15 - Channel 15 Pulse Generation

pub fn ch16pulse(&mut self) -> CH16PULSE_W<'_>

Bit 16 - Channel 16 Pulse Generation

pub fn ch17pulse(&mut self) -> CH17PULSE_W<'_>

Bit 17 - Channel 17 Pulse Generation

pub fn ch18pulse(&mut self) -> CH18PULSE_W<'_>

Bit 18 - Channel 18 Pulse Generation

pub fn ch19pulse(&mut self) -> CH19PULSE_W<'_>

Bit 19 - Channel 19 Pulse Generation

pub fn ch20pulse(&mut self) -> CH20PULSE_W<'_>

Bit 20 - Channel 20 Pulse Generation

pub fn ch21pulse(&mut self) -> CH21PULSE_W<'_>

Bit 21 - Channel 21 Pulse Generation

pub fn ch22pulse(&mut self) -> CH22PULSE_W<'_>

Bit 22 - Channel 22 Pulse Generation

pub fn ch23pulse(&mut self) -> CH23PULSE_W<'_>

Bit 23 - Channel 23 Pulse Generation

impl W<u32, Reg<u32, _SWLEVEL>>

pub fn ch0level(&mut self) -> CH0LEVEL_W<'_>

Bit 0 - Channel 0 Software Level

pub fn ch1level(&mut self) -> CH1LEVEL_W<'_>

Bit 1 - Channel 1 Software Level

pub fn ch2level(&mut self) -> CH2LEVEL_W<'_>

Bit 2 - Channel 2 Software Level

pub fn ch3level(&mut self) -> CH3LEVEL_W<'_>

Bit 3 - Channel 3 Software Level

pub fn ch4level(&mut self) -> CH4LEVEL_W<'_>

Bit 4 - Channel 4 Software Level

pub fn ch5level(&mut self) -> CH5LEVEL_W<'_>

Bit 5 - Channel 5 Software Level

pub fn ch6level(&mut self) -> CH6LEVEL_W<'_>

Bit 6 - Channel 6 Software Level

pub fn ch7level(&mut self) -> CH7LEVEL_W<'_>

Bit 7 - Channel 7 Software Level

pub fn ch8level(&mut self) -> CH8LEVEL_W<'_>

Bit 8 - Channel 8 Software Level

pub fn ch9level(&mut self) -> CH9LEVEL_W<'_>

Bit 9 - Channel 9 Software Level

pub fn ch10level(&mut self) -> CH10LEVEL_W<'_>

Bit 10 - Channel 10 Software Level

pub fn ch11level(&mut self) -> CH11LEVEL_W<'_>

Bit 11 - Channel 11 Software Level

pub fn ch12level(&mut self) -> CH12LEVEL_W<'_>

Bit 12 - Channel 12 Software Level

pub fn ch13level(&mut self) -> CH13LEVEL_W<'_>

Bit 13 - Channel 13 Software Level

pub fn ch14level(&mut self) -> CH14LEVEL_W<'_>

Bit 14 - Channel 14 Software Level

pub fn ch15level(&mut self) -> CH15LEVEL_W<'_>

Bit 15 - Channel 15 Software Level

pub fn ch16level(&mut self) -> CH16LEVEL_W<'_>

Bit 16 - Channel 16 Software Level

pub fn ch17level(&mut self) -> CH17LEVEL_W<'_>

Bit 17 - Channel 17 Software Level

pub fn ch18level(&mut self) -> CH18LEVEL_W<'_>

Bit 18 - Channel 18 Software Level

pub fn ch19level(&mut self) -> CH19LEVEL_W<'_>

Bit 19 - Channel 19 Software Level

pub fn ch20level(&mut self) -> CH20LEVEL_W<'_>

Bit 20 - Channel 20 Software Level

pub fn ch21level(&mut self) -> CH21LEVEL_W<'_>

Bit 21 - Channel 21 Software Level

pub fn ch22level(&mut self) -> CH22LEVEL_W<'_>

Bit 22 - Channel 22 Software Level

pub fn ch23level(&mut self) -> CH23LEVEL_W<'_>

Bit 23 - Channel 23 Software Level

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn ch0pen(&mut self) -> CH0PEN_W<'_>

Bit 0 - CH0 Pin Enable

pub fn ch1pen(&mut self) -> CH1PEN_W<'_>

Bit 1 - CH1 Pin Enable

pub fn ch2pen(&mut self) -> CH2PEN_W<'_>

Bit 2 - CH2 Pin Enable

pub fn ch3pen(&mut self) -> CH3PEN_W<'_>

Bit 3 - CH3 Pin Enable

pub fn ch4pen(&mut self) -> CH4PEN_W<'_>

Bit 4 - CH4 Pin Enable

pub fn ch5pen(&mut self) -> CH5PEN_W<'_>

Bit 5 - CH5 Pin Enable

pub fn ch6pen(&mut self) -> CH6PEN_W<'_>

Bit 6 - CH6 Pin Enable

pub fn ch7pen(&mut self) -> CH7PEN_W<'_>

Bit 7 - CH7 Pin Enable

pub fn ch8pen(&mut self) -> CH8PEN_W<'_>

Bit 8 - CH8 Pin Enable

pub fn ch9pen(&mut self) -> CH9PEN_W<'_>

Bit 9 - CH9 Pin Enable

pub fn ch10pen(&mut self) -> CH10PEN_W<'_>

Bit 10 - CH10 Pin Enable

pub fn ch11pen(&mut self) -> CH11PEN_W<'_>

Bit 11 - CH11 Pin Enable

pub fn ch12pen(&mut self) -> CH12PEN_W<'_>

Bit 12 - CH12 Pin Enable

pub fn ch13pen(&mut self) -> CH13PEN_W<'_>

Bit 13 - CH13 Pin Enable

pub fn ch14pen(&mut self) -> CH14PEN_W<'_>

Bit 14 - CH14 Pin Enable

pub fn ch15pen(&mut self) -> CH15PEN_W<'_>

Bit 15 - CH15 Pin Enable

pub fn ch16pen(&mut self) -> CH16PEN_W<'_>

Bit 16 - CH16 Pin Enable

pub fn ch17pen(&mut self) -> CH17PEN_W<'_>

Bit 17 - CH17 Pin Enable

pub fn ch18pen(&mut self) -> CH18PEN_W<'_>

Bit 18 - CH18 Pin Enable

pub fn ch19pen(&mut self) -> CH19PEN_W<'_>

Bit 19 - CH19 Pin Enable

pub fn ch20pen(&mut self) -> CH20PEN_W<'_>

Bit 20 - CH20 Pin Enable

pub fn ch21pen(&mut self) -> CH21PEN_W<'_>

Bit 21 - CH21 Pin Enable

pub fn ch22pen(&mut self) -> CH22PEN_W<'_>

Bit 22 - CH22 Pin Enable

pub fn ch23pen(&mut self) -> CH23PEN_W<'_>

Bit 23 - CH23 Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn ch0loc(&mut self) -> CH0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn ch1loc(&mut self) -> CH1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn ch2loc(&mut self) -> CH2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn ch3loc(&mut self) -> CH3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn ch4loc(&mut self) -> CH4LOC_W<'_>

Bits 0:5 - I/O Location

pub fn ch5loc(&mut self) -> CH5LOC_W<'_>

Bits 8:13 - I/O Location

pub fn ch6loc(&mut self) -> CH6LOC_W<'_>

Bits 16:21 - I/O Location

pub fn ch7loc(&mut self) -> CH7LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn ch8loc(&mut self) -> CH8LOC_W<'_>

Bits 0:5 - I/O Location

pub fn ch9loc(&mut self) -> CH9LOC_W<'_>

Bits 8:13 - I/O Location

pub fn ch10loc(&mut self) -> CH10LOC_W<'_>

Bits 16:21 - I/O Location

pub fn ch11loc(&mut self) -> CH11LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC3>>

pub fn ch12loc(&mut self) -> CH12LOC_W<'_>

Bits 0:5 - I/O Location

pub fn ch13loc(&mut self) -> CH13LOC_W<'_>

Bits 8:13 - I/O Location

pub fn ch14loc(&mut self) -> CH14LOC_W<'_>

Bits 16:21 - I/O Location

pub fn ch15loc(&mut self) -> CH15LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC4>>

pub fn ch16loc(&mut self) -> CH16LOC_W<'_>

Bits 0:5 - I/O Location

pub fn ch17loc(&mut self) -> CH17LOC_W<'_>

Bits 8:13 - I/O Location

pub fn ch18loc(&mut self) -> CH18LOC_W<'_>

Bits 16:21 - I/O Location

pub fn ch19loc(&mut self) -> CH19LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC5>>

pub fn ch20loc(&mut self) -> CH20LOC_W<'_>

Bits 0:5 - I/O Location

pub fn ch21loc(&mut self) -> CH21LOC_W<'_>

Bits 8:13 - I/O Location

pub fn ch22loc(&mut self) -> CH22LOC_W<'_>

Bits 16:21 - I/O Location

pub fn ch23loc(&mut self) -> CH23LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn sevonprs(&mut self) -> SEVONPRS_W<'_>

Bit 0 - Set Event on PRS

pub fn sevonprssel(&mut self) -> SEVONPRSSEL_W<'_>

Bits 1:5 - SEVONPRS PRS Channel Select

impl W<u32, Reg<u32, _DMAREQ0>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 6:10 - DMA Request 0 PRS Channel Select

impl W<u32, Reg<u32, _DMAREQ1>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 6:10 - DMA Request 1 PRS Channel Select

impl W<u32, Reg<u32, _CH0_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH1_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH2_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH3_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH4_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH5_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH6_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH7_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH8_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH9_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH10_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH11_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH12_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH13_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH14_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH15_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH16_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH17_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH18_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH19_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH20_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH21_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH22_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH23_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CTRL>>

pub fn syncprsseten(&mut self) -> SYNCPRSSETEN_W<'_>

Bits 0:7 - Synchronization PRS Set Enable

pub fn syncprsclren(&mut self) -> SYNCPRSCLREN_W<'_>

Bits 8:15 - Synchronization PRS Clear Enable

pub fn numfixed(&mut self) -> NUMFIXED_W<'_>

Bits 24:28 - Number of Fixed Priority Channels

impl W<u32, Reg<u32, _SYNC>>

pub fn synctrig(&mut self) -> SYNCTRIG_W<'_>

Bits 0:7 - Synchronization Trigger

impl W<u32, Reg<u32, _CHEN>>

pub fn chen(&mut self) -> CHEN_W<'_>

Bits 0:23 - Channel Enables

impl W<u32, Reg<u32, _CHDONE>>

pub fn chdone(&mut self) -> CHDONE_W<'_>

Bits 0:23 - DMA Channel Linking or Done

impl W<u32, Reg<u32, _DBGHALT>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bits 0:23 - DMA Debug Halt

impl W<u32, Reg<u32, _SWREQ>>

pub fn swreq(&mut self) -> SWREQ_W<'_>

Bits 0:23 - Software Transfer Requests

impl W<u32, Reg<u32, _REQDIS>>

pub fn reqdis(&mut self) -> REQDIS_W<'_>

Bits 0:23 - DMA Request Disables

impl W<u32, Reg<u32, _LINKLOAD>>

pub fn linkload(&mut self) -> LINKLOAD_W<'_>

Bits 0:23 - DMA Link Loads

impl W<u32, Reg<u32, _REQCLEAR>>

pub fn reqclear(&mut self) -> REQCLEAR_W<'_>

Bits 0:23 - DMA Request Clear

impl W<u32, Reg<u32, _IFS>>

pub fn done(&mut self) -> DONE_W<'_>

Bits 0:23 - Set DONE Interrupt Flag

pub fn error(&mut self) -> ERROR_W<'_>

Bit 31 - Set ERROR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn done(&mut self) -> DONE_W<'_>

Bits 0:23 - Clear DONE Interrupt Flag

pub fn error(&mut self) -> ERROR_W<'_>

Bit 31 - Clear ERROR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn done(&mut self) -> DONE_W<'_>

Bits 0:23 - DONE Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 31 - ERROR Interrupt Enable

impl W<u32, Reg<u32, _CH0_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH0_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH0_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH0_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH0_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH0_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH0_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH1_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH1_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH1_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH1_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH1_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH1_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH1_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH2_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH2_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH2_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH2_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH2_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH2_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH2_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH3_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH3_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH3_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH3_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH3_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH3_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH3_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH4_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH4_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH4_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH4_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH4_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH4_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH4_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH5_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH5_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH5_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH5_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH5_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH5_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH5_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH6_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH6_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH6_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH6_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH6_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH6_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH6_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH7_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH7_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH7_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH7_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH7_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH7_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH7_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH8_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH8_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH8_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH8_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH8_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH8_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH8_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH9_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH9_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH9_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH9_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH9_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH9_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH9_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH10_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH10_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH10_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH10_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH10_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH10_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH10_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH11_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH11_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH11_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH11_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH11_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH11_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH11_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH12_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH12_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH12_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH12_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH12_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH12_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH12_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH13_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH13_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH13_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH13_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH13_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH13_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH13_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH14_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH14_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH14_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH14_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH14_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH14_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH14_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH15_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH15_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH15_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH15_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH15_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH15_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH15_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH16_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH16_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH16_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH16_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH16_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH16_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH16_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH17_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH17_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH17_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH17_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH17_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH17_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH17_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH18_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH18_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH18_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH18_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH18_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH18_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH18_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH19_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH19_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH19_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH19_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH19_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH19_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH19_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH20_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH20_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH20_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH20_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH20_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH20_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH20_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH21_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH21_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH21_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH21_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH21_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH21_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH21_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH22_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH22_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH22_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH22_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH22_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH22_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH22_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH23_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH23_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH23_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH23_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH23_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH23_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH23_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _IFS>>

pub fn fpioc(&mut self) -> FPIOC_W<'_>

Bit 0 - Set FPIOC Interrupt Flag

pub fn fpdzc(&mut self) -> FPDZC_W<'_>

Bit 1 - Set FPDZC Interrupt Flag

pub fn fpufc(&mut self) -> FPUFC_W<'_>

Bit 2 - Set FPUFC Interrupt Flag

pub fn fpofc(&mut self) -> FPOFC_W<'_>

Bit 3 - Set FPOFC Interrupt Flag

pub fn fpidc(&mut self) -> FPIDC_W<'_>

Bit 4 - Set FPIDC Interrupt Flag

pub fn fpixc(&mut self) -> FPIXC_W<'_>

Bit 5 - Set FPIXC Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn fpioc(&mut self) -> FPIOC_W<'_>

Bit 0 - Clear FPIOC Interrupt Flag

pub fn fpdzc(&mut self) -> FPDZC_W<'_>

Bit 1 - Clear FPDZC Interrupt Flag

pub fn fpufc(&mut self) -> FPUFC_W<'_>

Bit 2 - Clear FPUFC Interrupt Flag

pub fn fpofc(&mut self) -> FPOFC_W<'_>

Bit 3 - Clear FPOFC Interrupt Flag

pub fn fpidc(&mut self) -> FPIDC_W<'_>

Bit 4 - Clear FPIDC Interrupt Flag

pub fn fpixc(&mut self) -> FPIXC_W<'_>

Bit 5 - Clear FPIXC Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn fpioc(&mut self) -> FPIOC_W<'_>

Bit 0 - FPIOC Interrupt Enable

pub fn fpdzc(&mut self) -> FPDZC_W<'_>

Bit 1 - FPDZC Interrupt Enable

pub fn fpufc(&mut self) -> FPUFC_W<'_>

Bit 2 - FPUFC Interrupt Enable

pub fn fpofc(&mut self) -> FPOFC_W<'_>

Bit 3 - FPOFC Interrupt Enable

pub fn fpidc(&mut self) -> FPIDC_W<'_>

Bit 4 - FPIDC Interrupt Enable

pub fn fpixc(&mut self) -> FPIXC_W<'_>

Bit 5 - FPIXC Interrupt Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - CRC Functionality Enable

pub fn polysel(&mut self) -> POLYSEL_W<'_>

Bit 4 - Polynomial Select

pub fn bytemode(&mut self) -> BYTEMODE_W<'_>

Bit 8 - Byte Mode Enable

pub fn bitreverse(&mut self) -> BITREVERSE_W<'_>

Bit 9 - Byte-level Bit Reverse Enable

pub fn bytereverse(&mut self) -> BYTEREVERSE_W<'_>

Bit 10 - Byte Reverse Mode

pub fn autoinit(&mut self) -> AUTOINIT_W<'_>

Bit 13 - Auto Init Enable

impl W<u32, Reg<u32, _CMD>>

pub fn init(&mut self) -> INIT_W<'_>

Bit 0 - Initialization Enable

impl W<u32, Reg<u32, _INIT>>

pub fn init(&mut self) -> INIT_W<'_>

Bits 0:31 - CRC Initialization Value

impl W<u32, Reg<u32, _POLY>>

pub fn poly(&mut self) -> POLY_W<'_>

Bits 0:15 - CRC Polynomial Value

impl W<u32, Reg<u32, _INPUTDATA>>

pub fn inputdata(&mut self) -> INPUTDATA_W<'_>

Bits 0:31 - Input Data for 32-bit

impl W<u32, Reg<u32, _INPUTDATAHWORD>>

pub fn inputdatahword(&mut self) -> INPUTDATAHWORD_W<'_>

Bits 0:15 - Input Data for 16-bit

impl W<u32, Reg<u32, _INPUTDATABYTE>>

pub fn inputdatabyte(&mut self) -> INPUTDATABYTE_W<'_>

Bits 0:7 - Input Data for 8-bit

impl W<u32, Reg<u32, _CTRL>>

pub fn init(&mut self) -> INIT_W<'_>

Bit 0 - Initialize

pub fn ie(&mut self) -> IE_W<'_>

Bit 1 - Module Interrupt Enable

pub fn sie(&mut self) -> SIE_W<'_>

Bit 2 - Status Change Interrupt Enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 3 - Error Interrupt Enable

pub fn dar(&mut self) -> DAR_W<'_>

Bit 5 - Disable Automatic Retransmission

pub fn cce(&mut self) -> CCE_W<'_>

Bit 6 - Configuration Change Enable

pub fn test(&mut self) -> TEST_W<'_>

Bit 7 - Test Mode Enable Write

impl W<u32, Reg<u32, _STATUS>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 0:2 - Last Error Code

pub fn txok(&mut self) -> TXOK_W<'_>

Bit 3 - Transmitted a Message Successfully

pub fn rxok(&mut self) -> RXOK_W<'_>

Bit 4 - Received a Message Successfully

impl W<u32, Reg<u32, _BITTIMING>>

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:5 - Baud Rate Prescaler

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 6:7 - Synchronization Jump Width

pub fn tseg1(&mut self) -> TSEG1_W<'_>

Bits 8:11 - Time Segment Before the Sample Point

pub fn tseg2(&mut self) -> TSEG2_W<'_>

Bits 12:14 - Time Segment After the Sample Point

impl W<u32, Reg<u32, _TEST>>

pub fn basic(&mut self) -> BASIC_W<'_>

Bit 2 - Basic Mode

pub fn silent(&mut self) -> SILENT_W<'_>

Bit 3 - Silent Mode

pub fn lback(&mut self) -> LBACK_W<'_>

Bit 4 - Loopback Mode

pub fn tx(&mut self) -> TX_W<'_>

Bits 5:6 - Control of CAN_TX Pin

impl W<u32, Reg<u32, _BRPE>>

pub fn brpe(&mut self) -> BRPE_W<'_>

Bits 0:3 - Baud Rate Prescaler Extension

impl W<u32, Reg<u32, _CONFIG>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 15 - Debug Halt

impl W<u32, Reg<u32, _IF0IFS>>

pub fn message(&mut self) -> MESSAGE_W<'_>

Bits 0:31 - Set MESSAGE Interrupt Flag

impl W<u32, Reg<u32, _IF0IFC>>

pub fn message(&mut self) -> MESSAGE_W<'_>

Bits 0:31 - Clear MESSAGE Interrupt Flag

impl W<u32, Reg<u32, _IF0IEN>>

pub fn message(&mut self) -> MESSAGE_W<'_>

Bits 0:31 - MESSAGE Interrupt Enable

impl W<u32, Reg<u32, _IF1IFS>>

pub fn status(&mut self) -> STATUS_W<'_>

Bit 0 - Set STATUS Interrupt Flag

impl W<u32, Reg<u32, _IF1IFC>>

pub fn status(&mut self) -> STATUS_W<'_>

Bit 0 - Clear STATUS Interrupt Flag

impl W<u32, Reg<u32, _IF1IEN>>

pub fn status(&mut self) -> STATUS_W<'_>

Bit 0 - STATUS Interrupt Enable

impl W<u32, Reg<u32, _ROUTE>>

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 0 - TX Pin Enable

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 2:7 - RX Pin Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - TX Pin Location

impl W<u32, Reg<u32, _MIR0_CMDMASK>>

pub fn datab(&mut self) -> DATAB_W<'_>

Bit 0 - CC Channel Mode

pub fn dataa(&mut self) -> DATAA_W<'_>

Bit 1 - Access Data Bytes 0-3

pub fn txrqstnewdat(&mut self) -> TXRQSTNEWDAT_W<'_>

Bit 2 - Transmission Request Bit/ New Data Bit

pub fn clrintpnd(&mut self) -> CLRINTPND_W<'_>

Bit 3 - Clear Interrupt Pending Bit

pub fn control(&mut self) -> CONTROL_W<'_>

Bit 4 - Access Control Bits

pub fn arbacc(&mut self) -> ARBACC_W<'_>

Bit 5 - Access Arbitration Bits

pub fn maskacc(&mut self) -> MASKACC_W<'_>

Bit 6 - Access Mask Bits

pub fn wrrd(&mut self) -> WRRD_W<'_>

Bit 7 - Write/Read RAM

impl W<u32, Reg<u32, _MIR0_MASK>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 0:28 - Identifier Mask

pub fn mdir(&mut self) -> MDIR_W<'_>

Bit 30 - Mask Message Direction

pub fn mxtd(&mut self) -> MXTD_W<'_>

Bit 31 - Mask Extended Identifier

impl W<u32, Reg<u32, _MIR0_ARB>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:28 - Message Identifier

pub fn dir(&mut self) -> DIR_W<'_>

Bit 29 - Message Direction

pub fn xtd(&mut self) -> XTD_W<'_>

Bit 30 - Extended Identifier

pub fn msgval(&mut self) -> MSGVAL_W<'_>

Bit 31 - Message Valid

impl W<u32, Reg<u32, _MIR0_CTRL>>

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - Data Length Code

pub fn eob(&mut self) -> EOB_W<'_>

Bit 7 - End of Buffer

pub fn txrqst(&mut self) -> TXRQST_W<'_>

Bit 8 - Transmit Request

pub fn rmten(&mut self) -> RMTEN_W<'_>

Bit 9 - Remote Enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 10 - Receive Interrupt Enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 11 - Transmit Interrupt Enable

pub fn umask(&mut self) -> UMASK_W<'_>

Bit 12 - Use Acceptance Mask

pub fn intpnd(&mut self) -> INTPND_W<'_>

Bit 13 - Interrupt Pending

pub fn messageof(&mut self) -> MESSAGEOF_W<'_>

Bit 14 - Message Lost (only Valid for Message Objects With Direction = Receive)

pub fn datavalid(&mut self) -> DATAVALID_W<'_>

Bit 15 - New Data

impl W<u32, Reg<u32, _MIR0_DATAL>>

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - First Byte of CAN Data Frame

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - Second Byte of CAN Data Frame

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - Third Byte of CAN Data Frame

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - Fourth Byte of CAN Data Frame

impl W<u32, Reg<u32, _MIR0_DATAH>>

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - Fifth Byte of CAN Data Frame

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - Sixth Byte of CAN Data Frame

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - Seventh Byte of CAN Data Frame

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - Eight Byte of CAN Data Frame

impl W<u32, Reg<u32, _MIR0_CMDREQ>>

pub fn msgnum(&mut self) -> MSGNUM_W<'_>

Bits 0:5 - Message Number

impl W<u32, Reg<u32, _MIR1_CMDMASK>>

pub fn datab(&mut self) -> DATAB_W<'_>

Bit 0 - CC Channel Mode

pub fn dataa(&mut self) -> DATAA_W<'_>

Bit 1 - Access Data Bytes 0-3

pub fn txrqstnewdat(&mut self) -> TXRQSTNEWDAT_W<'_>

Bit 2 - Transmission Request Bit/ New Data Bit

pub fn clrintpnd(&mut self) -> CLRINTPND_W<'_>

Bit 3 - Clear Interrupt Pending Bit

pub fn control(&mut self) -> CONTROL_W<'_>

Bit 4 - Access Control Bits

pub fn arbacc(&mut self) -> ARBACC_W<'_>

Bit 5 - Access Arbitration Bits

pub fn maskacc(&mut self) -> MASKACC_W<'_>

Bit 6 - Access Mask Bits

pub fn wrrd(&mut self) -> WRRD_W<'_>

Bit 7 - Write/Read RAM

impl W<u32, Reg<u32, _MIR1_MASK>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 0:28 - Identifier Mask

pub fn mdir(&mut self) -> MDIR_W<'_>

Bit 30 - Mask Message Direction

pub fn mxtd(&mut self) -> MXTD_W<'_>

Bit 31 - Mask Extended Identifier

impl W<u32, Reg<u32, _MIR1_ARB>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:28 - Message Identifier

pub fn dir(&mut self) -> DIR_W<'_>

Bit 29 - Message Direction

pub fn xtd(&mut self) -> XTD_W<'_>

Bit 30 - Extended Identifier

pub fn msgval(&mut self) -> MSGVAL_W<'_>

Bit 31 - Message Valid

impl W<u32, Reg<u32, _MIR1_CTRL>>

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - Data Length Code

pub fn eob(&mut self) -> EOB_W<'_>

Bit 7 - End of Buffer

pub fn txrqst(&mut self) -> TXRQST_W<'_>

Bit 8 - Transmit Request

pub fn rmten(&mut self) -> RMTEN_W<'_>

Bit 9 - Remote Enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 10 - Receive Interrupt Enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 11 - Transmit Interrupt Enable

pub fn umask(&mut self) -> UMASK_W<'_>

Bit 12 - Use Acceptance Mask

pub fn intpnd(&mut self) -> INTPND_W<'_>

Bit 13 - Interrupt Pending

pub fn messageof(&mut self) -> MESSAGEOF_W<'_>

Bit 14 - Message Lost (only Valid for Message Objects With Direction = Receive)

pub fn datavalid(&mut self) -> DATAVALID_W<'_>

Bit 15 - New Data

impl W<u32, Reg<u32, _MIR1_DATAL>>

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - First Byte of CAN Data Frame

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - Second Byte of CAN Data Frame

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - Third Byte of CAN Data Frame

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - Fourth Byte of CAN Data Frame

impl W<u32, Reg<u32, _MIR1_DATAH>>

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - Fifth Byte of CAN Data Frame

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - Sixth Byte of CAN Data Frame

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - Seventh Byte of CAN Data Frame

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - Eight Byte of CAN Data Frame

impl W<u32, Reg<u32, _MIR1_CMDREQ>>

pub fn msgnum(&mut self) -> MSGNUM_W<'_>

Bits 0:5 - Message Number

impl W<u32, Reg<u32, _CTRL>>

pub fn init(&mut self) -> INIT_W<'_>

Bit 0 - Initialize

pub fn ie(&mut self) -> IE_W<'_>

Bit 1 - Module Interrupt Enable

pub fn sie(&mut self) -> SIE_W<'_>

Bit 2 - Status Change Interrupt Enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 3 - Error Interrupt Enable

pub fn dar(&mut self) -> DAR_W<'_>

Bit 5 - Disable Automatic Retransmission

pub fn cce(&mut self) -> CCE_W<'_>

Bit 6 - Configuration Change Enable

pub fn test(&mut self) -> TEST_W<'_>

Bit 7 - Test Mode Enable Write

impl W<u32, Reg<u32, _STATUS>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 0:2 - Last Error Code

pub fn txok(&mut self) -> TXOK_W<'_>

Bit 3 - Transmitted a Message Successfully

pub fn rxok(&mut self) -> RXOK_W<'_>

Bit 4 - Received a Message Successfully

impl W<u32, Reg<u32, _BITTIMING>>

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:5 - Baud Rate Prescaler

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 6:7 - Synchronization Jump Width

pub fn tseg1(&mut self) -> TSEG1_W<'_>

Bits 8:11 - Time Segment Before the Sample Point

pub fn tseg2(&mut self) -> TSEG2_W<'_>

Bits 12:14 - Time Segment After the Sample Point

impl W<u32, Reg<u32, _TEST>>

pub fn basic(&mut self) -> BASIC_W<'_>

Bit 2 - Basic Mode

pub fn silent(&mut self) -> SILENT_W<'_>

Bit 3 - Silent Mode

pub fn lback(&mut self) -> LBACK_W<'_>

Bit 4 - Loopback Mode

pub fn tx(&mut self) -> TX_W<'_>

Bits 5:6 - Control of CAN_TX Pin

impl W<u32, Reg<u32, _BRPE>>

pub fn brpe(&mut self) -> BRPE_W<'_>

Bits 0:3 - Baud Rate Prescaler Extension

impl W<u32, Reg<u32, _CONFIG>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 15 - Debug Halt

impl W<u32, Reg<u32, _IF0IFS>>

pub fn message(&mut self) -> MESSAGE_W<'_>

Bits 0:31 - Set MESSAGE Interrupt Flag

impl W<u32, Reg<u32, _IF0IFC>>

pub fn message(&mut self) -> MESSAGE_W<'_>

Bits 0:31 - Clear MESSAGE Interrupt Flag

impl W<u32, Reg<u32, _IF0IEN>>

pub fn message(&mut self) -> MESSAGE_W<'_>

Bits 0:31 - MESSAGE Interrupt Enable

impl W<u32, Reg<u32, _IF1IFS>>

pub fn status(&mut self) -> STATUS_W<'_>

Bit 0 - Set STATUS Interrupt Flag

impl W<u32, Reg<u32, _IF1IFC>>

pub fn status(&mut self) -> STATUS_W<'_>

Bit 0 - Clear STATUS Interrupt Flag

impl W<u32, Reg<u32, _IF1IEN>>

pub fn status(&mut self) -> STATUS_W<'_>

Bit 0 - STATUS Interrupt Enable

impl W<u32, Reg<u32, _ROUTE>>

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 0 - TX Pin Enable

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 2:7 - RX Pin Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - TX Pin Location

impl W<u32, Reg<u32, _MIR0_CMDMASK>>

pub fn datab(&mut self) -> DATAB_W<'_>

Bit 0 - CC Channel Mode

pub fn dataa(&mut self) -> DATAA_W<'_>

Bit 1 - Access Data Bytes 0-3

pub fn txrqstnewdat(&mut self) -> TXRQSTNEWDAT_W<'_>

Bit 2 - Transmission Request Bit/ New Data Bit

pub fn clrintpnd(&mut self) -> CLRINTPND_W<'_>

Bit 3 - Clear Interrupt Pending Bit

pub fn control(&mut self) -> CONTROL_W<'_>

Bit 4 - Access Control Bits

pub fn arbacc(&mut self) -> ARBACC_W<'_>

Bit 5 - Access Arbitration Bits

pub fn maskacc(&mut self) -> MASKACC_W<'_>

Bit 6 - Access Mask Bits

pub fn wrrd(&mut self) -> WRRD_W<'_>

Bit 7 - Write/Read RAM

impl W<u32, Reg<u32, _MIR0_MASK>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 0:28 - Identifier Mask

pub fn mdir(&mut self) -> MDIR_W<'_>

Bit 30 - Mask Message Direction

pub fn mxtd(&mut self) -> MXTD_W<'_>

Bit 31 - Mask Extended Identifier

impl W<u32, Reg<u32, _MIR0_ARB>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:28 - Message Identifier

pub fn dir(&mut self) -> DIR_W<'_>

Bit 29 - Message Direction

pub fn xtd(&mut self) -> XTD_W<'_>

Bit 30 - Extended Identifier

pub fn msgval(&mut self) -> MSGVAL_W<'_>

Bit 31 - Message Valid

impl W<u32, Reg<u32, _MIR0_CTRL>>

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - Data Length Code

pub fn eob(&mut self) -> EOB_W<'_>

Bit 7 - End of Buffer

pub fn txrqst(&mut self) -> TXRQST_W<'_>

Bit 8 - Transmit Request

pub fn rmten(&mut self) -> RMTEN_W<'_>

Bit 9 - Remote Enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 10 - Receive Interrupt Enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 11 - Transmit Interrupt Enable

pub fn umask(&mut self) -> UMASK_W<'_>

Bit 12 - Use Acceptance Mask

pub fn intpnd(&mut self) -> INTPND_W<'_>

Bit 13 - Interrupt Pending

pub fn messageof(&mut self) -> MESSAGEOF_W<'_>

Bit 14 - Message Lost (only Valid for Message Objects With Direction = Receive)

pub fn datavalid(&mut self) -> DATAVALID_W<'_>

Bit 15 - New Data

impl W<u32, Reg<u32, _MIR0_DATAL>>

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - First Byte of CAN Data Frame

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - Second Byte of CAN Data Frame

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - Third Byte of CAN Data Frame

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - Fourth Byte of CAN Data Frame

impl W<u32, Reg<u32, _MIR0_DATAH>>

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - Fifth Byte of CAN Data Frame

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - Sixth Byte of CAN Data Frame

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - Seventh Byte of CAN Data Frame

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - Eight Byte of CAN Data Frame

impl W<u32, Reg<u32, _MIR0_CMDREQ>>

pub fn msgnum(&mut self) -> MSGNUM_W<'_>

Bits 0:5 - Message Number

impl W<u32, Reg<u32, _MIR1_CMDMASK>>

pub fn datab(&mut self) -> DATAB_W<'_>

Bit 0 - CC Channel Mode

pub fn dataa(&mut self) -> DATAA_W<'_>

Bit 1 - Access Data Bytes 0-3

pub fn txrqstnewdat(&mut self) -> TXRQSTNEWDAT_W<'_>

Bit 2 - Transmission Request Bit/ New Data Bit

pub fn clrintpnd(&mut self) -> CLRINTPND_W<'_>

Bit 3 - Clear Interrupt Pending Bit

pub fn control(&mut self) -> CONTROL_W<'_>

Bit 4 - Access Control Bits

pub fn arbacc(&mut self) -> ARBACC_W<'_>

Bit 5 - Access Arbitration Bits

pub fn maskacc(&mut self) -> MASKACC_W<'_>

Bit 6 - Access Mask Bits

pub fn wrrd(&mut self) -> WRRD_W<'_>

Bit 7 - Write/Read RAM

impl W<u32, Reg<u32, _MIR1_MASK>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 0:28 - Identifier Mask

pub fn mdir(&mut self) -> MDIR_W<'_>

Bit 30 - Mask Message Direction

pub fn mxtd(&mut self) -> MXTD_W<'_>

Bit 31 - Mask Extended Identifier

impl W<u32, Reg<u32, _MIR1_ARB>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:28 - Message Identifier

pub fn dir(&mut self) -> DIR_W<'_>

Bit 29 - Message Direction

pub fn xtd(&mut self) -> XTD_W<'_>

Bit 30 - Extended Identifier

pub fn msgval(&mut self) -> MSGVAL_W<'_>

Bit 31 - Message Valid

impl W<u32, Reg<u32, _MIR1_CTRL>>

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - Data Length Code

pub fn eob(&mut self) -> EOB_W<'_>

Bit 7 - End of Buffer

pub fn txrqst(&mut self) -> TXRQST_W<'_>

Bit 8 - Transmit Request

pub fn rmten(&mut self) -> RMTEN_W<'_>

Bit 9 - Remote Enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 10 - Receive Interrupt Enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 11 - Transmit Interrupt Enable

pub fn umask(&mut self) -> UMASK_W<'_>

Bit 12 - Use Acceptance Mask

pub fn intpnd(&mut self) -> INTPND_W<'_>

Bit 13 - Interrupt Pending

pub fn messageof(&mut self) -> MESSAGEOF_W<'_>

Bit 14 - Message Lost (only Valid for Message Objects With Direction = Receive)

pub fn datavalid(&mut self) -> DATAVALID_W<'_>

Bit 15 - New Data

impl W<u32, Reg<u32, _MIR1_DATAL>>

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - First Byte of CAN Data Frame

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - Second Byte of CAN Data Frame

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - Third Byte of CAN Data Frame

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - Fourth Byte of CAN Data Frame

impl W<u32, Reg<u32, _MIR1_DATAH>>

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - Fifth Byte of CAN Data Frame

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - Sixth Byte of CAN Data Frame

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - Seventh Byte of CAN Data Frame

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - Eight Byte of CAN Data Frame

impl W<u32, Reg<u32, _MIR1_CMDREQ>>

pub fn msgnum(&mut self) -> MSGNUM_W<'_>

Bits 0:5 - Message Number

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn dissyncout(&mut self) -> DISSYNCOUT_W<'_>

Bit 14 - Disable Timer From Start/Stop/Reload Other Synchronized Timers

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:8 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:4 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:12 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn dissyncout(&mut self) -> DISSYNCOUT_W<'_>

Bit 14 - Disable Timer From Start/Stop/Reload Other Synchronized Timers

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:8 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:4 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:12 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn dissyncout(&mut self) -> DISSYNCOUT_W<'_>

Bit 14 - Disable Timer From Start/Stop/Reload Other Synchronized Timers

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:8 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:4 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:12 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn dissyncout(&mut self) -> DISSYNCOUT_W<'_>

Bit 14 - Disable Timer From Start/Stop/Reload Other Synchronized Timers

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:8 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:4 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:12 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn dissyncout(&mut self) -> DISSYNCOUT_W<'_>

Bit 14 - Disable Timer From Start/Stop/Reload Other Synchronized Timers

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:8 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:4 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:12 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn dissyncout(&mut self) -> DISSYNCOUT_W<'_>

Bit 14 - Disable Timer From Start/Stop/Reload Other Synchronized Timers

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:8 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:4 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:12 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn dissyncout(&mut self) -> DISSYNCOUT_W<'_>

Bit 14 - Disable Timer From Start/Stop/Reload Other Synchronized Timers

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:8 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:4 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:12 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn dissyncout(&mut self) -> DISSYNCOUT_W<'_>

Bit 14 - Disable Timer From Start/Stop/Reload Other Synchronized Timers

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:8 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:4 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:12 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn dissyncout(&mut self) -> DISSYNCOUT_W<'_>

Bit 14 - Disable Timer From Start/Stop/Reload Other Synchronized Timers

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:8 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:4 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:12 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn dissyncout(&mut self) -> DISSYNCOUT_W<'_>

Bit 14 - Disable Timer From Start/Stop/Reload Other Synchronized Timers

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:8 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:4 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:12 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn dissyncout(&mut self) -> DISSYNCOUT_W<'_>

Bit 14 - Disable Timer From Start/Stop/Reload Other Synchronized Timers

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:20 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:8 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:4 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:12 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 0 - USART Synchronous Mode

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 1 - Loopback Enable

pub fn ccen(&mut self) -> CCEN_W<'_>

Bit 2 - Collision Check Enable

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 3 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 4 - Multi-Processor Address-Bit

pub fn ovs(&mut self) -> OVS_W<'_>

Bits 5:6 - Oversampling

pub fn clkpol(&mut self) -> CLKPOL_W<'_>

Bit 8 - Clock Polarity

pub fn clkpha(&mut self) -> CLKPHA_W<'_>

Bit 9 - Clock Edge for Setup/Sample

pub fn msbf(&mut self) -> MSBF_W<'_>

Bit 10 - Most Significant Bit First

pub fn csma(&mut self) -> CSMA_W<'_>

Bit 11 - Action on Slave-Select in Master Mode

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 12 - TX Buffer Interrupt Level

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 13 - Receiver Input Invert

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 14 - Transmitter Output Invert

pub fn csinv(&mut self) -> CSINV_W<'_>

Bit 15 - Chip Select Invert

pub fn autocs(&mut self) -> AUTOCS_W<'_>

Bit 16 - Automatic Chip Select

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 17 - Automatic TX Tristate

pub fn scmode(&mut self) -> SCMODE_W<'_>

Bit 18 - SmartCard Mode

pub fn scretrans(&mut self) -> SCRETRANS_W<'_>

Bit 19 - SmartCard Retransmit

pub fn skipperrf(&mut self) -> SKIPPERRF_W<'_>

Bit 20 - Skip Parity Error Frames

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 21 - Bit 8 Default Value

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 22 - Halt DMA on Error

pub fn errsrx(&mut self) -> ERRSRX_W<'_>

Bit 23 - Disable RX on Error

pub fn errstx(&mut self) -> ERRSTX_W<'_>

Bit 24 - Disable TX on Error

pub fn sssearly(&mut self) -> SSSEARLY_W<'_>

Bit 25 - Synchronous Slave Setup Early

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 28 - Byteswap in Double Accesses

pub fn autotx(&mut self) -> AUTOTX_W<'_>

Bit 29 - Always Transmit When RX Not Full

pub fn mvdis(&mut self) -> MVDIS_W<'_>

Bit 30 - Majority Vote Disable

pub fn smsdelay(&mut self) -> SMSDELAY_W<'_>

Bit 31 - Synchronous Master Sample Delay

impl W<u32, Reg<u32, _FRAME>>

pub fn databits(&mut self) -> DATABITS_W<'_>

Bits 0:3 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 8:9 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bits 12:13 - Stop-Bit Mode

impl W<u32, Reg<u32, _TRIGCTRL>>

pub fn rxten(&mut self) -> RXTEN_W<'_>

Bit 4 - Receive Trigger Enable

pub fn txten(&mut self) -> TXTEN_W<'_>

Bit 5 - Transmit Trigger Enable

pub fn autotxten(&mut self) -> AUTOTXTEN_W<'_>

Bit 6 - AUTOTX Trigger Enable

pub fn txarx0en(&mut self) -> TXARX0EN_W<'_>

Bit 7 - Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL

pub fn txarx1en(&mut self) -> TXARX1EN_W<'_>

Bit 8 - Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL

pub fn txarx2en(&mut self) -> TXARX2EN_W<'_>

Bit 9 - Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL

pub fn rxatx0en(&mut self) -> RXATX0EN_W<'_>

Bit 10 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times

pub fn rxatx1en(&mut self) -> RXATX1EN_W<'_>

Bit 11 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times

pub fn rxatx2en(&mut self) -> RXATX2EN_W<'_>

Bit 12 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times

pub fn tsel(&mut self) -> TSEL_W<'_>

Bits 16:20 - Trigger PRS Channel Select

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn masteren(&mut self) -> MASTEREN_W<'_>

Bit 4 - Master Enable

pub fn masterdis(&mut self) -> MASTERDIS_W<'_>

Bit 5 - Master Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 6 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 7 - Receiver Block Disable

pub fn txtrien(&mut self) -> TXTRIEN_W<'_>

Bit 8 - Transmitter Tristate Enable

pub fn txtridis(&mut self) -> TXTRIDIS_W<'_>

Bit 9 - Transmitter Tristate Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 10 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 11 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:22 - Fractional Clock Divider

pub fn autobauden(&mut self) -> AUTOBAUDEN_W<'_>

Bit 31 - AUTOBAUD Detection Enable

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdatax(&mut self) -> TXDATAX_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat(&mut self) -> UBRXAT_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat(&mut self) -> TXTRIAT_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLEX>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat0(&mut self) -> UBRXAT0_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat0(&mut self) -> TXTRIAT0_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak0(&mut self) -> TXBREAK0_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat0(&mut self) -> TXDISAT0_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat0(&mut self) -> RXENAT0_W<'_>

Bit 15 - Enable RX After Transmission

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 16:24 - TX Data

pub fn ubrxat1(&mut self) -> UBRXAT1_W<'_>

Bit 27 - Unblock RX After Transmission

pub fn txtriat1(&mut self) -> TXTRIAT1_W<'_>

Bit 28 - Set TXTRI After Transmission

pub fn txbreak1(&mut self) -> TXBREAK1_W<'_>

Bit 29 - Transmit Data as Break

pub fn txdisat1(&mut self) -> TXDISAT1_W<'_>

Bit 30 - Clear TXEN After Transmission

pub fn rxenat1(&mut self) -> RXENAT1_W<'_>

Bit 31 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Set RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Set TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Set TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Set MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Set SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Set CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Set TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Set TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Set TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Set TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Clear RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Clear TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Clear TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Clear MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Clear SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Clear CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Clear TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Clear TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Clear TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Clear TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - RXFULL Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - TXOF Interrupt Enable

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - TXUF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - MPAF Interrupt Enable

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - SSM Interrupt Enable

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - CCF Interrupt Enable

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - TXIDLE Interrupt Enable

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - TCMP0 Interrupt Enable

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - TCMP1 Interrupt Enable

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - TCMP2 Interrupt Enable

impl W<u32, Reg<u32, _IRCTRL>>

pub fn iren(&mut self) -> IREN_W<'_>

Bit 0 - Enable IrDA Module

pub fn irpw(&mut self) -> IRPW_W<'_>

Bits 1:2 - IrDA TX Pulse Width

pub fn irfilt(&mut self) -> IRFILT_W<'_>

Bit 3 - IrDA RX Filter

pub fn irprsen(&mut self) -> IRPRSEN_W<'_>

Bit 7 - IrDA PRS Channel Enable

pub fn irprssel(&mut self) -> IRPRSSEL_W<'_>

Bits 8:12 - IrDA PRS Channel Select

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:4 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 7 - PRS RX Enable

pub fn clkprssel(&mut self) -> CLKPRSSEL_W<'_>

Bits 8:12 - CLK PRS Channel Select

pub fn clkprs(&mut self) -> CLKPRS_W<'_>

Bit 15 - PRS CLK Enable

impl W<u32, Reg<u32, _I2SCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable I2S Mode

pub fn mono(&mut self) -> MONO_W<'_>

Bit 1 - Stero or Mono

pub fn justify(&mut self) -> JUSTIFY_W<'_>

Bit 2 - Justification of I2S Data

pub fn dmasplit(&mut self) -> DMASPLIT_W<'_>

Bit 3 - Separate DMA Request for Left/Right Data

pub fn delay(&mut self) -> DELAY_W<'_>

Bit 4 - Delay on I2S Data

pub fn format(&mut self) -> FORMAT_W<'_>

Bits 8:10 - I2S Word Format

impl W<u32, Reg<u32, _TIMING>>

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 16:18 - TX Frame Start Delay

pub fn cssetup(&mut self) -> CSSETUP_W<'_>

Bits 20:22 - Chip Select Setup

pub fn ics(&mut self) -> ICS_W<'_>

Bits 24:26 - Inter-character Spacing

pub fn cshold(&mut self) -> CSHOLD_W<'_>

Bits 28:30 - Chip Select Hold

impl W<u32, Reg<u32, _CTRLX>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 0 - Debug Halt

pub fn ctsinv(&mut self) -> CTSINV_W<'_>

Bit 1 - CTS Pin Inversion

pub fn ctsen(&mut self) -> CTSEN_W<'_>

Bit 2 - CTS Function Enabled

pub fn rtsinv(&mut self) -> RTSINV_W<'_>

Bit 3 - RTS Pin Inversion

impl W<u32, Reg<u32, _TIMECMP0>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 0

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 0

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP0

impl W<u32, Reg<u32, _TIMECMP1>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 1

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 1

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP1

impl W<u32, Reg<u32, _TIMECMP2>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 2

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 2

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP2

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

pub fn cspen(&mut self) -> CSPEN_W<'_>

Bit 2 - CS Pin Enable

pub fn clkpen(&mut self) -> CLKPEN_W<'_>

Bit 3 - CLK Pin Enable

pub fn ctspen(&mut self) -> CTSPEN_W<'_>

Bit 4 - CTS Pin Enable

pub fn rtspen(&mut self) -> RTSPEN_W<'_>

Bit 5 - RTS Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

pub fn csloc(&mut self) -> CSLOC_W<'_>

Bits 16:21 - I/O Location

pub fn clkloc(&mut self) -> CLKLOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn ctsloc(&mut self) -> CTSLOC_W<'_>

Bits 0:5 - I/O Location

pub fn rtsloc(&mut self) -> RTSLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 0 - USART Synchronous Mode

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 1 - Loopback Enable

pub fn ccen(&mut self) -> CCEN_W<'_>

Bit 2 - Collision Check Enable

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 3 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 4 - Multi-Processor Address-Bit

pub fn ovs(&mut self) -> OVS_W<'_>

Bits 5:6 - Oversampling

pub fn clkpol(&mut self) -> CLKPOL_W<'_>

Bit 8 - Clock Polarity

pub fn clkpha(&mut self) -> CLKPHA_W<'_>

Bit 9 - Clock Edge for Setup/Sample

pub fn msbf(&mut self) -> MSBF_W<'_>

Bit 10 - Most Significant Bit First

pub fn csma(&mut self) -> CSMA_W<'_>

Bit 11 - Action on Slave-Select in Master Mode

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 12 - TX Buffer Interrupt Level

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 13 - Receiver Input Invert

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 14 - Transmitter Output Invert

pub fn csinv(&mut self) -> CSINV_W<'_>

Bit 15 - Chip Select Invert

pub fn autocs(&mut self) -> AUTOCS_W<'_>

Bit 16 - Automatic Chip Select

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 17 - Automatic TX Tristate

pub fn scmode(&mut self) -> SCMODE_W<'_>

Bit 18 - SmartCard Mode

pub fn scretrans(&mut self) -> SCRETRANS_W<'_>

Bit 19 - SmartCard Retransmit

pub fn skipperrf(&mut self) -> SKIPPERRF_W<'_>

Bit 20 - Skip Parity Error Frames

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 21 - Bit 8 Default Value

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 22 - Halt DMA on Error

pub fn errsrx(&mut self) -> ERRSRX_W<'_>

Bit 23 - Disable RX on Error

pub fn errstx(&mut self) -> ERRSTX_W<'_>

Bit 24 - Disable TX on Error

pub fn sssearly(&mut self) -> SSSEARLY_W<'_>

Bit 25 - Synchronous Slave Setup Early

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 28 - Byteswap in Double Accesses

pub fn autotx(&mut self) -> AUTOTX_W<'_>

Bit 29 - Always Transmit When RX Not Full

pub fn mvdis(&mut self) -> MVDIS_W<'_>

Bit 30 - Majority Vote Disable

pub fn smsdelay(&mut self) -> SMSDELAY_W<'_>

Bit 31 - Synchronous Master Sample Delay

impl W<u32, Reg<u32, _FRAME>>

pub fn databits(&mut self) -> DATABITS_W<'_>

Bits 0:3 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 8:9 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bits 12:13 - Stop-Bit Mode

impl W<u32, Reg<u32, _TRIGCTRL>>

pub fn rxten(&mut self) -> RXTEN_W<'_>

Bit 4 - Receive Trigger Enable

pub fn txten(&mut self) -> TXTEN_W<'_>

Bit 5 - Transmit Trigger Enable

pub fn autotxten(&mut self) -> AUTOTXTEN_W<'_>

Bit 6 - AUTOTX Trigger Enable

pub fn txarx0en(&mut self) -> TXARX0EN_W<'_>

Bit 7 - Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL

pub fn txarx1en(&mut self) -> TXARX1EN_W<'_>

Bit 8 - Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL

pub fn txarx2en(&mut self) -> TXARX2EN_W<'_>

Bit 9 - Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL

pub fn rxatx0en(&mut self) -> RXATX0EN_W<'_>

Bit 10 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times

pub fn rxatx1en(&mut self) -> RXATX1EN_W<'_>

Bit 11 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times

pub fn rxatx2en(&mut self) -> RXATX2EN_W<'_>

Bit 12 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times

pub fn tsel(&mut self) -> TSEL_W<'_>

Bits 16:20 - Trigger PRS Channel Select

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn masteren(&mut self) -> MASTEREN_W<'_>

Bit 4 - Master Enable

pub fn masterdis(&mut self) -> MASTERDIS_W<'_>

Bit 5 - Master Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 6 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 7 - Receiver Block Disable

pub fn txtrien(&mut self) -> TXTRIEN_W<'_>

Bit 8 - Transmitter Tristate Enable

pub fn txtridis(&mut self) -> TXTRIDIS_W<'_>

Bit 9 - Transmitter Tristate Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 10 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 11 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:22 - Fractional Clock Divider

pub fn autobauden(&mut self) -> AUTOBAUDEN_W<'_>

Bit 31 - AUTOBAUD Detection Enable

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdatax(&mut self) -> TXDATAX_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat(&mut self) -> UBRXAT_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat(&mut self) -> TXTRIAT_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLEX>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat0(&mut self) -> UBRXAT0_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat0(&mut self) -> TXTRIAT0_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak0(&mut self) -> TXBREAK0_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat0(&mut self) -> TXDISAT0_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat0(&mut self) -> RXENAT0_W<'_>

Bit 15 - Enable RX After Transmission

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 16:24 - TX Data

pub fn ubrxat1(&mut self) -> UBRXAT1_W<'_>

Bit 27 - Unblock RX After Transmission

pub fn txtriat1(&mut self) -> TXTRIAT1_W<'_>

Bit 28 - Set TXTRI After Transmission

pub fn txbreak1(&mut self) -> TXBREAK1_W<'_>

Bit 29 - Transmit Data as Break

pub fn txdisat1(&mut self) -> TXDISAT1_W<'_>

Bit 30 - Clear TXEN After Transmission

pub fn rxenat1(&mut self) -> RXENAT1_W<'_>

Bit 31 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Set RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Set TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Set TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Set MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Set SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Set CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Set TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Set TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Set TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Set TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Clear RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Clear TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Clear TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Clear MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Clear SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Clear CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Clear TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Clear TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Clear TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Clear TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - RXFULL Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - TXOF Interrupt Enable

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - TXUF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - MPAF Interrupt Enable

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - SSM Interrupt Enable

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - CCF Interrupt Enable

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - TXIDLE Interrupt Enable

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - TCMP0 Interrupt Enable

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - TCMP1 Interrupt Enable

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - TCMP2 Interrupt Enable

impl W<u32, Reg<u32, _IRCTRL>>

pub fn iren(&mut self) -> IREN_W<'_>

Bit 0 - Enable IrDA Module

pub fn irpw(&mut self) -> IRPW_W<'_>

Bits 1:2 - IrDA TX Pulse Width

pub fn irfilt(&mut self) -> IRFILT_W<'_>

Bit 3 - IrDA RX Filter

pub fn irprsen(&mut self) -> IRPRSEN_W<'_>

Bit 7 - IrDA PRS Channel Enable

pub fn irprssel(&mut self) -> IRPRSSEL_W<'_>

Bits 8:12 - IrDA PRS Channel Select

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:4 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 7 - PRS RX Enable

pub fn clkprssel(&mut self) -> CLKPRSSEL_W<'_>

Bits 8:12 - CLK PRS Channel Select

pub fn clkprs(&mut self) -> CLKPRS_W<'_>

Bit 15 - PRS CLK Enable

impl W<u32, Reg<u32, _I2SCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable I2S Mode

pub fn mono(&mut self) -> MONO_W<'_>

Bit 1 - Stero or Mono

pub fn justify(&mut self) -> JUSTIFY_W<'_>

Bit 2 - Justification of I2S Data

pub fn dmasplit(&mut self) -> DMASPLIT_W<'_>

Bit 3 - Separate DMA Request for Left/Right Data

pub fn delay(&mut self) -> DELAY_W<'_>

Bit 4 - Delay on I2S Data

pub fn format(&mut self) -> FORMAT_W<'_>

Bits 8:10 - I2S Word Format

impl W<u32, Reg<u32, _TIMING>>

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 16:18 - TX Frame Start Delay

pub fn cssetup(&mut self) -> CSSETUP_W<'_>

Bits 20:22 - Chip Select Setup

pub fn ics(&mut self) -> ICS_W<'_>

Bits 24:26 - Inter-character Spacing

pub fn cshold(&mut self) -> CSHOLD_W<'_>

Bits 28:30 - Chip Select Hold

impl W<u32, Reg<u32, _CTRLX>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 0 - Debug Halt

pub fn ctsinv(&mut self) -> CTSINV_W<'_>

Bit 1 - CTS Pin Inversion

pub fn ctsen(&mut self) -> CTSEN_W<'_>

Bit 2 - CTS Function Enabled

pub fn rtsinv(&mut self) -> RTSINV_W<'_>

Bit 3 - RTS Pin Inversion

impl W<u32, Reg<u32, _TIMECMP0>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 0

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 0

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP0

impl W<u32, Reg<u32, _TIMECMP1>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 1

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 1

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP1

impl W<u32, Reg<u32, _TIMECMP2>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 2

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 2

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP2

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

pub fn cspen(&mut self) -> CSPEN_W<'_>

Bit 2 - CS Pin Enable

pub fn clkpen(&mut self) -> CLKPEN_W<'_>

Bit 3 - CLK Pin Enable

pub fn ctspen(&mut self) -> CTSPEN_W<'_>

Bit 4 - CTS Pin Enable

pub fn rtspen(&mut self) -> RTSPEN_W<'_>

Bit 5 - RTS Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

pub fn csloc(&mut self) -> CSLOC_W<'_>

Bits 16:21 - I/O Location

pub fn clkloc(&mut self) -> CLKLOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn ctsloc(&mut self) -> CTSLOC_W<'_>

Bits 0:5 - I/O Location

pub fn rtsloc(&mut self) -> RTSLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 0 - USART Synchronous Mode

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 1 - Loopback Enable

pub fn ccen(&mut self) -> CCEN_W<'_>

Bit 2 - Collision Check Enable

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 3 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 4 - Multi-Processor Address-Bit

pub fn ovs(&mut self) -> OVS_W<'_>

Bits 5:6 - Oversampling

pub fn clkpol(&mut self) -> CLKPOL_W<'_>

Bit 8 - Clock Polarity

pub fn clkpha(&mut self) -> CLKPHA_W<'_>

Bit 9 - Clock Edge for Setup/Sample

pub fn msbf(&mut self) -> MSBF_W<'_>

Bit 10 - Most Significant Bit First

pub fn csma(&mut self) -> CSMA_W<'_>

Bit 11 - Action on Slave-Select in Master Mode

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 12 - TX Buffer Interrupt Level

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 13 - Receiver Input Invert

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 14 - Transmitter Output Invert

pub fn csinv(&mut self) -> CSINV_W<'_>

Bit 15 - Chip Select Invert

pub fn autocs(&mut self) -> AUTOCS_W<'_>

Bit 16 - Automatic Chip Select

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 17 - Automatic TX Tristate

pub fn scmode(&mut self) -> SCMODE_W<'_>

Bit 18 - SmartCard Mode

pub fn scretrans(&mut self) -> SCRETRANS_W<'_>

Bit 19 - SmartCard Retransmit

pub fn skipperrf(&mut self) -> SKIPPERRF_W<'_>

Bit 20 - Skip Parity Error Frames

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 21 - Bit 8 Default Value

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 22 - Halt DMA on Error

pub fn errsrx(&mut self) -> ERRSRX_W<'_>

Bit 23 - Disable RX on Error

pub fn errstx(&mut self) -> ERRSTX_W<'_>

Bit 24 - Disable TX on Error

pub fn sssearly(&mut self) -> SSSEARLY_W<'_>

Bit 25 - Synchronous Slave Setup Early

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 28 - Byteswap in Double Accesses

pub fn autotx(&mut self) -> AUTOTX_W<'_>

Bit 29 - Always Transmit When RX Not Full

pub fn mvdis(&mut self) -> MVDIS_W<'_>

Bit 30 - Majority Vote Disable

pub fn smsdelay(&mut self) -> SMSDELAY_W<'_>

Bit 31 - Synchronous Master Sample Delay

impl W<u32, Reg<u32, _FRAME>>

pub fn databits(&mut self) -> DATABITS_W<'_>

Bits 0:3 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 8:9 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bits 12:13 - Stop-Bit Mode

impl W<u32, Reg<u32, _TRIGCTRL>>

pub fn rxten(&mut self) -> RXTEN_W<'_>

Bit 4 - Receive Trigger Enable

pub fn txten(&mut self) -> TXTEN_W<'_>

Bit 5 - Transmit Trigger Enable

pub fn autotxten(&mut self) -> AUTOTXTEN_W<'_>

Bit 6 - AUTOTX Trigger Enable

pub fn txarx0en(&mut self) -> TXARX0EN_W<'_>

Bit 7 - Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL

pub fn txarx1en(&mut self) -> TXARX1EN_W<'_>

Bit 8 - Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL

pub fn txarx2en(&mut self) -> TXARX2EN_W<'_>

Bit 9 - Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL

pub fn rxatx0en(&mut self) -> RXATX0EN_W<'_>

Bit 10 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times

pub fn rxatx1en(&mut self) -> RXATX1EN_W<'_>

Bit 11 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times

pub fn rxatx2en(&mut self) -> RXATX2EN_W<'_>

Bit 12 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times

pub fn tsel(&mut self) -> TSEL_W<'_>

Bits 16:20 - Trigger PRS Channel Select

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn masteren(&mut self) -> MASTEREN_W<'_>

Bit 4 - Master Enable

pub fn masterdis(&mut self) -> MASTERDIS_W<'_>

Bit 5 - Master Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 6 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 7 - Receiver Block Disable

pub fn txtrien(&mut self) -> TXTRIEN_W<'_>

Bit 8 - Transmitter Tristate Enable

pub fn txtridis(&mut self) -> TXTRIDIS_W<'_>

Bit 9 - Transmitter Tristate Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 10 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 11 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:22 - Fractional Clock Divider

pub fn autobauden(&mut self) -> AUTOBAUDEN_W<'_>

Bit 31 - AUTOBAUD Detection Enable

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdatax(&mut self) -> TXDATAX_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat(&mut self) -> UBRXAT_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat(&mut self) -> TXTRIAT_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLEX>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat0(&mut self) -> UBRXAT0_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat0(&mut self) -> TXTRIAT0_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak0(&mut self) -> TXBREAK0_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat0(&mut self) -> TXDISAT0_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat0(&mut self) -> RXENAT0_W<'_>

Bit 15 - Enable RX After Transmission

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 16:24 - TX Data

pub fn ubrxat1(&mut self) -> UBRXAT1_W<'_>

Bit 27 - Unblock RX After Transmission

pub fn txtriat1(&mut self) -> TXTRIAT1_W<'_>

Bit 28 - Set TXTRI After Transmission

pub fn txbreak1(&mut self) -> TXBREAK1_W<'_>

Bit 29 - Transmit Data as Break

pub fn txdisat1(&mut self) -> TXDISAT1_W<'_>

Bit 30 - Clear TXEN After Transmission

pub fn rxenat1(&mut self) -> RXENAT1_W<'_>

Bit 31 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Set RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Set TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Set TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Set MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Set SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Set CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Set TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Set TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Set TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Set TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Clear RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Clear TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Clear TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Clear MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Clear SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Clear CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Clear TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Clear TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Clear TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Clear TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - RXFULL Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - TXOF Interrupt Enable

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - TXUF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - MPAF Interrupt Enable

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - SSM Interrupt Enable

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - CCF Interrupt Enable

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - TXIDLE Interrupt Enable

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - TCMP0 Interrupt Enable

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - TCMP1 Interrupt Enable

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - TCMP2 Interrupt Enable

impl W<u32, Reg<u32, _IRCTRL>>

pub fn iren(&mut self) -> IREN_W<'_>

Bit 0 - Enable IrDA Module

pub fn irpw(&mut self) -> IRPW_W<'_>

Bits 1:2 - IrDA TX Pulse Width

pub fn irfilt(&mut self) -> IRFILT_W<'_>

Bit 3 - IrDA RX Filter

pub fn irprsen(&mut self) -> IRPRSEN_W<'_>

Bit 7 - IrDA PRS Channel Enable

pub fn irprssel(&mut self) -> IRPRSSEL_W<'_>

Bits 8:12 - IrDA PRS Channel Select

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:4 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 7 - PRS RX Enable

pub fn clkprssel(&mut self) -> CLKPRSSEL_W<'_>

Bits 8:12 - CLK PRS Channel Select

pub fn clkprs(&mut self) -> CLKPRS_W<'_>

Bit 15 - PRS CLK Enable

impl W<u32, Reg<u32, _I2SCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable I2S Mode

pub fn mono(&mut self) -> MONO_W<'_>

Bit 1 - Stero or Mono

pub fn justify(&mut self) -> JUSTIFY_W<'_>

Bit 2 - Justification of I2S Data

pub fn dmasplit(&mut self) -> DMASPLIT_W<'_>

Bit 3 - Separate DMA Request for Left/Right Data

pub fn delay(&mut self) -> DELAY_W<'_>

Bit 4 - Delay on I2S Data

pub fn format(&mut self) -> FORMAT_W<'_>

Bits 8:10 - I2S Word Format

impl W<u32, Reg<u32, _TIMING>>

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 16:18 - TX Frame Start Delay

pub fn cssetup(&mut self) -> CSSETUP_W<'_>

Bits 20:22 - Chip Select Setup

pub fn ics(&mut self) -> ICS_W<'_>

Bits 24:26 - Inter-character Spacing

pub fn cshold(&mut self) -> CSHOLD_W<'_>

Bits 28:30 - Chip Select Hold

impl W<u32, Reg<u32, _CTRLX>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 0 - Debug Halt

pub fn ctsinv(&mut self) -> CTSINV_W<'_>

Bit 1 - CTS Pin Inversion

pub fn ctsen(&mut self) -> CTSEN_W<'_>

Bit 2 - CTS Function Enabled

pub fn rtsinv(&mut self) -> RTSINV_W<'_>

Bit 3 - RTS Pin Inversion

impl W<u32, Reg<u32, _TIMECMP0>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 0

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 0

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP0

impl W<u32, Reg<u32, _TIMECMP1>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 1

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 1

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP1

impl W<u32, Reg<u32, _TIMECMP2>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 2

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 2

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP2

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

pub fn cspen(&mut self) -> CSPEN_W<'_>

Bit 2 - CS Pin Enable

pub fn clkpen(&mut self) -> CLKPEN_W<'_>

Bit 3 - CLK Pin Enable

pub fn ctspen(&mut self) -> CTSPEN_W<'_>

Bit 4 - CTS Pin Enable

pub fn rtspen(&mut self) -> RTSPEN_W<'_>

Bit 5 - RTS Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

pub fn csloc(&mut self) -> CSLOC_W<'_>

Bits 16:21 - I/O Location

pub fn clkloc(&mut self) -> CLKLOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn ctsloc(&mut self) -> CTSLOC_W<'_>

Bits 0:5 - I/O Location

pub fn rtsloc(&mut self) -> RTSLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 0 - USART Synchronous Mode

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 1 - Loopback Enable

pub fn ccen(&mut self) -> CCEN_W<'_>

Bit 2 - Collision Check Enable

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 3 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 4 - Multi-Processor Address-Bit

pub fn ovs(&mut self) -> OVS_W<'_>

Bits 5:6 - Oversampling

pub fn clkpol(&mut self) -> CLKPOL_W<'_>

Bit 8 - Clock Polarity

pub fn clkpha(&mut self) -> CLKPHA_W<'_>

Bit 9 - Clock Edge for Setup/Sample

pub fn msbf(&mut self) -> MSBF_W<'_>

Bit 10 - Most Significant Bit First

pub fn csma(&mut self) -> CSMA_W<'_>

Bit 11 - Action on Slave-Select in Master Mode

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 12 - TX Buffer Interrupt Level

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 13 - Receiver Input Invert

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 14 - Transmitter Output Invert

pub fn csinv(&mut self) -> CSINV_W<'_>

Bit 15 - Chip Select Invert

pub fn autocs(&mut self) -> AUTOCS_W<'_>

Bit 16 - Automatic Chip Select

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 17 - Automatic TX Tristate

pub fn scmode(&mut self) -> SCMODE_W<'_>

Bit 18 - SmartCard Mode

pub fn scretrans(&mut self) -> SCRETRANS_W<'_>

Bit 19 - SmartCard Retransmit

pub fn skipperrf(&mut self) -> SKIPPERRF_W<'_>

Bit 20 - Skip Parity Error Frames

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 21 - Bit 8 Default Value

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 22 - Halt DMA on Error

pub fn errsrx(&mut self) -> ERRSRX_W<'_>

Bit 23 - Disable RX on Error

pub fn errstx(&mut self) -> ERRSTX_W<'_>

Bit 24 - Disable TX on Error

pub fn sssearly(&mut self) -> SSSEARLY_W<'_>

Bit 25 - Synchronous Slave Setup Early

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 28 - Byteswap in Double Accesses

pub fn autotx(&mut self) -> AUTOTX_W<'_>

Bit 29 - Always Transmit When RX Not Full

pub fn mvdis(&mut self) -> MVDIS_W<'_>

Bit 30 - Majority Vote Disable

pub fn smsdelay(&mut self) -> SMSDELAY_W<'_>

Bit 31 - Synchronous Master Sample Delay

impl W<u32, Reg<u32, _FRAME>>

pub fn databits(&mut self) -> DATABITS_W<'_>

Bits 0:3 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 8:9 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bits 12:13 - Stop-Bit Mode

impl W<u32, Reg<u32, _TRIGCTRL>>

pub fn rxten(&mut self) -> RXTEN_W<'_>

Bit 4 - Receive Trigger Enable

pub fn txten(&mut self) -> TXTEN_W<'_>

Bit 5 - Transmit Trigger Enable

pub fn autotxten(&mut self) -> AUTOTXTEN_W<'_>

Bit 6 - AUTOTX Trigger Enable

pub fn txarx0en(&mut self) -> TXARX0EN_W<'_>

Bit 7 - Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL

pub fn txarx1en(&mut self) -> TXARX1EN_W<'_>

Bit 8 - Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL

pub fn txarx2en(&mut self) -> TXARX2EN_W<'_>

Bit 9 - Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL

pub fn rxatx0en(&mut self) -> RXATX0EN_W<'_>

Bit 10 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times

pub fn rxatx1en(&mut self) -> RXATX1EN_W<'_>

Bit 11 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times

pub fn rxatx2en(&mut self) -> RXATX2EN_W<'_>

Bit 12 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times

pub fn tsel(&mut self) -> TSEL_W<'_>

Bits 16:20 - Trigger PRS Channel Select

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn masteren(&mut self) -> MASTEREN_W<'_>

Bit 4 - Master Enable

pub fn masterdis(&mut self) -> MASTERDIS_W<'_>

Bit 5 - Master Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 6 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 7 - Receiver Block Disable

pub fn txtrien(&mut self) -> TXTRIEN_W<'_>

Bit 8 - Transmitter Tristate Enable

pub fn txtridis(&mut self) -> TXTRIDIS_W<'_>

Bit 9 - Transmitter Tristate Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 10 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 11 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:22 - Fractional Clock Divider

pub fn autobauden(&mut self) -> AUTOBAUDEN_W<'_>

Bit 31 - AUTOBAUD Detection Enable

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdatax(&mut self) -> TXDATAX_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat(&mut self) -> UBRXAT_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat(&mut self) -> TXTRIAT_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLEX>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat0(&mut self) -> UBRXAT0_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat0(&mut self) -> TXTRIAT0_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak0(&mut self) -> TXBREAK0_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat0(&mut self) -> TXDISAT0_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat0(&mut self) -> RXENAT0_W<'_>

Bit 15 - Enable RX After Transmission

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 16:24 - TX Data

pub fn ubrxat1(&mut self) -> UBRXAT1_W<'_>

Bit 27 - Unblock RX After Transmission

pub fn txtriat1(&mut self) -> TXTRIAT1_W<'_>

Bit 28 - Set TXTRI After Transmission

pub fn txbreak1(&mut self) -> TXBREAK1_W<'_>

Bit 29 - Transmit Data as Break

pub fn txdisat1(&mut self) -> TXDISAT1_W<'_>

Bit 30 - Clear TXEN After Transmission

pub fn rxenat1(&mut self) -> RXENAT1_W<'_>

Bit 31 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Set RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Set TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Set TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Set MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Set SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Set CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Set TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Set TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Set TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Set TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Clear RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Clear TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Clear TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Clear MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Clear SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Clear CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Clear TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Clear TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Clear TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Clear TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - RXFULL Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - TXOF Interrupt Enable

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - TXUF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - MPAF Interrupt Enable

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - SSM Interrupt Enable

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - CCF Interrupt Enable

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - TXIDLE Interrupt Enable

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - TCMP0 Interrupt Enable

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - TCMP1 Interrupt Enable

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - TCMP2 Interrupt Enable

impl W<u32, Reg<u32, _IRCTRL>>

pub fn iren(&mut self) -> IREN_W<'_>

Bit 0 - Enable IrDA Module

pub fn irpw(&mut self) -> IRPW_W<'_>

Bits 1:2 - IrDA TX Pulse Width

pub fn irfilt(&mut self) -> IRFILT_W<'_>

Bit 3 - IrDA RX Filter

pub fn irprsen(&mut self) -> IRPRSEN_W<'_>

Bit 7 - IrDA PRS Channel Enable

pub fn irprssel(&mut self) -> IRPRSSEL_W<'_>

Bits 8:12 - IrDA PRS Channel Select

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:4 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 7 - PRS RX Enable

pub fn clkprssel(&mut self) -> CLKPRSSEL_W<'_>

Bits 8:12 - CLK PRS Channel Select

pub fn clkprs(&mut self) -> CLKPRS_W<'_>

Bit 15 - PRS CLK Enable

impl W<u32, Reg<u32, _I2SCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable I2S Mode

pub fn mono(&mut self) -> MONO_W<'_>

Bit 1 - Stero or Mono

pub fn justify(&mut self) -> JUSTIFY_W<'_>

Bit 2 - Justification of I2S Data

pub fn dmasplit(&mut self) -> DMASPLIT_W<'_>

Bit 3 - Separate DMA Request for Left/Right Data

pub fn delay(&mut self) -> DELAY_W<'_>

Bit 4 - Delay on I2S Data

pub fn format(&mut self) -> FORMAT_W<'_>

Bits 8:10 - I2S Word Format

impl W<u32, Reg<u32, _TIMING>>

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 16:18 - TX Frame Start Delay

pub fn cssetup(&mut self) -> CSSETUP_W<'_>

Bits 20:22 - Chip Select Setup

pub fn ics(&mut self) -> ICS_W<'_>

Bits 24:26 - Inter-character Spacing

pub fn cshold(&mut self) -> CSHOLD_W<'_>

Bits 28:30 - Chip Select Hold

impl W<u32, Reg<u32, _CTRLX>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 0 - Debug Halt

pub fn ctsinv(&mut self) -> CTSINV_W<'_>

Bit 1 - CTS Pin Inversion

pub fn ctsen(&mut self) -> CTSEN_W<'_>

Bit 2 - CTS Function Enabled

pub fn rtsinv(&mut self) -> RTSINV_W<'_>

Bit 3 - RTS Pin Inversion

impl W<u32, Reg<u32, _TIMECMP0>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 0

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 0

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP0

impl W<u32, Reg<u32, _TIMECMP1>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 1

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 1

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP1

impl W<u32, Reg<u32, _TIMECMP2>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 2

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 2

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP2

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

pub fn cspen(&mut self) -> CSPEN_W<'_>

Bit 2 - CS Pin Enable

pub fn clkpen(&mut self) -> CLKPEN_W<'_>

Bit 3 - CLK Pin Enable

pub fn ctspen(&mut self) -> CTSPEN_W<'_>

Bit 4 - CTS Pin Enable

pub fn rtspen(&mut self) -> RTSPEN_W<'_>

Bit 5 - RTS Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

pub fn csloc(&mut self) -> CSLOC_W<'_>

Bits 16:21 - I/O Location

pub fn clkloc(&mut self) -> CLKLOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn ctsloc(&mut self) -> CTSLOC_W<'_>

Bits 0:5 - I/O Location

pub fn rtsloc(&mut self) -> RTSLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 0 - USART Synchronous Mode

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 1 - Loopback Enable

pub fn ccen(&mut self) -> CCEN_W<'_>

Bit 2 - Collision Check Enable

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 3 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 4 - Multi-Processor Address-Bit

pub fn ovs(&mut self) -> OVS_W<'_>

Bits 5:6 - Oversampling

pub fn clkpol(&mut self) -> CLKPOL_W<'_>

Bit 8 - Clock Polarity

pub fn clkpha(&mut self) -> CLKPHA_W<'_>

Bit 9 - Clock Edge for Setup/Sample

pub fn msbf(&mut self) -> MSBF_W<'_>

Bit 10 - Most Significant Bit First

pub fn csma(&mut self) -> CSMA_W<'_>

Bit 11 - Action on Slave-Select in Master Mode

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 12 - TX Buffer Interrupt Level

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 13 - Receiver Input Invert

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 14 - Transmitter Output Invert

pub fn csinv(&mut self) -> CSINV_W<'_>

Bit 15 - Chip Select Invert

pub fn autocs(&mut self) -> AUTOCS_W<'_>

Bit 16 - Automatic Chip Select

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 17 - Automatic TX Tristate

pub fn scmode(&mut self) -> SCMODE_W<'_>

Bit 18 - SmartCard Mode

pub fn scretrans(&mut self) -> SCRETRANS_W<'_>

Bit 19 - SmartCard Retransmit

pub fn skipperrf(&mut self) -> SKIPPERRF_W<'_>

Bit 20 - Skip Parity Error Frames

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 21 - Bit 8 Default Value

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 22 - Halt DMA on Error

pub fn errsrx(&mut self) -> ERRSRX_W<'_>

Bit 23 - Disable RX on Error

pub fn errstx(&mut self) -> ERRSTX_W<'_>

Bit 24 - Disable TX on Error

pub fn sssearly(&mut self) -> SSSEARLY_W<'_>

Bit 25 - Synchronous Slave Setup Early

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 28 - Byteswap in Double Accesses

pub fn autotx(&mut self) -> AUTOTX_W<'_>

Bit 29 - Always Transmit When RX Not Full

pub fn mvdis(&mut self) -> MVDIS_W<'_>

Bit 30 - Majority Vote Disable

pub fn smsdelay(&mut self) -> SMSDELAY_W<'_>

Bit 31 - Synchronous Master Sample Delay

impl W<u32, Reg<u32, _FRAME>>

pub fn databits(&mut self) -> DATABITS_W<'_>

Bits 0:3 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 8:9 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bits 12:13 - Stop-Bit Mode

impl W<u32, Reg<u32, _TRIGCTRL>>

pub fn rxten(&mut self) -> RXTEN_W<'_>

Bit 4 - Receive Trigger Enable

pub fn txten(&mut self) -> TXTEN_W<'_>

Bit 5 - Transmit Trigger Enable

pub fn autotxten(&mut self) -> AUTOTXTEN_W<'_>

Bit 6 - AUTOTX Trigger Enable

pub fn txarx0en(&mut self) -> TXARX0EN_W<'_>

Bit 7 - Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL

pub fn txarx1en(&mut self) -> TXARX1EN_W<'_>

Bit 8 - Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL

pub fn txarx2en(&mut self) -> TXARX2EN_W<'_>

Bit 9 - Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL

pub fn rxatx0en(&mut self) -> RXATX0EN_W<'_>

Bit 10 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times

pub fn rxatx1en(&mut self) -> RXATX1EN_W<'_>

Bit 11 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times

pub fn rxatx2en(&mut self) -> RXATX2EN_W<'_>

Bit 12 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times

pub fn tsel(&mut self) -> TSEL_W<'_>

Bits 16:20 - Trigger PRS Channel Select

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn masteren(&mut self) -> MASTEREN_W<'_>

Bit 4 - Master Enable

pub fn masterdis(&mut self) -> MASTERDIS_W<'_>

Bit 5 - Master Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 6 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 7 - Receiver Block Disable

pub fn txtrien(&mut self) -> TXTRIEN_W<'_>

Bit 8 - Transmitter Tristate Enable

pub fn txtridis(&mut self) -> TXTRIDIS_W<'_>

Bit 9 - Transmitter Tristate Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 10 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 11 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:22 - Fractional Clock Divider

pub fn autobauden(&mut self) -> AUTOBAUDEN_W<'_>

Bit 31 - AUTOBAUD Detection Enable

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdatax(&mut self) -> TXDATAX_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat(&mut self) -> UBRXAT_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat(&mut self) -> TXTRIAT_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLEX>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat0(&mut self) -> UBRXAT0_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat0(&mut self) -> TXTRIAT0_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak0(&mut self) -> TXBREAK0_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat0(&mut self) -> TXDISAT0_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat0(&mut self) -> RXENAT0_W<'_>

Bit 15 - Enable RX After Transmission

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 16:24 - TX Data

pub fn ubrxat1(&mut self) -> UBRXAT1_W<'_>

Bit 27 - Unblock RX After Transmission

pub fn txtriat1(&mut self) -> TXTRIAT1_W<'_>

Bit 28 - Set TXTRI After Transmission

pub fn txbreak1(&mut self) -> TXBREAK1_W<'_>

Bit 29 - Transmit Data as Break

pub fn txdisat1(&mut self) -> TXDISAT1_W<'_>

Bit 30 - Clear TXEN After Transmission

pub fn rxenat1(&mut self) -> RXENAT1_W<'_>

Bit 31 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Set RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Set TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Set TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Set MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Set SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Set CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Set TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Set TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Set TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Set TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Clear RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Clear TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Clear TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Clear MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Clear SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Clear CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Clear TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Clear TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Clear TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Clear TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - RXFULL Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - TXOF Interrupt Enable

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - TXUF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - MPAF Interrupt Enable

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - SSM Interrupt Enable

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - CCF Interrupt Enable

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - TXIDLE Interrupt Enable

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - TCMP0 Interrupt Enable

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - TCMP1 Interrupt Enable

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - TCMP2 Interrupt Enable

impl W<u32, Reg<u32, _IRCTRL>>

pub fn iren(&mut self) -> IREN_W<'_>

Bit 0 - Enable IrDA Module

pub fn irpw(&mut self) -> IRPW_W<'_>

Bits 1:2 - IrDA TX Pulse Width

pub fn irfilt(&mut self) -> IRFILT_W<'_>

Bit 3 - IrDA RX Filter

pub fn irprsen(&mut self) -> IRPRSEN_W<'_>

Bit 7 - IrDA PRS Channel Enable

pub fn irprssel(&mut self) -> IRPRSSEL_W<'_>

Bits 8:12 - IrDA PRS Channel Select

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:4 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 7 - PRS RX Enable

pub fn clkprssel(&mut self) -> CLKPRSSEL_W<'_>

Bits 8:12 - CLK PRS Channel Select

pub fn clkprs(&mut self) -> CLKPRS_W<'_>

Bit 15 - PRS CLK Enable

impl W<u32, Reg<u32, _I2SCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable I2S Mode

pub fn mono(&mut self) -> MONO_W<'_>

Bit 1 - Stero or Mono

pub fn justify(&mut self) -> JUSTIFY_W<'_>

Bit 2 - Justification of I2S Data

pub fn dmasplit(&mut self) -> DMASPLIT_W<'_>

Bit 3 - Separate DMA Request for Left/Right Data

pub fn delay(&mut self) -> DELAY_W<'_>

Bit 4 - Delay on I2S Data

pub fn format(&mut self) -> FORMAT_W<'_>

Bits 8:10 - I2S Word Format

impl W<u32, Reg<u32, _TIMING>>

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 16:18 - TX Frame Start Delay

pub fn cssetup(&mut self) -> CSSETUP_W<'_>

Bits 20:22 - Chip Select Setup

pub fn ics(&mut self) -> ICS_W<'_>

Bits 24:26 - Inter-character Spacing

pub fn cshold(&mut self) -> CSHOLD_W<'_>

Bits 28:30 - Chip Select Hold

impl W<u32, Reg<u32, _CTRLX>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 0 - Debug Halt

pub fn ctsinv(&mut self) -> CTSINV_W<'_>

Bit 1 - CTS Pin Inversion

pub fn ctsen(&mut self) -> CTSEN_W<'_>

Bit 2 - CTS Function Enabled

pub fn rtsinv(&mut self) -> RTSINV_W<'_>

Bit 3 - RTS Pin Inversion

impl W<u32, Reg<u32, _TIMECMP0>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 0

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 0

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP0

impl W<u32, Reg<u32, _TIMECMP1>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 1

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 1

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP1

impl W<u32, Reg<u32, _TIMECMP2>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 2

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 2

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP2

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

pub fn cspen(&mut self) -> CSPEN_W<'_>

Bit 2 - CS Pin Enable

pub fn clkpen(&mut self) -> CLKPEN_W<'_>

Bit 3 - CLK Pin Enable

pub fn ctspen(&mut self) -> CTSPEN_W<'_>

Bit 4 - CTS Pin Enable

pub fn rtspen(&mut self) -> RTSPEN_W<'_>

Bit 5 - RTS Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

pub fn csloc(&mut self) -> CSLOC_W<'_>

Bits 16:21 - I/O Location

pub fn clkloc(&mut self) -> CLKLOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn ctsloc(&mut self) -> CTSLOC_W<'_>

Bits 0:5 - I/O Location

pub fn rtsloc(&mut self) -> RTSLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 0 - USART Synchronous Mode

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 1 - Loopback Enable

pub fn ccen(&mut self) -> CCEN_W<'_>

Bit 2 - Collision Check Enable

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 3 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 4 - Multi-Processor Address-Bit

pub fn ovs(&mut self) -> OVS_W<'_>

Bits 5:6 - Oversampling

pub fn clkpol(&mut self) -> CLKPOL_W<'_>

Bit 8 - Clock Polarity

pub fn clkpha(&mut self) -> CLKPHA_W<'_>

Bit 9 - Clock Edge for Setup/Sample

pub fn msbf(&mut self) -> MSBF_W<'_>

Bit 10 - Most Significant Bit First

pub fn csma(&mut self) -> CSMA_W<'_>

Bit 11 - Action on Slave-Select in Master Mode

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 12 - TX Buffer Interrupt Level

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 13 - Receiver Input Invert

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 14 - Transmitter Output Invert

pub fn csinv(&mut self) -> CSINV_W<'_>

Bit 15 - Chip Select Invert

pub fn autocs(&mut self) -> AUTOCS_W<'_>

Bit 16 - Automatic Chip Select

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 17 - Automatic TX Tristate

pub fn scmode(&mut self) -> SCMODE_W<'_>

Bit 18 - SmartCard Mode

pub fn scretrans(&mut self) -> SCRETRANS_W<'_>

Bit 19 - SmartCard Retransmit

pub fn skipperrf(&mut self) -> SKIPPERRF_W<'_>

Bit 20 - Skip Parity Error Frames

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 21 - Bit 8 Default Value

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 22 - Halt DMA on Error

pub fn errsrx(&mut self) -> ERRSRX_W<'_>

Bit 23 - Disable RX on Error

pub fn errstx(&mut self) -> ERRSTX_W<'_>

Bit 24 - Disable TX on Error

pub fn sssearly(&mut self) -> SSSEARLY_W<'_>

Bit 25 - Synchronous Slave Setup Early

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 28 - Byteswap in Double Accesses

pub fn autotx(&mut self) -> AUTOTX_W<'_>

Bit 29 - Always Transmit When RX Not Full

pub fn mvdis(&mut self) -> MVDIS_W<'_>

Bit 30 - Majority Vote Disable

pub fn smsdelay(&mut self) -> SMSDELAY_W<'_>

Bit 31 - Synchronous Master Sample Delay

impl W<u32, Reg<u32, _FRAME>>

pub fn databits(&mut self) -> DATABITS_W<'_>

Bits 0:3 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 8:9 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bits 12:13 - Stop-Bit Mode

impl W<u32, Reg<u32, _TRIGCTRL>>

pub fn rxten(&mut self) -> RXTEN_W<'_>

Bit 4 - Receive Trigger Enable

pub fn txten(&mut self) -> TXTEN_W<'_>

Bit 5 - Transmit Trigger Enable

pub fn autotxten(&mut self) -> AUTOTXTEN_W<'_>

Bit 6 - AUTOTX Trigger Enable

pub fn txarx0en(&mut self) -> TXARX0EN_W<'_>

Bit 7 - Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL

pub fn txarx1en(&mut self) -> TXARX1EN_W<'_>

Bit 8 - Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL

pub fn txarx2en(&mut self) -> TXARX2EN_W<'_>

Bit 9 - Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL

pub fn rxatx0en(&mut self) -> RXATX0EN_W<'_>

Bit 10 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times

pub fn rxatx1en(&mut self) -> RXATX1EN_W<'_>

Bit 11 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times

pub fn rxatx2en(&mut self) -> RXATX2EN_W<'_>

Bit 12 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times

pub fn tsel(&mut self) -> TSEL_W<'_>

Bits 16:20 - Trigger PRS Channel Select

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn masteren(&mut self) -> MASTEREN_W<'_>

Bit 4 - Master Enable

pub fn masterdis(&mut self) -> MASTERDIS_W<'_>

Bit 5 - Master Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 6 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 7 - Receiver Block Disable

pub fn txtrien(&mut self) -> TXTRIEN_W<'_>

Bit 8 - Transmitter Tristate Enable

pub fn txtridis(&mut self) -> TXTRIDIS_W<'_>

Bit 9 - Transmitter Tristate Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 10 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 11 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:22 - Fractional Clock Divider

pub fn autobauden(&mut self) -> AUTOBAUDEN_W<'_>

Bit 31 - AUTOBAUD Detection Enable

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdatax(&mut self) -> TXDATAX_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat(&mut self) -> UBRXAT_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat(&mut self) -> TXTRIAT_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLEX>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat0(&mut self) -> UBRXAT0_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat0(&mut self) -> TXTRIAT0_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak0(&mut self) -> TXBREAK0_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat0(&mut self) -> TXDISAT0_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat0(&mut self) -> RXENAT0_W<'_>

Bit 15 - Enable RX After Transmission

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 16:24 - TX Data

pub fn ubrxat1(&mut self) -> UBRXAT1_W<'_>

Bit 27 - Unblock RX After Transmission

pub fn txtriat1(&mut self) -> TXTRIAT1_W<'_>

Bit 28 - Set TXTRI After Transmission

pub fn txbreak1(&mut self) -> TXBREAK1_W<'_>

Bit 29 - Transmit Data as Break

pub fn txdisat1(&mut self) -> TXDISAT1_W<'_>

Bit 30 - Clear TXEN After Transmission

pub fn rxenat1(&mut self) -> RXENAT1_W<'_>

Bit 31 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Set RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Set TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Set TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Set MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Set SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Set CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Set TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Set TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Set TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Set TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Clear RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Clear TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Clear TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Clear MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Clear SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Clear CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Clear TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Clear TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Clear TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Clear TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - RXFULL Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - TXOF Interrupt Enable

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - TXUF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - MPAF Interrupt Enable

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - SSM Interrupt Enable

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - CCF Interrupt Enable

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - TXIDLE Interrupt Enable

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - TCMP0 Interrupt Enable

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - TCMP1 Interrupt Enable

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - TCMP2 Interrupt Enable

impl W<u32, Reg<u32, _IRCTRL>>

pub fn iren(&mut self) -> IREN_W<'_>

Bit 0 - Enable IrDA Module

pub fn irpw(&mut self) -> IRPW_W<'_>

Bits 1:2 - IrDA TX Pulse Width

pub fn irfilt(&mut self) -> IRFILT_W<'_>

Bit 3 - IrDA RX Filter

pub fn irprsen(&mut self) -> IRPRSEN_W<'_>

Bit 7 - IrDA PRS Channel Enable

pub fn irprssel(&mut self) -> IRPRSSEL_W<'_>

Bits 8:12 - IrDA PRS Channel Select

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:4 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 7 - PRS RX Enable

pub fn clkprssel(&mut self) -> CLKPRSSEL_W<'_>

Bits 8:12 - CLK PRS Channel Select

pub fn clkprs(&mut self) -> CLKPRS_W<'_>

Bit 15 - PRS CLK Enable

impl W<u32, Reg<u32, _I2SCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable I2S Mode

pub fn mono(&mut self) -> MONO_W<'_>

Bit 1 - Stero or Mono

pub fn justify(&mut self) -> JUSTIFY_W<'_>

Bit 2 - Justification of I2S Data

pub fn dmasplit(&mut self) -> DMASPLIT_W<'_>

Bit 3 - Separate DMA Request for Left/Right Data

pub fn delay(&mut self) -> DELAY_W<'_>

Bit 4 - Delay on I2S Data

pub fn format(&mut self) -> FORMAT_W<'_>

Bits 8:10 - I2S Word Format

impl W<u32, Reg<u32, _TIMING>>

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 16:18 - TX Frame Start Delay

pub fn cssetup(&mut self) -> CSSETUP_W<'_>

Bits 20:22 - Chip Select Setup

pub fn ics(&mut self) -> ICS_W<'_>

Bits 24:26 - Inter-character Spacing

pub fn cshold(&mut self) -> CSHOLD_W<'_>

Bits 28:30 - Chip Select Hold

impl W<u32, Reg<u32, _CTRLX>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 0 - Debug Halt

pub fn ctsinv(&mut self) -> CTSINV_W<'_>

Bit 1 - CTS Pin Inversion

pub fn ctsen(&mut self) -> CTSEN_W<'_>

Bit 2 - CTS Function Enabled

pub fn rtsinv(&mut self) -> RTSINV_W<'_>

Bit 3 - RTS Pin Inversion

impl W<u32, Reg<u32, _TIMECMP0>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 0

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 0

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP0

impl W<u32, Reg<u32, _TIMECMP1>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 1

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 1

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP1

impl W<u32, Reg<u32, _TIMECMP2>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 2

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 2

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP2

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

pub fn cspen(&mut self) -> CSPEN_W<'_>

Bit 2 - CS Pin Enable

pub fn clkpen(&mut self) -> CLKPEN_W<'_>

Bit 3 - CLK Pin Enable

pub fn ctspen(&mut self) -> CTSPEN_W<'_>

Bit 4 - CTS Pin Enable

pub fn rtspen(&mut self) -> RTSPEN_W<'_>

Bit 5 - RTS Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

pub fn csloc(&mut self) -> CSLOC_W<'_>

Bits 16:21 - I/O Location

pub fn clkloc(&mut self) -> CLKLOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn ctsloc(&mut self) -> CTSLOC_W<'_>

Bits 0:5 - I/O Location

pub fn rtsloc(&mut self) -> RTSLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 0 - USART Synchronous Mode

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 1 - Loopback Enable

pub fn ccen(&mut self) -> CCEN_W<'_>

Bit 2 - Collision Check Enable

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 3 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 4 - Multi-Processor Address-Bit

pub fn ovs(&mut self) -> OVS_W<'_>

Bits 5:6 - Oversampling

pub fn clkpol(&mut self) -> CLKPOL_W<'_>

Bit 8 - Clock Polarity

pub fn clkpha(&mut self) -> CLKPHA_W<'_>

Bit 9 - Clock Edge for Setup/Sample

pub fn msbf(&mut self) -> MSBF_W<'_>

Bit 10 - Most Significant Bit First

pub fn csma(&mut self) -> CSMA_W<'_>

Bit 11 - Action on Slave-Select in Master Mode

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 12 - TX Buffer Interrupt Level

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 13 - Receiver Input Invert

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 14 - Transmitter Output Invert

pub fn csinv(&mut self) -> CSINV_W<'_>

Bit 15 - Chip Select Invert

pub fn autocs(&mut self) -> AUTOCS_W<'_>

Bit 16 - Automatic Chip Select

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 17 - Automatic TX Tristate

pub fn scmode(&mut self) -> SCMODE_W<'_>

Bit 18 - SmartCard Mode

pub fn scretrans(&mut self) -> SCRETRANS_W<'_>

Bit 19 - SmartCard Retransmit

pub fn skipperrf(&mut self) -> SKIPPERRF_W<'_>

Bit 20 - Skip Parity Error Frames

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 21 - Bit 8 Default Value

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 22 - Halt DMA on Error

pub fn errsrx(&mut self) -> ERRSRX_W<'_>

Bit 23 - Disable RX on Error

pub fn errstx(&mut self) -> ERRSTX_W<'_>

Bit 24 - Disable TX on Error

pub fn sssearly(&mut self) -> SSSEARLY_W<'_>

Bit 25 - Synchronous Slave Setup Early

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 28 - Byteswap in Double Accesses

pub fn autotx(&mut self) -> AUTOTX_W<'_>

Bit 29 - Always Transmit When RX Not Full

pub fn mvdis(&mut self) -> MVDIS_W<'_>

Bit 30 - Majority Vote Disable

pub fn smsdelay(&mut self) -> SMSDELAY_W<'_>

Bit 31 - Synchronous Master Sample Delay

impl W<u32, Reg<u32, _FRAME>>

pub fn databits(&mut self) -> DATABITS_W<'_>

Bits 0:3 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 8:9 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bits 12:13 - Stop-Bit Mode

impl W<u32, Reg<u32, _TRIGCTRL>>

pub fn rxten(&mut self) -> RXTEN_W<'_>

Bit 4 - Receive Trigger Enable

pub fn txten(&mut self) -> TXTEN_W<'_>

Bit 5 - Transmit Trigger Enable

pub fn autotxten(&mut self) -> AUTOTXTEN_W<'_>

Bit 6 - AUTOTX Trigger Enable

pub fn txarx0en(&mut self) -> TXARX0EN_W<'_>

Bit 7 - Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL

pub fn txarx1en(&mut self) -> TXARX1EN_W<'_>

Bit 8 - Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL

pub fn txarx2en(&mut self) -> TXARX2EN_W<'_>

Bit 9 - Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL

pub fn rxatx0en(&mut self) -> RXATX0EN_W<'_>

Bit 10 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times

pub fn rxatx1en(&mut self) -> RXATX1EN_W<'_>

Bit 11 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times

pub fn rxatx2en(&mut self) -> RXATX2EN_W<'_>

Bit 12 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times

pub fn tsel(&mut self) -> TSEL_W<'_>

Bits 16:20 - Trigger PRS Channel Select

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn masteren(&mut self) -> MASTEREN_W<'_>

Bit 4 - Master Enable

pub fn masterdis(&mut self) -> MASTERDIS_W<'_>

Bit 5 - Master Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 6 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 7 - Receiver Block Disable

pub fn txtrien(&mut self) -> TXTRIEN_W<'_>

Bit 8 - Transmitter Tristate Enable

pub fn txtridis(&mut self) -> TXTRIDIS_W<'_>

Bit 9 - Transmitter Tristate Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 10 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 11 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:22 - Fractional Clock Divider

pub fn autobauden(&mut self) -> AUTOBAUDEN_W<'_>

Bit 31 - AUTOBAUD Detection Enable

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdatax(&mut self) -> TXDATAX_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat(&mut self) -> UBRXAT_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat(&mut self) -> TXTRIAT_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLEX>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat0(&mut self) -> UBRXAT0_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat0(&mut self) -> TXTRIAT0_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak0(&mut self) -> TXBREAK0_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat0(&mut self) -> TXDISAT0_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat0(&mut self) -> RXENAT0_W<'_>

Bit 15 - Enable RX After Transmission

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 16:24 - TX Data

pub fn ubrxat1(&mut self) -> UBRXAT1_W<'_>

Bit 27 - Unblock RX After Transmission

pub fn txtriat1(&mut self) -> TXTRIAT1_W<'_>

Bit 28 - Set TXTRI After Transmission

pub fn txbreak1(&mut self) -> TXBREAK1_W<'_>

Bit 29 - Transmit Data as Break

pub fn txdisat1(&mut self) -> TXDISAT1_W<'_>

Bit 30 - Clear TXEN After Transmission

pub fn rxenat1(&mut self) -> RXENAT1_W<'_>

Bit 31 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Set RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Set TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Set TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Set MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Set SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Set CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Set TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Set TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Set TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Set TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Clear RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Clear TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Clear TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Clear MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Clear SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Clear CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Clear TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Clear TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Clear TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Clear TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - RXFULL Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - TXOF Interrupt Enable

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - TXUF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - MPAF Interrupt Enable

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - SSM Interrupt Enable

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - CCF Interrupt Enable

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - TXIDLE Interrupt Enable

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - TCMP0 Interrupt Enable

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - TCMP1 Interrupt Enable

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - TCMP2 Interrupt Enable

impl W<u32, Reg<u32, _IRCTRL>>

pub fn iren(&mut self) -> IREN_W<'_>

Bit 0 - Enable IrDA Module

pub fn irpw(&mut self) -> IRPW_W<'_>

Bits 1:2 - IrDA TX Pulse Width

pub fn irfilt(&mut self) -> IRFILT_W<'_>

Bit 3 - IrDA RX Filter

pub fn irprsen(&mut self) -> IRPRSEN_W<'_>

Bit 7 - IrDA PRS Channel Enable

pub fn irprssel(&mut self) -> IRPRSSEL_W<'_>

Bits 8:12 - IrDA PRS Channel Select

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:4 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 7 - PRS RX Enable

pub fn clkprssel(&mut self) -> CLKPRSSEL_W<'_>

Bits 8:12 - CLK PRS Channel Select

pub fn clkprs(&mut self) -> CLKPRS_W<'_>

Bit 15 - PRS CLK Enable

impl W<u32, Reg<u32, _I2SCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable I2S Mode

pub fn mono(&mut self) -> MONO_W<'_>

Bit 1 - Stero or Mono

pub fn justify(&mut self) -> JUSTIFY_W<'_>

Bit 2 - Justification of I2S Data

pub fn dmasplit(&mut self) -> DMASPLIT_W<'_>

Bit 3 - Separate DMA Request for Left/Right Data

pub fn delay(&mut self) -> DELAY_W<'_>

Bit 4 - Delay on I2S Data

pub fn format(&mut self) -> FORMAT_W<'_>

Bits 8:10 - I2S Word Format

impl W<u32, Reg<u32, _TIMING>>

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 16:18 - TX Frame Start Delay

pub fn cssetup(&mut self) -> CSSETUP_W<'_>

Bits 20:22 - Chip Select Setup

pub fn ics(&mut self) -> ICS_W<'_>

Bits 24:26 - Inter-character Spacing

pub fn cshold(&mut self) -> CSHOLD_W<'_>

Bits 28:30 - Chip Select Hold

impl W<u32, Reg<u32, _CTRLX>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 0 - Debug Halt

pub fn ctsinv(&mut self) -> CTSINV_W<'_>

Bit 1 - CTS Pin Inversion

pub fn ctsen(&mut self) -> CTSEN_W<'_>

Bit 2 - CTS Function Enabled

pub fn rtsinv(&mut self) -> RTSINV_W<'_>

Bit 3 - RTS Pin Inversion

impl W<u32, Reg<u32, _TIMECMP0>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 0

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 0

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP0

impl W<u32, Reg<u32, _TIMECMP1>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 1

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 1

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP1

impl W<u32, Reg<u32, _TIMECMP2>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 2

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 2

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP2

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

pub fn cspen(&mut self) -> CSPEN_W<'_>

Bit 2 - CS Pin Enable

pub fn clkpen(&mut self) -> CLKPEN_W<'_>

Bit 3 - CLK Pin Enable

pub fn ctspen(&mut self) -> CTSPEN_W<'_>

Bit 4 - CTS Pin Enable

pub fn rtspen(&mut self) -> RTSPEN_W<'_>

Bit 5 - RTS Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

pub fn csloc(&mut self) -> CSLOC_W<'_>

Bits 16:21 - I/O Location

pub fn clkloc(&mut self) -> CLKLOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn ctsloc(&mut self) -> CTSLOC_W<'_>

Bits 0:5 - I/O Location

pub fn rtsloc(&mut self) -> RTSLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 0 - USART Synchronous Mode

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 1 - Loopback Enable

pub fn ccen(&mut self) -> CCEN_W<'_>

Bit 2 - Collision Check Enable

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 3 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 4 - Multi-Processor Address-Bit

pub fn ovs(&mut self) -> OVS_W<'_>

Bits 5:6 - Oversampling

pub fn clkpol(&mut self) -> CLKPOL_W<'_>

Bit 8 - Clock Polarity

pub fn clkpha(&mut self) -> CLKPHA_W<'_>

Bit 9 - Clock Edge for Setup/Sample

pub fn msbf(&mut self) -> MSBF_W<'_>

Bit 10 - Most Significant Bit First

pub fn csma(&mut self) -> CSMA_W<'_>

Bit 11 - Action on Slave-Select in Master Mode

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 12 - TX Buffer Interrupt Level

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 13 - Receiver Input Invert

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 14 - Transmitter Output Invert

pub fn csinv(&mut self) -> CSINV_W<'_>

Bit 15 - Chip Select Invert

pub fn autocs(&mut self) -> AUTOCS_W<'_>

Bit 16 - Automatic Chip Select

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 17 - Automatic TX Tristate

pub fn scmode(&mut self) -> SCMODE_W<'_>

Bit 18 - SmartCard Mode

pub fn scretrans(&mut self) -> SCRETRANS_W<'_>

Bit 19 - SmartCard Retransmit

pub fn skipperrf(&mut self) -> SKIPPERRF_W<'_>

Bit 20 - Skip Parity Error Frames

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 21 - Bit 8 Default Value

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 22 - Halt DMA on Error

pub fn errsrx(&mut self) -> ERRSRX_W<'_>

Bit 23 - Disable RX on Error

pub fn errstx(&mut self) -> ERRSTX_W<'_>

Bit 24 - Disable TX on Error

pub fn sssearly(&mut self) -> SSSEARLY_W<'_>

Bit 25 - Synchronous Slave Setup Early

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 28 - Byteswap in Double Accesses

pub fn autotx(&mut self) -> AUTOTX_W<'_>

Bit 29 - Always Transmit When RX Not Full

pub fn mvdis(&mut self) -> MVDIS_W<'_>

Bit 30 - Majority Vote Disable

pub fn smsdelay(&mut self) -> SMSDELAY_W<'_>

Bit 31 - Synchronous Master Sample Delay

impl W<u32, Reg<u32, _FRAME>>

pub fn databits(&mut self) -> DATABITS_W<'_>

Bits 0:3 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 8:9 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bits 12:13 - Stop-Bit Mode

impl W<u32, Reg<u32, _TRIGCTRL>>

pub fn rxten(&mut self) -> RXTEN_W<'_>

Bit 4 - Receive Trigger Enable

pub fn txten(&mut self) -> TXTEN_W<'_>

Bit 5 - Transmit Trigger Enable

pub fn autotxten(&mut self) -> AUTOTXTEN_W<'_>

Bit 6 - AUTOTX Trigger Enable

pub fn txarx0en(&mut self) -> TXARX0EN_W<'_>

Bit 7 - Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL

pub fn txarx1en(&mut self) -> TXARX1EN_W<'_>

Bit 8 - Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL

pub fn txarx2en(&mut self) -> TXARX2EN_W<'_>

Bit 9 - Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL

pub fn rxatx0en(&mut self) -> RXATX0EN_W<'_>

Bit 10 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times

pub fn rxatx1en(&mut self) -> RXATX1EN_W<'_>

Bit 11 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times

pub fn rxatx2en(&mut self) -> RXATX2EN_W<'_>

Bit 12 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times

pub fn tsel(&mut self) -> TSEL_W<'_>

Bits 16:20 - Trigger PRS Channel Select

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn masteren(&mut self) -> MASTEREN_W<'_>

Bit 4 - Master Enable

pub fn masterdis(&mut self) -> MASTERDIS_W<'_>

Bit 5 - Master Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 6 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 7 - Receiver Block Disable

pub fn txtrien(&mut self) -> TXTRIEN_W<'_>

Bit 8 - Transmitter Tristate Enable

pub fn txtridis(&mut self) -> TXTRIDIS_W<'_>

Bit 9 - Transmitter Tristate Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 10 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 11 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:22 - Fractional Clock Divider

pub fn autobauden(&mut self) -> AUTOBAUDEN_W<'_>

Bit 31 - AUTOBAUD Detection Enable

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdatax(&mut self) -> TXDATAX_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat(&mut self) -> UBRXAT_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat(&mut self) -> TXTRIAT_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLEX>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat0(&mut self) -> UBRXAT0_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat0(&mut self) -> TXTRIAT0_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak0(&mut self) -> TXBREAK0_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat0(&mut self) -> TXDISAT0_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat0(&mut self) -> RXENAT0_W<'_>

Bit 15 - Enable RX After Transmission

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 16:24 - TX Data

pub fn ubrxat1(&mut self) -> UBRXAT1_W<'_>

Bit 27 - Unblock RX After Transmission

pub fn txtriat1(&mut self) -> TXTRIAT1_W<'_>

Bit 28 - Set TXTRI After Transmission

pub fn txbreak1(&mut self) -> TXBREAK1_W<'_>

Bit 29 - Transmit Data as Break

pub fn txdisat1(&mut self) -> TXDISAT1_W<'_>

Bit 30 - Clear TXEN After Transmission

pub fn rxenat1(&mut self) -> RXENAT1_W<'_>

Bit 31 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Set RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Set TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Set TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Set MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Set SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Set CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Set TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Set TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Set TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Set TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Clear RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Clear TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Clear TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Clear MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Clear SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Clear CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Clear TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Clear TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Clear TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Clear TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - RXFULL Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - TXOF Interrupt Enable

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - TXUF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - MPAF Interrupt Enable

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - SSM Interrupt Enable

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - CCF Interrupt Enable

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - TXIDLE Interrupt Enable

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - TCMP0 Interrupt Enable

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - TCMP1 Interrupt Enable

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - TCMP2 Interrupt Enable

impl W<u32, Reg<u32, _IRCTRL>>

pub fn iren(&mut self) -> IREN_W<'_>

Bit 0 - Enable IrDA Module

pub fn irpw(&mut self) -> IRPW_W<'_>

Bits 1:2 - IrDA TX Pulse Width

pub fn irfilt(&mut self) -> IRFILT_W<'_>

Bit 3 - IrDA RX Filter

pub fn irprsen(&mut self) -> IRPRSEN_W<'_>

Bit 7 - IrDA PRS Channel Enable

pub fn irprssel(&mut self) -> IRPRSSEL_W<'_>

Bits 8:12 - IrDA PRS Channel Select

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:4 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 7 - PRS RX Enable

pub fn clkprssel(&mut self) -> CLKPRSSEL_W<'_>

Bits 8:12 - CLK PRS Channel Select

pub fn clkprs(&mut self) -> CLKPRS_W<'_>

Bit 15 - PRS CLK Enable

impl W<u32, Reg<u32, _I2SCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable I2S Mode

pub fn mono(&mut self) -> MONO_W<'_>

Bit 1 - Stero or Mono

pub fn justify(&mut self) -> JUSTIFY_W<'_>

Bit 2 - Justification of I2S Data

pub fn dmasplit(&mut self) -> DMASPLIT_W<'_>

Bit 3 - Separate DMA Request for Left/Right Data

pub fn delay(&mut self) -> DELAY_W<'_>

Bit 4 - Delay on I2S Data

pub fn format(&mut self) -> FORMAT_W<'_>

Bits 8:10 - I2S Word Format

impl W<u32, Reg<u32, _TIMING>>

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 16:18 - TX Frame Start Delay

pub fn cssetup(&mut self) -> CSSETUP_W<'_>

Bits 20:22 - Chip Select Setup

pub fn ics(&mut self) -> ICS_W<'_>

Bits 24:26 - Inter-character Spacing

pub fn cshold(&mut self) -> CSHOLD_W<'_>

Bits 28:30 - Chip Select Hold

impl W<u32, Reg<u32, _CTRLX>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 0 - Debug Halt

pub fn ctsinv(&mut self) -> CTSINV_W<'_>

Bit 1 - CTS Pin Inversion

pub fn ctsen(&mut self) -> CTSEN_W<'_>

Bit 2 - CTS Function Enabled

pub fn rtsinv(&mut self) -> RTSINV_W<'_>

Bit 3 - RTS Pin Inversion

impl W<u32, Reg<u32, _TIMECMP0>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 0

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 0

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP0

impl W<u32, Reg<u32, _TIMECMP1>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 1

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 1

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP1

impl W<u32, Reg<u32, _TIMECMP2>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 2

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 2

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP2

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

pub fn cspen(&mut self) -> CSPEN_W<'_>

Bit 2 - CS Pin Enable

pub fn clkpen(&mut self) -> CLKPEN_W<'_>

Bit 3 - CLK Pin Enable

pub fn ctspen(&mut self) -> CTSPEN_W<'_>

Bit 4 - CTS Pin Enable

pub fn rtspen(&mut self) -> RTSPEN_W<'_>

Bit 5 - RTS Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

pub fn csloc(&mut self) -> CSLOC_W<'_>

Bits 16:21 - I/O Location

pub fn clkloc(&mut self) -> CLKLOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn ctsloc(&mut self) -> CTSLOC_W<'_>

Bits 0:5 - I/O Location

pub fn rtsloc(&mut self) -> RTSLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CONFIG>>

pub fn enbspi(&mut self) -> ENBSPI_W<'_>

Bit 0 - QSPI Enable

pub fn selclkpol(&mut self) -> SELCLKPOL_W<'_>

Bit 1 - Clock Polarity, CPOL

pub fn selclkphase(&mut self) -> SELCLKPHASE_W<'_>

Bit 2 - Clock Phase, CPHA

pub fn phymodeenable(&mut self) -> PHYMODEENABLE_W<'_>

Bit 3 - PHY Mode Enable

pub fn enbdiraccctlr(&mut self) -> ENBDIRACCCTLR_W<'_>

Bit 7 - Enable Direct Access Controller

pub fn enblegacyipmode(&mut self) -> ENBLEGACYIPMODE_W<'_>

Bit 8 - Legacy IP Mode Enable

pub fn periphseldec(&mut self) -> PERIPHSELDEC_W<'_>

Bit 9 - Peripheral Select Decode

pub fn periphcslines(&mut self) -> PERIPHCSLINES_W<'_>

Bits 10:11 - Peripheral Chip Select Lines

pub fn wrprotflash(&mut self) -> WRPROTFLASH_W<'_>

Bit 14 - Write Protect Flash Pin

pub fn enbahbaddrremap(&mut self) -> ENBAHBADDRREMAP_W<'_>

Bit 16 - Enable Address Remapping

pub fn enterxipmode(&mut self) -> ENTERXIPMODE_W<'_>

Bit 17 - Enter XIP Mode on Next READ

pub fn enterxipmodeimm(&mut self) -> ENTERXIPMODEIMM_W<'_>

Bit 18 - Enter XIP Mode Immediately

pub fn mstrbauddiv(&mut self) -> MSTRBAUDDIV_W<'_>

Bits 19:22 - Master Mode Baud Rate Divisor

pub fn enableahbdecoder(&mut self) -> ENABLEAHBDECODER_W<'_>

Bit 23 - Enable Address Decoder

pub fn enabledtrprotocol(&mut self) -> ENABLEDTRPROTOCOL_W<'_>

Bit 24 - Enable DTR Protocol

pub fn pipelinephy(&mut self) -> PIPELINEPHY_W<'_>

Bit 25 - Pipeline PHY Mode Enable

pub fn crcenable(&mut self) -> CRCENABLE_W<'_>

Bit 29 - CRC Enable Bit

pub fn dualbyteopcodeen(&mut self) -> DUALBYTEOPCODEEN_W<'_>

Bit 30 - Dual-byte Opcode Mode Enable Bit

impl W<u32, Reg<u32, _DEVINSTRRDCONFIG>>

pub fn rdopcodenonxip(&mut self) -> RDOPCODENONXIP_W<'_>

Bits 0:7 - Read Opcode in Non-XIP Mode

pub fn instrtype(&mut self) -> INSTRTYPE_W<'_>

Bits 8:9 - Instruction Type

pub fn ddren(&mut self) -> DDREN_W<'_>

Bit 10 - DDR Enable

pub fn addrxfertypestdmode(&mut self) -> ADDRXFERTYPESTDMODE_W<'_>

Bits 12:13 - Address Transfer Type for Standard SPI Modes

pub fn dataxfertypeextmode(&mut self) -> DATAXFERTYPEEXTMODE_W<'_>

Bits 16:17 - Data Transfer Type for Standard SPI Modes

pub fn modebitenable(&mut self) -> MODEBITENABLE_W<'_>

Bit 20 - Mode Bit Enable

pub fn dummyrdclkcycles(&mut self) -> DUMMYRDCLKCYCLES_W<'_>

Bits 24:28 - Dummy Read Clock Cycles

impl W<u32, Reg<u32, _DEVINSTRWRCONFIG>>

pub fn wropcode(&mut self) -> WROPCODE_W<'_>

Bits 0:7 - Write Opcode

pub fn weldis(&mut self) -> WELDIS_W<'_>

Bit 8 - WEL Disable

pub fn addrxfertypestdmode(&mut self) -> ADDRXFERTYPESTDMODE_W<'_>

Bits 12:13 - Address Transfer Type for Standard SPI Modes

pub fn dataxfertypeextmode(&mut self) -> DATAXFERTYPEEXTMODE_W<'_>

Bits 16:17 - Data Transfer Type for Standard SPI Modes

pub fn dummywrclkcycles(&mut self) -> DUMMYWRCLKCYCLES_W<'_>

Bits 24:28 - Dummy Write Clock Cycles

impl W<u32, Reg<u32, _DEVDELAY>>

pub fn dinit(&mut self) -> DINIT_W<'_>

Bits 0:7 - Clock Delay for CS

pub fn dafter(&mut self) -> DAFTER_W<'_>

Bits 8:15 - Clock Delay for Last Transaction Bit

pub fn dbtwn(&mut self) -> DBTWN_W<'_>

Bits 16:23 - Clock Delay Between Two Chip Selects

pub fn dnss(&mut self) -> DNSS_W<'_>

Bits 24:31 - Clock Delay for Chip Select Deassert

impl W<u32, Reg<u32, _RDDATACAPTURE>>

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 0 - Bypass the Adapted Loopback Clock Circuit

pub fn delay(&mut self) -> DELAY_W<'_>

Bits 1:4 - Read Delay

pub fn dqsenable(&mut self) -> DQSENABLE_W<'_>

Bit 8 - DQS Enable Bit

pub fn ddrreaddelay(&mut self) -> DDRREADDELAY_W<'_>

Bits 16:19 - DDR Read Delay

impl W<u32, Reg<u32, _DEVSIZECONFIG>>

pub fn numaddrbytes(&mut self) -> NUMADDRBYTES_W<'_>

Bits 0:3 - Number of Address Bytes

pub fn bytesperdevicepage(&mut self) -> BYTESPERDEVICEPAGE_W<'_>

Bits 4:15 - Number of Bytes Per Device Page

pub fn bytespersubsector(&mut self) -> BYTESPERSUBSECTOR_W<'_>

Bits 16:20 - Number of Bytes Per Block

pub fn memsizeoncs0(&mut self) -> MEMSIZEONCS0_W<'_>

Bits 21:22 - Size of Flash Device Connected to CS[0] Pin

pub fn memsizeoncs1(&mut self) -> MEMSIZEONCS1_W<'_>

Bits 23:24 - Size of Flash Device Connected to CS[1] Pin

impl W<u32, Reg<u32, _SRAMPARTITIONCFG>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:7 - Indirect Read Partition Size

impl W<u32, Reg<u32, _INDAHBADDRTRIGGER>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Indirect Address Trigger Register

impl W<u32, Reg<u32, _REMAPADDR>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Remap Address Value

impl W<u32, Reg<u32, _MODEBITCONFIG>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:7 - Mode Bits

pub fn chunksize(&mut self) -> CHUNKSIZE_W<'_>

Bits 8:10 - Chunk Size

pub fn crcoutenable(&mut self) -> CRCOUTENABLE_W<'_>

Bit 15 - CRC# Output Enable Bit

impl W<u32, Reg<u32, _TXTHRESH>>

pub fn level(&mut self) -> LEVEL_W<'_>

Bits 0:4 - Threshold Level

impl W<u32, Reg<u32, _RXTHRESH>>

pub fn level(&mut self) -> LEVEL_W<'_>

Bits 0:4 - Threshold Level

impl W<u32, Reg<u32, _WRITECOMPLETIONCTRL>>

pub fn opcode(&mut self) -> OPCODE_W<'_>

Bits 0:7 - Opcode

pub fn pollingbitindex(&mut self) -> POLLINGBITINDEX_W<'_>

Bits 8:10 - Polling Bit Index

pub fn pollingpolarity(&mut self) -> POLLINGPOLARITY_W<'_>

Bit 13 - Polling Polarity

pub fn disablepolling(&mut self) -> DISABLEPOLLING_W<'_>

Bit 14 - Disable Polling

pub fn enablepollingexp(&mut self) -> ENABLEPOLLINGEXP_W<'_>

Bit 15 - Enable Polling Expiration

pub fn pollcount(&mut self) -> POLLCOUNT_W<'_>

Bits 16:23 - Poll Count

pub fn pollrepdelay(&mut self) -> POLLREPDELAY_W<'_>

Bits 24:31 - Poll Repetition Delay

impl W<u32, Reg<u32, _NOOFPOLLSBEFEXP>>

pub fn noofpollsbefexp(&mut self) -> NOOFPOLLSBEFEXP_W<'_>

Bits 0:31 - Number of Polls Cycles Before Expiration

impl W<u32, Reg<u32, _IRQSTATUS>>

pub fn modemfail(&mut self) -> MODEMFAIL_W<'_>

Bit 0 - Mode M Failure

pub fn underflowdet(&mut self) -> UNDERFLOWDET_W<'_>

Bit 1 - Underflow Detected

pub fn indirectopdone(&mut self) -> INDIRECTOPDONE_W<'_>

Bit 2 - Indirect Operation Complete

pub fn indirectreadreject(&mut self) -> INDIRECTREADREJECT_W<'_>

Bit 3 - Indirect Operation Was Requested but Could Not Be Accepted

pub fn protwrattempt(&mut self) -> PROTWRATTEMPT_W<'_>

Bit 4 - Write to Protected Area Was Attempted and Rejected

pub fn illegalaccessdet(&mut self) -> ILLEGALACCESSDET_W<'_>

Bit 5 - Illegal Memory Access Has Been Detected

pub fn indirectxferlevelbreach(&mut self) -> INDIRECTXFERLEVELBREACH_W<'_>

Bit 6 - Indirect Transfer Watermark Level Breached

pub fn recvoverflow(&mut self) -> RECVOVERFLOW_W<'_>

Bit 7 - Receive Overflow

pub fn txfifonotfull(&mut self) -> TXFIFONOTFULL_W<'_>

Bit 8 - Small TX FIFO Not Full

pub fn txfifofull(&mut self) -> TXFIFOFULL_W<'_>

Bit 9 - Small TX FIFO Full

pub fn rxfifonotempty(&mut self) -> RXFIFONOTEMPTY_W<'_>

Bit 10 - Small RX FIFO Not Empty

pub fn rxfifofull(&mut self) -> RXFIFOFULL_W<'_>

Bit 11 - Small RX FIFO Full

pub fn indrdsramfull(&mut self) -> INDRDSRAMFULL_W<'_>

Bit 12 - Indirect Read Partition Overflow

pub fn pollexpint(&mut self) -> POLLEXPINT_W<'_>

Bit 13 - The Maximum Number of Programmed Polls Cycles is Expired

pub fn stigreqint(&mut self) -> STIGREQINT_W<'_>

Bit 14 - The Controller is Ready for Getting Another STIG Request

pub fn rxcrcdataerr(&mut self) -> RXCRCDATAERR_W<'_>

Bit 16 - RX CRC Data Error

pub fn rxcrcdataval(&mut self) -> RXCRCDATAVAL_W<'_>

Bit 17 - RX CRC Data Valid

pub fn txcrcchunkbrk(&mut self) -> TXCRCCHUNKBRK_W<'_>

Bit 18 - TX CRC Chunk Was Broken

impl W<u32, Reg<u32, _IRQMASK>>

pub fn modemfailmask(&mut self) -> MODEMFAILMASK_W<'_>

Bit 0 - Mode M Failure Mask

pub fn underflowdetmask(&mut self) -> UNDERFLOWDETMASK_W<'_>

Bit 1 - Underflow Detected Mask

pub fn indirectopdonemask(&mut self) -> INDIRECTOPDONEMASK_W<'_>

Bit 2 - Indirect Complete Mask

pub fn indirectreadrejectmask(&mut self) -> INDIRECTREADREJECTMASK_W<'_>

Bit 3 - Indirect Read Reject Mask

pub fn protwrattemptmask(&mut self) -> PROTWRATTEMPTMASK_W<'_>

Bit 4 - Protected Area Write Attempt Mask

pub fn illegalaccessdetmask(&mut self) -> ILLEGALACCESSDETMASK_W<'_>

Bit 5 - Illegal Access Detected Mask

pub fn indirectxferlevelbreachmask(
    &mut self
) -> INDIRECTXFERLEVELBREACHMASK_W<'_>

Bit 6 - Transfer Watermark Breach Mask

pub fn recvoverflowmask(&mut self) -> RECVOVERFLOWMASK_W<'_>

Bit 7 - Receive Overflow Mask

pub fn txfifonotfullmask(&mut self) -> TXFIFONOTFULLMASK_W<'_>

Bit 8 - Small TX FIFO Not Full Mask

pub fn txfifofullmask(&mut self) -> TXFIFOFULLMASK_W<'_>

Bit 9 - Small TX FIFO Full Mask

pub fn rxfifonotemptymask(&mut self) -> RXFIFONOTEMPTYMASK_W<'_>

Bit 10 - Small RX FIFO Not Empty Mask

pub fn rxfifofullmask(&mut self) -> RXFIFOFULLMASK_W<'_>

Bit 11 - Small RX FIFO Full Mask

pub fn indrdsramfullmask(&mut self) -> INDRDSRAMFULLMASK_W<'_>

Bit 12 - Indirect Read Partition Overflow Mask

pub fn pollexpintmask(&mut self) -> POLLEXPINTMASK_W<'_>

Bit 13 - Polling Expiration Detected Mask

pub fn stigreqmask(&mut self) -> STIGREQMASK_W<'_>

Bit 14 - STIG Request Completion Mask

pub fn rxcrcdataerrmask(&mut self) -> RXCRCDATAERRMASK_W<'_>

Bit 16 - RX CRC Data Error Mask

pub fn rxcrcdatavalmask(&mut self) -> RXCRCDATAVALMASK_W<'_>

Bit 17 - RX CRC Data Valid Mask

pub fn txcrcchunkbrkmask(&mut self) -> TXCRCCHUNKBRKMASK_W<'_>

Bit 18 - TX CRC Chunk Was Broken Mask

impl W<u32, Reg<u32, _LOWERWRPROT>>

pub fn subsector(&mut self) -> SUBSECTOR_W<'_>

Bits 0:31 - Lower Block Number

impl W<u32, Reg<u32, _UPPERWRPROT>>

pub fn subsector(&mut self) -> SUBSECTOR_W<'_>

Bits 0:31 - Upper Block Number

impl W<u32, Reg<u32, _WRPROTCTRL>>

pub fn inv(&mut self) -> INV_W<'_>

Bit 0 - Write Protection Inversion Bit

pub fn enb(&mut self) -> ENB_W<'_>

Bit 1 - Write Protection Enable Bit

impl W<u32, Reg<u32, _INDIRECTREADXFERCTRL>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Indirect Read

pub fn cancel(&mut self) -> CANCEL_W<'_>

Bit 1 - Cancel Indirect Read

pub fn sramfull(&mut self) -> SRAMFULL_W<'_>

Bit 3 - SRAM Full

pub fn indopsdonestatus(&mut self) -> INDOPSDONESTATUS_W<'_>

Bit 5 - Indirect Completion Status

impl W<u32, Reg<u32, _INDIRECTREADXFERWATERMARK>>

pub fn level(&mut self) -> LEVEL_W<'_>

Bits 0:31 - Watermark Value

impl W<u32, Reg<u32, _INDIRECTREADXFERSTART>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Indirect Read Transfer Start Address

impl W<u32, Reg<u32, _INDIRECTREADXFERNUMBYTES>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Indirect Read Transfer Number Bytes

impl W<u32, Reg<u32, _INDIRECTWRITEXFERCTRL>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Indirect Write

pub fn cancel(&mut self) -> CANCEL_W<'_>

Bit 1 - Cancel Indirect Write

pub fn indopsdonestatus(&mut self) -> INDOPSDONESTATUS_W<'_>

Bit 5 - Indirect Completion Status

impl W<u32, Reg<u32, _INDIRECTWRITEXFERWATERMARK>>

pub fn level(&mut self) -> LEVEL_W<'_>

Bits 0:31 - Watermark Value

impl W<u32, Reg<u32, _INDIRECTWRITEXFERSTART>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Start of Indirect Access

impl W<u32, Reg<u32, _INDIRECTWRITEXFERNUMBYTES>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Indirect Number of Bytes

impl W<u32, Reg<u32, _INDIRECTTRIGGERADDRRANGE>>

pub fn indrangewidth(&mut self) -> INDRANGEWIDTH_W<'_>

Bits 0:3 - Indirect Trigger Address Width

impl W<u32, Reg<u32, _FLASHCOMMANDCTRLMEM>>

pub fn triggermembankreq(&mut self) -> TRIGGERMEMBANKREQ_W<'_>

Bit 0 - Trigger the Memory Bank Data Request

pub fn nbofstigreadbytes(&mut self) -> NBOFSTIGREADBYTES_W<'_>

Bits 16:18 - Number of Read Bytes for the Extended STIG

pub fn membankaddr(&mut self) -> MEMBANKADDR_W<'_>

Bits 20:28 - Memory Bank Address

impl W<u32, Reg<u32, _FLASHCMDCTRL>>

pub fn cmdexec(&mut self) -> CMDEXEC_W<'_>

Bit 0 - Execute the Command

pub fn stigmembanken(&mut self) -> STIGMEMBANKEN_W<'_>

Bit 2 - STIG Memory Bank Enable Bit

pub fn numdummycycles(&mut self) -> NUMDUMMYCYCLES_W<'_>

Bits 7:11 - Number of Dummy Cycles

pub fn numwrdatabytes(&mut self) -> NUMWRDATABYTES_W<'_>

Bits 12:14 - Number of Write Data Bytes

pub fn enbwritedata(&mut self) -> ENBWRITEDATA_W<'_>

Bit 15 - Write Data Enable

pub fn numaddrbytes(&mut self) -> NUMADDRBYTES_W<'_>

Bits 16:17 - Number of Address Bytes

pub fn enbmodebit(&mut self) -> ENBMODEBIT_W<'_>

Bit 18 - Mode Bit Enable

pub fn enbcomdaddr(&mut self) -> ENBCOMDADDR_W<'_>

Bit 19 - Command Address Enable

pub fn numrddatabytes(&mut self) -> NUMRDDATABYTES_W<'_>

Bits 20:22 - Number of Read Data Bytes

pub fn enbreaddata(&mut self) -> ENBREADDATA_W<'_>

Bit 23 - Read Data Enable

pub fn cmdopcode(&mut self) -> CMDOPCODE_W<'_>

Bits 24:31 - Command Opcode

impl W<u32, Reg<u32, _FLASHCMDADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Command Address

impl W<u32, Reg<u32, _FLASHWRDATALOWER>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Command Write Data Lower Byte

impl W<u32, Reg<u32, _FLASHWRDATAUPPER>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Command Write Data Upper Byte

impl W<u32, Reg<u32, _POLLINGFLASHSTATUS>>

pub fn devicestatusnbdummy(&mut self) -> DEVICESTATUSNBDUMMY_W<'_>

Bits 16:19 - Auto-polling Dummy Cycles

impl W<u32, Reg<u32, _PHYCONFIGURATION>>

pub fn phyconfigrxdlldelay(&mut self) -> PHYCONFIGRXDLLDELAY_W<'_>

Bits 0:6 - RX DLL Delay

pub fn phyconfigtxdlldelay(&mut self) -> PHYCONFIGTXDLLDELAY_W<'_>

Bits 16:22 - TX DLL Delay

pub fn phyconfigresync(&mut self) -> PHYCONFIGRESYNC_W<'_>

Bit 31 - PHY Config Resync

impl W<u32, Reg<u32, _OPCODEEXTLOWER>>

pub fn extstigopcode(&mut self) -> EXTSTIGOPCODE_W<'_>

Bits 0:7 - STIG Opcode Extension

pub fn extpollopcode(&mut self) -> EXTPOLLOPCODE_W<'_>

Bits 8:15 - Polling Opcode Extension

pub fn extwriteopcode(&mut self) -> EXTWRITEOPCODE_W<'_>

Bits 16:23 - Write Opcode Extension

pub fn extreadopcode(&mut self) -> EXTREADOPCODE_W<'_>

Bits 24:31 - Read Opcode Extension

impl W<u32, Reg<u32, _OPCODEEXTUPPER>>

pub fn extwelopcode(&mut self) -> EXTWELOPCODE_W<'_>

Bits 16:23 - WEL Opcode Extension

pub fn welopcode(&mut self) -> WELOPCODE_W<'_>

Bits 24:31 - WEL Opcode

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn sclkpen(&mut self) -> SCLKPEN_W<'_>

Bit 0 - SCLK Pin Enable

pub fn cs0pen(&mut self) -> CS0PEN_W<'_>

Bit 1 - CS0 Pin Enable

pub fn cs1pen(&mut self) -> CS1PEN_W<'_>

Bit 2 - CS1 Pin Enable

pub fn dq0pen(&mut self) -> DQ0PEN_W<'_>

Bit 5 - DQ0 Pin Enable

pub fn dq1pen(&mut self) -> DQ1PEN_W<'_>

Bit 6 - DQ1 Pin Enable

pub fn dq2pen(&mut self) -> DQ2PEN_W<'_>

Bit 7 - DQ2 Pin Enable

pub fn dq3pen(&mut self) -> DQ3PEN_W<'_>

Bit 8 - DQ3 Pin Enable

pub fn dq4pen(&mut self) -> DQ4PEN_W<'_>

Bit 9 - DQ4 Pin Enable

pub fn dq5pen(&mut self) -> DQ5PEN_W<'_>

Bit 10 - DQ5 Pin Enable

pub fn dq6pen(&mut self) -> DQ6PEN_W<'_>

Bit 11 - DQ6 Pin Enable

pub fn dq7pen(&mut self) -> DQ7PEN_W<'_>

Bit 12 - DQ7 Pin Enable

pub fn dqspen(&mut self) -> DQSPEN_W<'_>

Bit 13 - DQS Pin Enable

pub fn sclkinpen(&mut self) -> SCLKINPEN_W<'_>

Bit 14 - SCLKIN Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn qspiloc(&mut self) -> QSPILOC_W<'_>

Bits 0:5 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 0 - Automatic Transmitter Tristate

pub fn databits(&mut self) -> DATABITS_W<'_>

Bit 1 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 2:3 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bit 4 - Stop-Bit Mode

pub fn inv(&mut self) -> INV_W<'_>

Bit 5 - Invert Input and Output

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 6 - Clear RX DMA on Error

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 7 - Loopback Enable

pub fn sfubrx(&mut self) -> SFUBRX_W<'_>

Bit 8 - Start-Frame UnBlock RX

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 9 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 10 - Multi-Processor Address-Bit

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 11 - Bit 8 Default Value

pub fn rxdmawu(&mut self) -> RXDMAWU_W<'_>

Bit 12 - RX DMA Wakeup

pub fn txdmawu(&mut self) -> TXDMAWU_W<'_>

Bit 13 - TX DMA Wakeup

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 14:15 - TX Delay Transmission

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 4 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 5 - Receiver Block Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 6 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 7 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:16 - Fractional Clock Divider

impl W<u32, Reg<u32, _STARTFRAME>>

pub fn startframe(&mut self) -> STARTFRAME_W<'_>

Bits 0:8 - Start Frame

impl W<u32, Reg<u32, _SIGFRAME>>

pub fn sigframe(&mut self) -> SIGFRAME_W<'_>

Bits 0:8 - Signal Frame

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:8 - TX Data

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Disable TX After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 3 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 4 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 5 - Set TXOF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 6 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 7 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 8 - Set MPAF Interrupt Flag

pub fn startf(&mut self) -> STARTF_W<'_>

Bit 9 - Set STARTF Interrupt Flag

pub fn sigf(&mut self) -> SIGF_W<'_>

Bit 10 - Set SIGF Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 3 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 4 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 5 - Clear TXOF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 6 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 7 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 8 - Clear MPAF Interrupt Flag

pub fn startf(&mut self) -> STARTF_W<'_>

Bit 9 - Clear STARTF Interrupt Flag

pub fn sigf(&mut self) -> SIGF_W<'_>

Bit 10 - Clear SIGF Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 3 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 4 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 5 - TXOF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 6 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 7 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 8 - MPAF Interrupt Enable

pub fn startf(&mut self) -> STARTF_W<'_>

Bit 9 - STARTF Interrupt Enable

pub fn sigf(&mut self) -> SIGF_W<'_>

Bit 10 - SIGF Interrupt Enable

impl W<u32, Reg<u32, _PULSECTRL>>

pub fn pulsew(&mut self) -> PULSEW_W<'_>

Bits 0:3 - Pulse Width

pub fn pulseen(&mut self) -> PULSEEN_W<'_>

Bit 4 - Pulse Generator/Extender Enable

pub fn pulsefilt(&mut self) -> PULSEFILT_W<'_>

Bit 5 - Pulse Filter

impl W<u32, Reg<u32, _FREEZE>>

pub fn regfreeze(&mut self) -> REGFREEZE_W<'_>

Bit 0 - Register Update Freeze

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:4 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 5 - PRS RX Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 0 - Automatic Transmitter Tristate

pub fn databits(&mut self) -> DATABITS_W<'_>

Bit 1 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 2:3 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bit 4 - Stop-Bit Mode

pub fn inv(&mut self) -> INV_W<'_>

Bit 5 - Invert Input and Output

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 6 - Clear RX DMA on Error

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 7 - Loopback Enable

pub fn sfubrx(&mut self) -> SFUBRX_W<'_>

Bit 8 - Start-Frame UnBlock RX

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 9 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 10 - Multi-Processor Address-Bit

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 11 - Bit 8 Default Value

pub fn rxdmawu(&mut self) -> RXDMAWU_W<'_>

Bit 12 - RX DMA Wakeup

pub fn txdmawu(&mut self) -> TXDMAWU_W<'_>

Bit 13 - TX DMA Wakeup

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 14:15 - TX Delay Transmission

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 4 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 5 - Receiver Block Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 6 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 7 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:16 - Fractional Clock Divider

impl W<u32, Reg<u32, _STARTFRAME>>

pub fn startframe(&mut self) -> STARTFRAME_W<'_>

Bits 0:8 - Start Frame

impl W<u32, Reg<u32, _SIGFRAME>>

pub fn sigframe(&mut self) -> SIGFRAME_W<'_>

Bits 0:8 - Signal Frame

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:8 - TX Data

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Disable TX After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 3 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 4 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 5 - Set TXOF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 6 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 7 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 8 - Set MPAF Interrupt Flag

pub fn startf(&mut self) -> STARTF_W<'_>

Bit 9 - Set STARTF Interrupt Flag

pub fn sigf(&mut self) -> SIGF_W<'_>

Bit 10 - Set SIGF Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 3 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 4 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 5 - Clear TXOF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 6 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 7 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 8 - Clear MPAF Interrupt Flag

pub fn startf(&mut self) -> STARTF_W<'_>

Bit 9 - Clear STARTF Interrupt Flag

pub fn sigf(&mut self) -> SIGF_W<'_>

Bit 10 - Clear SIGF Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 3 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 4 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 5 - TXOF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 6 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 7 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 8 - MPAF Interrupt Enable

pub fn startf(&mut self) -> STARTF_W<'_>

Bit 9 - STARTF Interrupt Enable

pub fn sigf(&mut self) -> SIGF_W<'_>

Bit 10 - SIGF Interrupt Enable

impl W<u32, Reg<u32, _PULSECTRL>>

pub fn pulsew(&mut self) -> PULSEW_W<'_>

Bits 0:3 - Pulse Width

pub fn pulseen(&mut self) -> PULSEEN_W<'_>

Bit 4 - Pulse Generator/Extender Enable

pub fn pulsefilt(&mut self) -> PULSEFILT_W<'_>

Bit 5 - Pulse Filter

impl W<u32, Reg<u32, _FREEZE>>

pub fn regfreeze(&mut self) -> REGFREEZE_W<'_>

Bit 0 - Register Update Freeze

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:4 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 5 - PRS RX Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn repmode(&mut self) -> REPMODE_W<'_>

Bits 0:1 - Repeat Mode

pub fn ufoa0(&mut self) -> UFOA0_W<'_>

Bits 2:3 - Underflow Output Action 0

pub fn ufoa1(&mut self) -> UFOA1_W<'_>

Bits 4:5 - Underflow Output Action 1

pub fn opol0(&mut self) -> OPOL0_W<'_>

Bit 6 - Output 0 Polarity

pub fn opol1(&mut self) -> OPOL1_W<'_>

Bit 7 - Output 1 Polarity

pub fn buftop(&mut self) -> BUFTOP_W<'_>

Bit 8 - Buffered Top

pub fn comp0top(&mut self) -> COMP0TOP_W<'_>

Bit 9 - Compare Value 0 is Top Value

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 12 - Debug Mode Run Enable

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start LETIMER

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop LETIMER

pub fn clear(&mut self) -> CLEAR_W<'_>

Bit 2 - Clear LETIMER

pub fn cto0(&mut self) -> CTO0_W<'_>

Bit 3 - Clear Toggle Output 0

pub fn cto1(&mut self) -> CTO1_W<'_>

Bit 4 - Clear Toggle Output 1

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _COMP0>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bits 0:15 - Compare Value 0

impl W<u32, Reg<u32, _COMP1>>

pub fn comp1(&mut self) -> COMP1_W<'_>

Bits 0:15 - Compare Value 1

impl W<u32, Reg<u32, _REP0>>

pub fn rep0(&mut self) -> REP0_W<'_>

Bits 0:7 - Repeat Counter 0

impl W<u32, Reg<u32, _REP1>>

pub fn rep1(&mut self) -> REP1_W<'_>

Bits 0:7 - Repeat Counter 1

impl W<u32, Reg<u32, _IFS>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Set COMP0 Interrupt Flag

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Set COMP1 Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 2 - Set UF Interrupt Flag

pub fn rep0(&mut self) -> REP0_W<'_>

Bit 3 - Set REP0 Interrupt Flag

pub fn rep1(&mut self) -> REP1_W<'_>

Bit 4 - Set REP1 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Clear COMP0 Interrupt Flag

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Clear COMP1 Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 2 - Clear UF Interrupt Flag

pub fn rep0(&mut self) -> REP0_W<'_>

Bit 3 - Clear REP0 Interrupt Flag

pub fn rep1(&mut self) -> REP1_W<'_>

Bit 4 - Clear REP1 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - COMP0 Interrupt Enable

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - COMP1 Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 2 - UF Interrupt Enable

pub fn rep0(&mut self) -> REP0_W<'_>

Bit 3 - REP0 Interrupt Enable

pub fn rep1(&mut self) -> REP1_W<'_>

Bit 4 - REP1 Interrupt Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn out0pen(&mut self) -> OUT0PEN_W<'_>

Bit 0 - Output 0 Pin Enable

pub fn out1pen(&mut self) -> OUT1PEN_W<'_>

Bit 1 - Output 1 Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn out0loc(&mut self) -> OUT0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn out1loc(&mut self) -> OUT1LOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _PRSSEL>>

pub fn prsstartsel(&mut self) -> PRSSTARTSEL_W<'_>

Bits 0:4 - PRS Start Select

pub fn prsstopsel(&mut self) -> PRSSTOPSEL_W<'_>

Bits 6:10 - PRS Stop Select

pub fn prsclearsel(&mut self) -> PRSCLEARSEL_W<'_>

Bits 12:16 - PRS Clear Select

pub fn prsstartmode(&mut self) -> PRSSTARTMODE_W<'_>

Bits 18:19 - PRS Start Mode

pub fn prsstopmode(&mut self) -> PRSSTOPMODE_W<'_>

Bits 22:23 - PRS Stop Mode

pub fn prsclearmode(&mut self) -> PRSCLEARMODE_W<'_>

Bits 26:27 - PRS Clear Mode

impl W<u32, Reg<u32, _CTRL>>

pub fn repmode(&mut self) -> REPMODE_W<'_>

Bits 0:1 - Repeat Mode

pub fn ufoa0(&mut self) -> UFOA0_W<'_>

Bits 2:3 - Underflow Output Action 0

pub fn ufoa1(&mut self) -> UFOA1_W<'_>

Bits 4:5 - Underflow Output Action 1

pub fn opol0(&mut self) -> OPOL0_W<'_>

Bit 6 - Output 0 Polarity

pub fn opol1(&mut self) -> OPOL1_W<'_>

Bit 7 - Output 1 Polarity

pub fn buftop(&mut self) -> BUFTOP_W<'_>

Bit 8 - Buffered Top

pub fn comp0top(&mut self) -> COMP0TOP_W<'_>

Bit 9 - Compare Value 0 is Top Value

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 12 - Debug Mode Run Enable

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start LETIMER

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop LETIMER

pub fn clear(&mut self) -> CLEAR_W<'_>

Bit 2 - Clear LETIMER

pub fn cto0(&mut self) -> CTO0_W<'_>

Bit 3 - Clear Toggle Output 0

pub fn cto1(&mut self) -> CTO1_W<'_>

Bit 4 - Clear Toggle Output 1

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _COMP0>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bits 0:15 - Compare Value 0

impl W<u32, Reg<u32, _COMP1>>

pub fn comp1(&mut self) -> COMP1_W<'_>

Bits 0:15 - Compare Value 1

impl W<u32, Reg<u32, _REP0>>

pub fn rep0(&mut self) -> REP0_W<'_>

Bits 0:7 - Repeat Counter 0

impl W<u32, Reg<u32, _REP1>>

pub fn rep1(&mut self) -> REP1_W<'_>

Bits 0:7 - Repeat Counter 1

impl W<u32, Reg<u32, _IFS>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Set COMP0 Interrupt Flag

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Set COMP1 Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 2 - Set UF Interrupt Flag

pub fn rep0(&mut self) -> REP0_W<'_>

Bit 3 - Set REP0 Interrupt Flag

pub fn rep1(&mut self) -> REP1_W<'_>

Bit 4 - Set REP1 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Clear COMP0 Interrupt Flag

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Clear COMP1 Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 2 - Clear UF Interrupt Flag

pub fn rep0(&mut self) -> REP0_W<'_>

Bit 3 - Clear REP0 Interrupt Flag

pub fn rep1(&mut self) -> REP1_W<'_>

Bit 4 - Clear REP1 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - COMP0 Interrupt Enable

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - COMP1 Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 2 - UF Interrupt Enable

pub fn rep0(&mut self) -> REP0_W<'_>

Bit 3 - REP0 Interrupt Enable

pub fn rep1(&mut self) -> REP1_W<'_>

Bit 4 - REP1 Interrupt Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn out0pen(&mut self) -> OUT0PEN_W<'_>

Bit 0 - Output 0 Pin Enable

pub fn out1pen(&mut self) -> OUT1PEN_W<'_>

Bit 1 - Output 1 Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn out0loc(&mut self) -> OUT0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn out1loc(&mut self) -> OUT1LOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _PRSSEL>>

pub fn prsstartsel(&mut self) -> PRSSTARTSEL_W<'_>

Bits 0:4 - PRS Start Select

pub fn prsstopsel(&mut self) -> PRSSTOPSEL_W<'_>

Bits 6:10 - PRS Stop Select

pub fn prsclearsel(&mut self) -> PRSCLEARSEL_W<'_>

Bits 12:16 - PRS Clear Select

pub fn prsstartmode(&mut self) -> PRSSTARTMODE_W<'_>

Bits 18:19 - PRS Start Mode

pub fn prsstopmode(&mut self) -> PRSSTOPMODE_W<'_>

Bits 22:23 - PRS Stop Mode

pub fn prsclearmode(&mut self) -> PRSCLEARMODE_W<'_>

Bits 26:27 - PRS Clear Mode

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable CRYOTIMER

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 1 - Debug Mode Run Enable

pub fn oscsel(&mut self) -> OSCSEL_W<'_>

Bits 2:3 - Select Low Frequency Oscillator

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 5:7 - Prescaler Setting

impl W<u32, Reg<u32, _PERIODSEL>>

pub fn periodsel(&mut self) -> PERIODSEL_W<'_>

Bits 0:5 - Interrupts/Wakeup Events Period Setting

impl W<u32, Reg<u32, _EM4WUEN>>

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bit 0 - EM4 Wake-up Enable

impl W<u32, Reg<u32, _IFS>>

pub fn period(&mut self) -> PERIOD_W<'_>

Bit 0 - Set PERIOD Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn period(&mut self) -> PERIOD_W<'_>

Bit 0 - Clear PERIOD Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn period(&mut self) -> PERIOD_W<'_>

Bit 0 - PERIOD Interrupt Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:2 - Mode Select

pub fn filt(&mut self) -> FILT_W<'_>

Bit 3 - Enable Digital Pulse Width Filter

pub fn rsten(&mut self) -> RSTEN_W<'_>

Bit 4 - Enable PCNT Clock Domain Reset

pub fn cntrsten(&mut self) -> CNTRSTEN_W<'_>

Bit 5 - Enable CNT Reset

pub fn auxcntrsten(&mut self) -> AUXCNTRSTEN_W<'_>

Bit 6 - Enable AUXCNT Reset

pub fn debughalt(&mut self) -> DEBUGHALT_W<'_>

Bit 7 - Debug Mode Halt Enable

pub fn hyst(&mut self) -> HYST_W<'_>

Bit 8 - Enable Hysteresis

pub fn s1cdir(&mut self) -> S1CDIR_W<'_>

Bit 9 - Count Direction Determined By S1

pub fn cntev(&mut self) -> CNTEV_W<'_>

Bits 10:11 - Controls When the Counter Counts

pub fn auxcntev(&mut self) -> AUXCNTEV_W<'_>

Bits 12:13 - Controls When the Auxiliary Counter Counts

pub fn cntdir(&mut self) -> CNTDIR_W<'_>

Bit 14 - Non-Quadrature Mode Counter Direction Control

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 15 - Edge Select

pub fn tccmode(&mut self) -> TCCMODE_W<'_>

Bits 16:17 - Sets the Mode for Triggered Compare and Clear

pub fn tccpresc(&mut self) -> TCCPRESC_W<'_>

Bits 19:20 - Set the LFA Prescaler for Triggered Compare and Clear

pub fn tcccomp(&mut self) -> TCCCOMP_W<'_>

Bits 22:23 - Triggered Compare and Clear Compare Mode

pub fn prsgateen(&mut self) -> PRSGATEEN_W<'_>

Bit 24 - PRS Gate Enable

pub fn tccprspol(&mut self) -> TCCPRSPOL_W<'_>

Bit 25 - TCC PRS Polarity Select

pub fn tccprssel(&mut self) -> TCCPRSSEL_W<'_>

Bits 26:30 - TCC PRS Channel Select

pub fn topbhfsel(&mut self) -> TOPBHFSEL_W<'_>

Bit 31 - TOPB High Frequency Value Select

impl W<u32, Reg<u32, _CMD>>

pub fn lcntim(&mut self) -> LCNTIM_W<'_>

Bit 0 - Load CNT Immediately

pub fn ltopbim(&mut self) -> LTOPBIM_W<'_>

Bit 1 - Load TOPB Immediately

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:15 - Counter Top Buffer

impl W<u32, Reg<u32, _IFS>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - Set UF Interrupt Flag

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - Set OF Interrupt Flag

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - Set DIRCNG Interrupt Flag

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - Set AUXOF Interrupt Flag

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - Set TCC Interrupt Flag

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - Set OQSTERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - Clear UF Interrupt Flag

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - Clear OF Interrupt Flag

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - Clear DIRCNG Interrupt Flag

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - Clear AUXOF Interrupt Flag

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - Clear TCC Interrupt Flag

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - Clear OQSTERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - UF Interrupt Enable

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - OF Interrupt Enable

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - DIRCNG Interrupt Enable

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - AUXOF Interrupt Enable

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - TCC Interrupt Enable

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - OQSTERR Interrupt Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn s0inloc(&mut self) -> S0INLOC_W<'_>

Bits 0:5 - I/O Location

pub fn s1inloc(&mut self) -> S1INLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _FREEZE>>

pub fn regfreeze(&mut self) -> REGFREEZE_W<'_>

Bit 0 - Register Update Freeze

impl W<u32, Reg<u32, _INPUT>>

pub fn s0prssel(&mut self) -> S0PRSSEL_W<'_>

Bits 0:4 - S0IN PRS Channel Select

pub fn s0prsen(&mut self) -> S0PRSEN_W<'_>

Bit 5 - S0IN PRS Enable

pub fn s1prssel(&mut self) -> S1PRSSEL_W<'_>

Bits 6:10 - S1IN PRS Channel Select

pub fn s1prsen(&mut self) -> S1PRSEN_W<'_>

Bit 11 - S1IN PRS Enable

impl W<u32, Reg<u32, _OVSCFG>>

pub fn filtlen(&mut self) -> FILTLEN_W<'_>

Bits 0:7 - Configure Filter Length for Inputs S0IN and S1IN

pub fn flutterrm(&mut self) -> FLUTTERRM_W<'_>

Bit 12 - Flutter Remove

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:2 - Mode Select

pub fn filt(&mut self) -> FILT_W<'_>

Bit 3 - Enable Digital Pulse Width Filter

pub fn rsten(&mut self) -> RSTEN_W<'_>

Bit 4 - Enable PCNT Clock Domain Reset

pub fn cntrsten(&mut self) -> CNTRSTEN_W<'_>

Bit 5 - Enable CNT Reset

pub fn auxcntrsten(&mut self) -> AUXCNTRSTEN_W<'_>

Bit 6 - Enable AUXCNT Reset

pub fn debughalt(&mut self) -> DEBUGHALT_W<'_>

Bit 7 - Debug Mode Halt Enable

pub fn hyst(&mut self) -> HYST_W<'_>

Bit 8 - Enable Hysteresis

pub fn s1cdir(&mut self) -> S1CDIR_W<'_>

Bit 9 - Count Direction Determined By S1

pub fn cntev(&mut self) -> CNTEV_W<'_>

Bits 10:11 - Controls When the Counter Counts

pub fn auxcntev(&mut self) -> AUXCNTEV_W<'_>

Bits 12:13 - Controls When the Auxiliary Counter Counts

pub fn cntdir(&mut self) -> CNTDIR_W<'_>

Bit 14 - Non-Quadrature Mode Counter Direction Control

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 15 - Edge Select

pub fn tccmode(&mut self) -> TCCMODE_W<'_>

Bits 16:17 - Sets the Mode for Triggered Compare and Clear

pub fn tccpresc(&mut self) -> TCCPRESC_W<'_>

Bits 19:20 - Set the LFA Prescaler for Triggered Compare and Clear

pub fn tcccomp(&mut self) -> TCCCOMP_W<'_>

Bits 22:23 - Triggered Compare and Clear Compare Mode

pub fn prsgateen(&mut self) -> PRSGATEEN_W<'_>

Bit 24 - PRS Gate Enable

pub fn tccprspol(&mut self) -> TCCPRSPOL_W<'_>

Bit 25 - TCC PRS Polarity Select

pub fn tccprssel(&mut self) -> TCCPRSSEL_W<'_>

Bits 26:30 - TCC PRS Channel Select

pub fn topbhfsel(&mut self) -> TOPBHFSEL_W<'_>

Bit 31 - TOPB High Frequency Value Select

impl W<u32, Reg<u32, _CMD>>

pub fn lcntim(&mut self) -> LCNTIM_W<'_>

Bit 0 - Load CNT Immediately

pub fn ltopbim(&mut self) -> LTOPBIM_W<'_>

Bit 1 - Load TOPB Immediately

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:15 - Counter Top Buffer

impl W<u32, Reg<u32, _IFS>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - Set UF Interrupt Flag

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - Set OF Interrupt Flag

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - Set DIRCNG Interrupt Flag

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - Set AUXOF Interrupt Flag

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - Set TCC Interrupt Flag

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - Set OQSTERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - Clear UF Interrupt Flag

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - Clear OF Interrupt Flag

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - Clear DIRCNG Interrupt Flag

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - Clear AUXOF Interrupt Flag

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - Clear TCC Interrupt Flag

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - Clear OQSTERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - UF Interrupt Enable

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - OF Interrupt Enable

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - DIRCNG Interrupt Enable

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - AUXOF Interrupt Enable

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - TCC Interrupt Enable

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - OQSTERR Interrupt Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn s0inloc(&mut self) -> S0INLOC_W<'_>

Bits 0:5 - I/O Location

pub fn s1inloc(&mut self) -> S1INLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _FREEZE>>

pub fn regfreeze(&mut self) -> REGFREEZE_W<'_>

Bit 0 - Register Update Freeze

impl W<u32, Reg<u32, _INPUT>>

pub fn s0prssel(&mut self) -> S0PRSSEL_W<'_>

Bits 0:4 - S0IN PRS Channel Select

pub fn s0prsen(&mut self) -> S0PRSEN_W<'_>

Bit 5 - S0IN PRS Enable

pub fn s1prssel(&mut self) -> S1PRSSEL_W<'_>

Bits 6:10 - S1IN PRS Channel Select

pub fn s1prsen(&mut self) -> S1PRSEN_W<'_>

Bit 11 - S1IN PRS Enable

impl W<u32, Reg<u32, _OVSCFG>>

pub fn filtlen(&mut self) -> FILTLEN_W<'_>

Bits 0:7 - Configure Filter Length for Inputs S0IN and S1IN

pub fn flutterrm(&mut self) -> FLUTTERRM_W<'_>

Bit 12 - Flutter Remove

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:2 - Mode Select

pub fn filt(&mut self) -> FILT_W<'_>

Bit 3 - Enable Digital Pulse Width Filter

pub fn rsten(&mut self) -> RSTEN_W<'_>

Bit 4 - Enable PCNT Clock Domain Reset

pub fn cntrsten(&mut self) -> CNTRSTEN_W<'_>

Bit 5 - Enable CNT Reset

pub fn auxcntrsten(&mut self) -> AUXCNTRSTEN_W<'_>

Bit 6 - Enable AUXCNT Reset

pub fn debughalt(&mut self) -> DEBUGHALT_W<'_>

Bit 7 - Debug Mode Halt Enable

pub fn hyst(&mut self) -> HYST_W<'_>

Bit 8 - Enable Hysteresis

pub fn s1cdir(&mut self) -> S1CDIR_W<'_>

Bit 9 - Count Direction Determined By S1

pub fn cntev(&mut self) -> CNTEV_W<'_>

Bits 10:11 - Controls When the Counter Counts

pub fn auxcntev(&mut self) -> AUXCNTEV_W<'_>

Bits 12:13 - Controls When the Auxiliary Counter Counts

pub fn cntdir(&mut self) -> CNTDIR_W<'_>

Bit 14 - Non-Quadrature Mode Counter Direction Control

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 15 - Edge Select

pub fn tccmode(&mut self) -> TCCMODE_W<'_>

Bits 16:17 - Sets the Mode for Triggered Compare and Clear

pub fn tccpresc(&mut self) -> TCCPRESC_W<'_>

Bits 19:20 - Set the LFA Prescaler for Triggered Compare and Clear

pub fn tcccomp(&mut self) -> TCCCOMP_W<'_>

Bits 22:23 - Triggered Compare and Clear Compare Mode

pub fn prsgateen(&mut self) -> PRSGATEEN_W<'_>

Bit 24 - PRS Gate Enable

pub fn tccprspol(&mut self) -> TCCPRSPOL_W<'_>

Bit 25 - TCC PRS Polarity Select

pub fn tccprssel(&mut self) -> TCCPRSSEL_W<'_>

Bits 26:30 - TCC PRS Channel Select

pub fn topbhfsel(&mut self) -> TOPBHFSEL_W<'_>

Bit 31 - TOPB High Frequency Value Select

impl W<u32, Reg<u32, _CMD>>

pub fn lcntim(&mut self) -> LCNTIM_W<'_>

Bit 0 - Load CNT Immediately

pub fn ltopbim(&mut self) -> LTOPBIM_W<'_>

Bit 1 - Load TOPB Immediately

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:15 - Counter Top Buffer

impl W<u32, Reg<u32, _IFS>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - Set UF Interrupt Flag

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - Set OF Interrupt Flag

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - Set DIRCNG Interrupt Flag

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - Set AUXOF Interrupt Flag

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - Set TCC Interrupt Flag

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - Set OQSTERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - Clear UF Interrupt Flag

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - Clear OF Interrupt Flag

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - Clear DIRCNG Interrupt Flag

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - Clear AUXOF Interrupt Flag

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - Clear TCC Interrupt Flag

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - Clear OQSTERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - UF Interrupt Enable

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - OF Interrupt Enable

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - DIRCNG Interrupt Enable

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - AUXOF Interrupt Enable

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - TCC Interrupt Enable

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - OQSTERR Interrupt Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn s0inloc(&mut self) -> S0INLOC_W<'_>

Bits 0:5 - I/O Location

pub fn s1inloc(&mut self) -> S1INLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _FREEZE>>

pub fn regfreeze(&mut self) -> REGFREEZE_W<'_>

Bit 0 - Register Update Freeze

impl W<u32, Reg<u32, _INPUT>>

pub fn s0prssel(&mut self) -> S0PRSSEL_W<'_>

Bits 0:4 - S0IN PRS Channel Select

pub fn s0prsen(&mut self) -> S0PRSEN_W<'_>

Bit 5 - S0IN PRS Enable

pub fn s1prssel(&mut self) -> S1PRSSEL_W<'_>

Bits 6:10 - S1IN PRS Channel Select

pub fn s1prsen(&mut self) -> S1PRSEN_W<'_>

Bit 11 - S1IN PRS Enable

impl W<u32, Reg<u32, _OVSCFG>>

pub fn filtlen(&mut self) -> FILTLEN_W<'_>

Bits 0:7 - Configure Filter Length for Inputs S0IN and S1IN

pub fn flutterrm(&mut self) -> FLUTTERRM_W<'_>

Bit 12 - Flutter Remove

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - I2C Enable

pub fn slave(&mut self) -> SLAVE_W<'_>

Bit 1 - Addressable as Slave

pub fn autoack(&mut self) -> AUTOACK_W<'_>

Bit 2 - Automatic Acknowledge

pub fn autose(&mut self) -> AUTOSE_W<'_>

Bit 3 - Automatic STOP When Empty

pub fn autosn(&mut self) -> AUTOSN_W<'_>

Bit 4 - Automatic STOP on NACK

pub fn arbdis(&mut self) -> ARBDIS_W<'_>

Bit 5 - Arbitration Disable

pub fn gcamen(&mut self) -> GCAMEN_W<'_>

Bit 6 - General Call Address Match Enable

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 7 - TX Buffer Interrupt Level

pub fn clhr(&mut self) -> CLHR_W<'_>

Bits 8:9 - Clock Low High Ratio

pub fn bito(&mut self) -> BITO_W<'_>

Bits 12:13 - Bus Idle Timeout

pub fn gibito(&mut self) -> GIBITO_W<'_>

Bit 15 - Go Idle on Bus Idle Timeout

pub fn clto(&mut self) -> CLTO_W<'_>

Bits 16:18 - Clock Low Timeout

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Send Start Condition

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Send Stop Condition

pub fn ack(&mut self) -> ACK_W<'_>

Bit 2 - Send ACK

pub fn nack(&mut self) -> NACK_W<'_>

Bit 3 - Send NACK

pub fn cont(&mut self) -> CONT_W<'_>

Bit 4 - Continue Transmission

pub fn abort(&mut self) -> ABORT_W<'_>

Bit 5 - Abort Transmission

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 6 - Clear TX

pub fn clearpc(&mut self) -> CLEARPC_W<'_>

Bit 7 - Clear Pending Commands

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 0:8 - Clock Divider

impl W<u32, Reg<u32, _SADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 1:7 - Slave Address

impl W<u32, Reg<u32, _SADDRMASK>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 1:7 - Slave Address Mask

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Set START Interrupt Flag

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - Set RSTART Interrupt Flag

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - Set ADDR Interrupt Flag

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - Set TXC Interrupt Flag

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - Set ACK Interrupt Flag

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - Set NACK Interrupt Flag

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - Set MSTOP Interrupt Flag

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - Set ARBLOST Interrupt Flag

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - Set BUSERR Interrupt Flag

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - Set BUSHOLD Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - Set TXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - Set RXUF Interrupt Flag

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - Set BITO Interrupt Flag

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - Set CLTO Interrupt Flag

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - Set SSTOP Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - Set RXFULL Interrupt Flag

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - Set CLERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Clear START Interrupt Flag

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - Clear RSTART Interrupt Flag

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - Clear ADDR Interrupt Flag

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - Clear TXC Interrupt Flag

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - Clear ACK Interrupt Flag

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - Clear NACK Interrupt Flag

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - Clear MSTOP Interrupt Flag

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - Clear ARBLOST Interrupt Flag

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - Clear BUSERR Interrupt Flag

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - Clear BUSHOLD Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - Clear TXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - Clear RXUF Interrupt Flag

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - Clear BITO Interrupt Flag

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - Clear CLTO Interrupt Flag

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - Clear SSTOP Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - Clear RXFULL Interrupt Flag

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - Clear CLERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - START Interrupt Enable

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - RSTART Interrupt Enable

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - ADDR Interrupt Enable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 4 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 5 - RXDATAV Interrupt Enable

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - ACK Interrupt Enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - NACK Interrupt Enable

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - MSTOP Interrupt Enable

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - ARBLOST Interrupt Enable

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - BUSERR Interrupt Enable

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - BUSHOLD Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - TXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - RXUF Interrupt Enable

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - BITO Interrupt Enable

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - CLTO Interrupt Enable

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - SSTOP Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - RXFULL Interrupt Enable

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - CLERR Interrupt Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn sdapen(&mut self) -> SDAPEN_W<'_>

Bit 0 - SDA Pin Enable

pub fn sclpen(&mut self) -> SCLPEN_W<'_>

Bit 1 - SCL Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn sdaloc(&mut self) -> SDALOC_W<'_>

Bits 0:5 - I/O Location

pub fn sclloc(&mut self) -> SCLLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - I2C Enable

pub fn slave(&mut self) -> SLAVE_W<'_>

Bit 1 - Addressable as Slave

pub fn autoack(&mut self) -> AUTOACK_W<'_>

Bit 2 - Automatic Acknowledge

pub fn autose(&mut self) -> AUTOSE_W<'_>

Bit 3 - Automatic STOP When Empty

pub fn autosn(&mut self) -> AUTOSN_W<'_>

Bit 4 - Automatic STOP on NACK

pub fn arbdis(&mut self) -> ARBDIS_W<'_>

Bit 5 - Arbitration Disable

pub fn gcamen(&mut self) -> GCAMEN_W<'_>

Bit 6 - General Call Address Match Enable

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 7 - TX Buffer Interrupt Level

pub fn clhr(&mut self) -> CLHR_W<'_>

Bits 8:9 - Clock Low High Ratio

pub fn bito(&mut self) -> BITO_W<'_>

Bits 12:13 - Bus Idle Timeout

pub fn gibito(&mut self) -> GIBITO_W<'_>

Bit 15 - Go Idle on Bus Idle Timeout

pub fn clto(&mut self) -> CLTO_W<'_>

Bits 16:18 - Clock Low Timeout

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Send Start Condition

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Send Stop Condition

pub fn ack(&mut self) -> ACK_W<'_>

Bit 2 - Send ACK

pub fn nack(&mut self) -> NACK_W<'_>

Bit 3 - Send NACK

pub fn cont(&mut self) -> CONT_W<'_>

Bit 4 - Continue Transmission

pub fn abort(&mut self) -> ABORT_W<'_>

Bit 5 - Abort Transmission

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 6 - Clear TX

pub fn clearpc(&mut self) -> CLEARPC_W<'_>

Bit 7 - Clear Pending Commands

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 0:8 - Clock Divider

impl W<u32, Reg<u32, _SADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 1:7 - Slave Address

impl W<u32, Reg<u32, _SADDRMASK>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 1:7 - Slave Address Mask

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Set START Interrupt Flag

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - Set RSTART Interrupt Flag

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - Set ADDR Interrupt Flag

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - Set TXC Interrupt Flag

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - Set ACK Interrupt Flag

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - Set NACK Interrupt Flag

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - Set MSTOP Interrupt Flag

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - Set ARBLOST Interrupt Flag

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - Set BUSERR Interrupt Flag

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - Set BUSHOLD Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - Set TXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - Set RXUF Interrupt Flag

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - Set BITO Interrupt Flag

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - Set CLTO Interrupt Flag

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - Set SSTOP Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - Set RXFULL Interrupt Flag

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - Set CLERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Clear START Interrupt Flag

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - Clear RSTART Interrupt Flag

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - Clear ADDR Interrupt Flag

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - Clear TXC Interrupt Flag

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - Clear ACK Interrupt Flag

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - Clear NACK Interrupt Flag

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - Clear MSTOP Interrupt Flag

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - Clear ARBLOST Interrupt Flag

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - Clear BUSERR Interrupt Flag

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - Clear BUSHOLD Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - Clear TXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - Clear RXUF Interrupt Flag

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - Clear BITO Interrupt Flag

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - Clear CLTO Interrupt Flag

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - Clear SSTOP Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - Clear RXFULL Interrupt Flag

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - Clear CLERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - START Interrupt Enable

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - RSTART Interrupt Enable

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - ADDR Interrupt Enable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 4 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 5 - RXDATAV Interrupt Enable

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - ACK Interrupt Enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - NACK Interrupt Enable

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - MSTOP Interrupt Enable

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - ARBLOST Interrupt Enable

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - BUSERR Interrupt Enable

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - BUSHOLD Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - TXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - RXUF Interrupt Enable

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - BITO Interrupt Enable

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - CLTO Interrupt Enable

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - SSTOP Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - RXFULL Interrupt Enable

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - CLERR Interrupt Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn sdapen(&mut self) -> SDAPEN_W<'_>

Bit 0 - SDA Pin Enable

pub fn sclpen(&mut self) -> SCLPEN_W<'_>

Bit 1 - SCL Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn sdaloc(&mut self) -> SDALOC_W<'_>

Bits 0:5 - I/O Location

pub fn sclloc(&mut self) -> SCLLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - I2C Enable

pub fn slave(&mut self) -> SLAVE_W<'_>

Bit 1 - Addressable as Slave

pub fn autoack(&mut self) -> AUTOACK_W<'_>

Bit 2 - Automatic Acknowledge

pub fn autose(&mut self) -> AUTOSE_W<'_>

Bit 3 - Automatic STOP When Empty

pub fn autosn(&mut self) -> AUTOSN_W<'_>

Bit 4 - Automatic STOP on NACK

pub fn arbdis(&mut self) -> ARBDIS_W<'_>

Bit 5 - Arbitration Disable

pub fn gcamen(&mut self) -> GCAMEN_W<'_>

Bit 6 - General Call Address Match Enable

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 7 - TX Buffer Interrupt Level

pub fn clhr(&mut self) -> CLHR_W<'_>

Bits 8:9 - Clock Low High Ratio

pub fn bito(&mut self) -> BITO_W<'_>

Bits 12:13 - Bus Idle Timeout

pub fn gibito(&mut self) -> GIBITO_W<'_>

Bit 15 - Go Idle on Bus Idle Timeout

pub fn clto(&mut self) -> CLTO_W<'_>

Bits 16:18 - Clock Low Timeout

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Send Start Condition

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Send Stop Condition

pub fn ack(&mut self) -> ACK_W<'_>

Bit 2 - Send ACK

pub fn nack(&mut self) -> NACK_W<'_>

Bit 3 - Send NACK

pub fn cont(&mut self) -> CONT_W<'_>

Bit 4 - Continue Transmission

pub fn abort(&mut self) -> ABORT_W<'_>

Bit 5 - Abort Transmission

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 6 - Clear TX

pub fn clearpc(&mut self) -> CLEARPC_W<'_>

Bit 7 - Clear Pending Commands

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 0:8 - Clock Divider

impl W<u32, Reg<u32, _SADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 1:7 - Slave Address

impl W<u32, Reg<u32, _SADDRMASK>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 1:7 - Slave Address Mask

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Set START Interrupt Flag

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - Set RSTART Interrupt Flag

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - Set ADDR Interrupt Flag

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - Set TXC Interrupt Flag

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - Set ACK Interrupt Flag

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - Set NACK Interrupt Flag

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - Set MSTOP Interrupt Flag

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - Set ARBLOST Interrupt Flag

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - Set BUSERR Interrupt Flag

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - Set BUSHOLD Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - Set TXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - Set RXUF Interrupt Flag

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - Set BITO Interrupt Flag

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - Set CLTO Interrupt Flag

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - Set SSTOP Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - Set RXFULL Interrupt Flag

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - Set CLERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Clear START Interrupt Flag

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - Clear RSTART Interrupt Flag

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - Clear ADDR Interrupt Flag

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - Clear TXC Interrupt Flag

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - Clear ACK Interrupt Flag

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - Clear NACK Interrupt Flag

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - Clear MSTOP Interrupt Flag

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - Clear ARBLOST Interrupt Flag

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - Clear BUSERR Interrupt Flag

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - Clear BUSHOLD Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - Clear TXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - Clear RXUF Interrupt Flag

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - Clear BITO Interrupt Flag

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - Clear CLTO Interrupt Flag

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - Clear SSTOP Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - Clear RXFULL Interrupt Flag

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - Clear CLERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - START Interrupt Enable

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - RSTART Interrupt Enable

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - ADDR Interrupt Enable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 4 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 5 - RXDATAV Interrupt Enable

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - ACK Interrupt Enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - NACK Interrupt Enable

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - MSTOP Interrupt Enable

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - ARBLOST Interrupt Enable

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - BUSERR Interrupt Enable

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - BUSHOLD Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - TXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - RXUF Interrupt Enable

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - BITO Interrupt Enable

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - CLTO Interrupt Enable

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - SSTOP Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - RXFULL Interrupt Enable

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - CLERR Interrupt Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn sdapen(&mut self) -> SDAPEN_W<'_>

Bit 0 - SDA Pin Enable

pub fn sclpen(&mut self) -> SCLPEN_W<'_>

Bit 1 - SCL Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn sdaloc(&mut self) -> SDALOC_W<'_>

Bits 0:5 - I/O Location

pub fn sclloc(&mut self) -> SCLLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn warmupmode(&mut self) -> WARMUPMODE_W<'_>

Bits 0:1 - Warm-up Mode

pub fn singledmawu(&mut self) -> SINGLEDMAWU_W<'_>

Bit 2 - SINGLEFIFO DMA Wakeup

pub fn scandmawu(&mut self) -> SCANDMAWU_W<'_>

Bit 3 - SCANFIFO DMA Wakeup

pub fn tailgate(&mut self) -> TAILGATE_W<'_>

Bit 4 - Conversion Tailgating

pub fn asyncclken(&mut self) -> ASYNCCLKEN_W<'_>

Bit 6 - Selects ASYNC CLK Enable Mode When ADCCLKMODE=1

pub fn adcclkmode(&mut self) -> ADCCLKMODE_W<'_>

Bit 7 - ADC Clock Mode

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:14 - Prescalar Setting for ADC Sample and Conversion Clock

pub fn timebase(&mut self) -> TIMEBASE_W<'_>

Bits 16:22 - 1us Time Base

pub fn ovsrsel(&mut self) -> OVSRSEL_W<'_>

Bits 24:27 - Oversample Rate Select

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 28 - Debug Mode Halt Enable

pub fn chconmode(&mut self) -> CHCONMODE_W<'_>

Bit 29 - Channel Connect

pub fn chconrefwarmidle(&mut self) -> CHCONREFWARMIDLE_W<'_>

Bits 30:31 - Channel Connect and Reference Warm Sel When ADC is IDLE

impl W<u32, Reg<u32, _CMD>>

pub fn singlestart(&mut self) -> SINGLESTART_W<'_>

Bit 0 - Single Channel Conversion Start

pub fn singlestop(&mut self) -> SINGLESTOP_W<'_>

Bit 1 - Single Channel Conversion Stop

pub fn scanstart(&mut self) -> SCANSTART_W<'_>

Bit 2 - Scan Sequence Start

pub fn scanstop(&mut self) -> SCANSTOP_W<'_>

Bit 3 - Scan Sequence Stop

impl W<u32, Reg<u32, _SINGLECTRL>>

pub fn rep(&mut self) -> REP_W<'_>

Bit 0 - Single Channel Repetitive Mode

pub fn diff(&mut self) -> DIFF_W<'_>

Bit 1 - Single Channel Differential Mode

pub fn adj(&mut self) -> ADJ_W<'_>

Bit 2 - Single Channel Result Adjustment

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - Single Channel Resolution Select

pub fn ref_(&mut self) -> REF_W<'_>

Bits 5:7 - Single Channel Reference Selection

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 8:15 - Single Channel Positive Input Selection

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 16:23 - Single Channel Negative Input Selection

pub fn at(&mut self) -> AT_W<'_>

Bits 24:27 - Single Channel Acquisition Time

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 29 - Single Channel PRS Trigger Enable

pub fn cmpen(&mut self) -> CMPEN_W<'_>

Bit 31 - Compare Logic Enable for Single Channel

impl W<u32, Reg<u32, _SINGLECTRLX>>

pub fn vrefsel(&mut self) -> VREFSEL_W<'_>

Bits 0:2 - Single Channel Reference Selection

pub fn vrefattfix(&mut self) -> VREFATTFIX_W<'_>

Bit 3 - Enable Fixed Scaling on VREF

pub fn vrefatt(&mut self) -> VREFATT_W<'_>

Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5

pub fn vinatt(&mut self) -> VINATT_W<'_>

Bits 8:11 - Code for VIN Attenuation Factor

pub fn dvl(&mut self) -> DVL_W<'_>

Bits 12:13 - Single Channel DV Level Select

pub fn fifoofact(&mut self) -> FIFOOFACT_W<'_>

Bit 14 - Single Channel FIFO Overflow Action

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 16 - Single Channel PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 17:21 - Single Channel PRS Trigger Select

pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W<'_>

Bits 22:26 - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set

pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W<'_>

Bit 27 - Enable Delaying Next Conversion Start

pub fn repdelay(&mut self) -> REPDELAY_W<'_>

Bits 29:31 - REPDELAY Select for SINGLE REP Mode

impl W<u32, Reg<u32, _SCANCTRL>>

pub fn rep(&mut self) -> REP_W<'_>

Bit 0 - Scan Sequence Repetitive Mode

pub fn diff(&mut self) -> DIFF_W<'_>

Bit 1 - Scan Sequence Differential Mode

pub fn adj(&mut self) -> ADJ_W<'_>

Bit 2 - Scan Sequence Result Adjustment

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - Scan Sequence Resolution Select

pub fn ref_(&mut self) -> REF_W<'_>

Bits 5:7 - Scan Sequence Reference Selection

pub fn at(&mut self) -> AT_W<'_>

Bits 24:27 - Scan Acquisition Time

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 29 - Scan Sequence PRS Trigger Enable

pub fn cmpen(&mut self) -> CMPEN_W<'_>

Bit 31 - Compare Logic Enable for Scan

impl W<u32, Reg<u32, _SCANCTRLX>>

pub fn vrefsel(&mut self) -> VREFSEL_W<'_>

Bits 0:2 - Scan Channel Reference Selection

pub fn vrefattfix(&mut self) -> VREFATTFIX_W<'_>

Bit 3 - Enable Fixed Scaling on VREF

pub fn vrefatt(&mut self) -> VREFATT_W<'_>

Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5

pub fn vinatt(&mut self) -> VINATT_W<'_>

Bits 8:11 - Code for VIN Attenuation Factor

pub fn dvl(&mut self) -> DVL_W<'_>

Bits 12:13 - Scan DV Level Select

pub fn fifoofact(&mut self) -> FIFOOFACT_W<'_>

Bit 14 - Scan FIFO Overflow Action

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 16 - Scan PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 17:21 - Scan Sequence PRS Trigger Select

pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W<'_>

Bits 22:26 - Delay Next Conversion Start If CONVSTARTDELAYEN is Set

pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W<'_>

Bit 27 - Enable Delaying Next Conversion Start

pub fn repdelay(&mut self) -> REPDELAY_W<'_>

Bits 29:31 - REPDELAY Select for SCAN REP Mode

impl W<u32, Reg<u32, _SCANMASK>>

pub fn scaninputen(&mut self) -> SCANINPUTEN_W<'_>

Bits 0:31 - Scan Sequence Input Mask

impl W<u32, Reg<u32, _SCANINPUTSEL>>

pub fn input0to7sel(&mut self) -> INPUT0TO7SEL_W<'_>

Bits 0:4 - Inputs Chosen for ADCn_INPUT7-ADCn_INPUT0 as Referred in SCANMASK

pub fn input8to15sel(&mut self) -> INPUT8TO15SEL_W<'_>

Bits 8:12 - Inputs Chosen for ADCn_INPUT8-ADCn_INPUT15 as Referred in SCANMASK

pub fn input16to23sel(&mut self) -> INPUT16TO23SEL_W<'_>

Bits 16:20 - Inputs Chosen for ADCn_INPUT16-ADCn_INPUT23 as Referred in SCANMASK

pub fn input24to31sel(&mut self) -> INPUT24TO31SEL_W<'_>

Bits 24:28 - Inputs Chosen for ADCn_INPUT24-ADCn_INPUT31 as Referred in SCANMASK

impl W<u32, Reg<u32, _SCANNEGSEL>>

pub fn input0negsel(&mut self) -> INPUT0NEGSEL_W<'_>

Bits 0:1 - Negative Input Select Register for ADCn_INPUT0 in Differential Scan Mode

pub fn input2negsel(&mut self) -> INPUT2NEGSEL_W<'_>

Bits 2:3 - Negative Input Select Register for ADCn_INPUT2 in Differential Scan Mode

pub fn input4negsel(&mut self) -> INPUT4NEGSEL_W<'_>

Bits 4:5 - Negative Input Select Register for ADCn_INPUT4 in Differential Scan Mode

pub fn input6negsel(&mut self) -> INPUT6NEGSEL_W<'_>

Bits 6:7 - Negative Input Select Register for ADCn_INPUT1 in Differential Scan Mode

pub fn input9negsel(&mut self) -> INPUT9NEGSEL_W<'_>

Bits 8:9 - Negative Input Select Register for ADCn_INPUT9 in Differential Scan Mode

pub fn input11negsel(&mut self) -> INPUT11NEGSEL_W<'_>

Bits 10:11 - Negative Input Select Register for ADCn_INPUT11 in Differential Scan Mode

pub fn input13negsel(&mut self) -> INPUT13NEGSEL_W<'_>

Bits 12:13 - Negative Input Select Register for ADCn_INPUT13 in Differential Scan Mode

pub fn input15negsel(&mut self) -> INPUT15NEGSEL_W<'_>

Bits 14:15 - Negative Input Select Register for ADCn_INPUT15 in Differential Scan Mode

impl W<u32, Reg<u32, _CMPTHR>>

pub fn adlt(&mut self) -> ADLT_W<'_>

Bits 0:15 - Less Than Compare Threshold

pub fn adgt(&mut self) -> ADGT_W<'_>

Bits 16:31 - Greater Than Compare Threshold

impl W<u32, Reg<u32, _BIASPROG>>

pub fn adcbiasprog(&mut self) -> ADCBIASPROG_W<'_>

Bits 0:3 - Bias Programming Value of Analog ADC Block

pub fn vfaultclr(&mut self) -> VFAULTCLR_W<'_>

Bit 12 - Clear VREFOF Flag

pub fn gpbiasacc(&mut self) -> GPBIASACC_W<'_>

Bit 16 - Accuracy Setting for the System Bias During ADC Operation

impl W<u32, Reg<u32, _CAL>>

pub fn singleoffset(&mut self) -> SINGLEOFFSET_W<'_>

Bits 0:3 - Single Mode Offset Calibration Value for Differential or Positive Single-ended Mode

pub fn singleoffsetinv(&mut self) -> SINGLEOFFSETINV_W<'_>

Bits 4:7 - Single Mode Offset Calibration Value for Negative Single-ended Mode

pub fn singlegain(&mut self) -> SINGLEGAIN_W<'_>

Bits 8:14 - Single Mode Gain Calibration Value

pub fn offsetinvmode(&mut self) -> OFFSETINVMODE_W<'_>

Bit 15 - Negative Single-ended Offset Calibration is Enabled

pub fn scanoffset(&mut self) -> SCANOFFSET_W<'_>

Bits 16:19 - Scan Mode Offset Calibration Value for Differential or Positive Single-ended Mode

pub fn scanoffsetinv(&mut self) -> SCANOFFSETINV_W<'_>

Bits 20:23 - Scan Mode Offset Calibration Value for Negative Single-ended Mode

pub fn scangain(&mut self) -> SCANGAIN_W<'_>

Bits 24:30 - Scan Mode Gain Calibration Value

pub fn calen(&mut self) -> CALEN_W<'_>

Bit 31 - Calibration Mode is Enabled

impl W<u32, Reg<u32, _IFS>>

pub fn singleof(&mut self) -> SINGLEOF_W<'_>

Bit 8 - Set SINGLEOF Interrupt Flag

pub fn scanof(&mut self) -> SCANOF_W<'_>

Bit 9 - Set SCANOF Interrupt Flag

pub fn singleuf(&mut self) -> SINGLEUF_W<'_>

Bit 10 - Set SINGLEUF Interrupt Flag

pub fn scanuf(&mut self) -> SCANUF_W<'_>

Bit 11 - Set SCANUF Interrupt Flag

pub fn singlecmp(&mut self) -> SINGLECMP_W<'_>

Bit 16 - Set SINGLECMP Interrupt Flag

pub fn scancmp(&mut self) -> SCANCMP_W<'_>

Bit 17 - Set SCANCMP Interrupt Flag

pub fn vrefov(&mut self) -> VREFOV_W<'_>

Bit 24 - Set VREFOV Interrupt Flag

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 25 - Set PROGERR Interrupt Flag

pub fn scanextpend(&mut self) -> SCANEXTPEND_W<'_>

Bit 26 - Set SCANEXTPEND Interrupt Flag

pub fn scanpend(&mut self) -> SCANPEND_W<'_>

Bit 27 - Set SCANPEND Interrupt Flag

pub fn prstimederr(&mut self) -> PRSTIMEDERR_W<'_>

Bit 28 - Set PRSTIMEDERR Interrupt Flag

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 29 - Set EM23ERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn singleof(&mut self) -> SINGLEOF_W<'_>

Bit 8 - Clear SINGLEOF Interrupt Flag

pub fn scanof(&mut self) -> SCANOF_W<'_>

Bit 9 - Clear SCANOF Interrupt Flag

pub fn singleuf(&mut self) -> SINGLEUF_W<'_>

Bit 10 - Clear SINGLEUF Interrupt Flag

pub fn scanuf(&mut self) -> SCANUF_W<'_>

Bit 11 - Clear SCANUF Interrupt Flag

pub fn singlecmp(&mut self) -> SINGLECMP_W<'_>

Bit 16 - Clear SINGLECMP Interrupt Flag

pub fn scancmp(&mut self) -> SCANCMP_W<'_>

Bit 17 - Clear SCANCMP Interrupt Flag

pub fn vrefov(&mut self) -> VREFOV_W<'_>

Bit 24 - Clear VREFOV Interrupt Flag

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 25 - Clear PROGERR Interrupt Flag

pub fn scanextpend(&mut self) -> SCANEXTPEND_W<'_>

Bit 26 - Clear SCANEXTPEND Interrupt Flag

pub fn scanpend(&mut self) -> SCANPEND_W<'_>

Bit 27 - Clear SCANPEND Interrupt Flag

pub fn prstimederr(&mut self) -> PRSTIMEDERR_W<'_>

Bit 28 - Clear PRSTIMEDERR Interrupt Flag

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 29 - Clear EM23ERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn single(&mut self) -> SINGLE_W<'_>

Bit 0 - SINGLE Interrupt Enable

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 1 - SCAN Interrupt Enable

pub fn singleof(&mut self) -> SINGLEOF_W<'_>

Bit 8 - SINGLEOF Interrupt Enable

pub fn scanof(&mut self) -> SCANOF_W<'_>

Bit 9 - SCANOF Interrupt Enable

pub fn singleuf(&mut self) -> SINGLEUF_W<'_>

Bit 10 - SINGLEUF Interrupt Enable

pub fn scanuf(&mut self) -> SCANUF_W<'_>

Bit 11 - SCANUF Interrupt Enable

pub fn singlecmp(&mut self) -> SINGLECMP_W<'_>

Bit 16 - SINGLECMP Interrupt Enable

pub fn scancmp(&mut self) -> SCANCMP_W<'_>

Bit 17 - SCANCMP Interrupt Enable

pub fn vrefov(&mut self) -> VREFOV_W<'_>

Bit 24 - VREFOV Interrupt Enable

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 25 - PROGERR Interrupt Enable

pub fn scanextpend(&mut self) -> SCANEXTPEND_W<'_>

Bit 26 - SCANEXTPEND Interrupt Enable

pub fn scanpend(&mut self) -> SCANPEND_W<'_>

Bit 27 - SCANPEND Interrupt Enable

pub fn prstimederr(&mut self) -> PRSTIMEDERR_W<'_>

Bit 28 - PRSTIMEDERR Interrupt Enable

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 29 - EM23ERR Interrupt Enable

impl W<u32, Reg<u32, _SINGLEFIFOCLEAR>>

pub fn singlefifoclear(&mut self) -> SINGLEFIFOCLEAR_W<'_>

Bit 0 - Clear Single FIFO Content

impl W<u32, Reg<u32, _SCANFIFOCLEAR>>

pub fn scanfifoclear(&mut self) -> SCANFIFOCLEAR_W<'_>

Bit 0 - Clear Scan FIFO Content

impl W<u32, Reg<u32, _APORTMASTERDIS>>

pub fn aport1xmasterdis(&mut self) -> APORT1XMASTERDIS_W<'_>

Bit 2 - APORT1X Master Disable

pub fn aport1ymasterdis(&mut self) -> APORT1YMASTERDIS_W<'_>

Bit 3 - APORT1Y Master Disable

pub fn aport2xmasterdis(&mut self) -> APORT2XMASTERDIS_W<'_>

Bit 4 - APORT2X Master Disable

pub fn aport2ymasterdis(&mut self) -> APORT2YMASTERDIS_W<'_>

Bit 5 - APORT2Y Master Disable

pub fn aport3xmasterdis(&mut self) -> APORT3XMASTERDIS_W<'_>

Bit 6 - APORT3X Master Disable

pub fn aport3ymasterdis(&mut self) -> APORT3YMASTERDIS_W<'_>

Bit 7 - APORT3Y Master Disable

pub fn aport4xmasterdis(&mut self) -> APORT4XMASTERDIS_W<'_>

Bit 8 - APORT4X Master Disable

pub fn aport4ymasterdis(&mut self) -> APORT4YMASTERDIS_W<'_>

Bit 9 - APORT4Y Master Disable

impl W<u32, Reg<u32, _CTRL>>

pub fn warmupmode(&mut self) -> WARMUPMODE_W<'_>

Bits 0:1 - Warm-up Mode

pub fn singledmawu(&mut self) -> SINGLEDMAWU_W<'_>

Bit 2 - SINGLEFIFO DMA Wakeup

pub fn scandmawu(&mut self) -> SCANDMAWU_W<'_>

Bit 3 - SCANFIFO DMA Wakeup

pub fn tailgate(&mut self) -> TAILGATE_W<'_>

Bit 4 - Conversion Tailgating

pub fn asyncclken(&mut self) -> ASYNCCLKEN_W<'_>

Bit 6 - Selects ASYNC CLK Enable Mode When ADCCLKMODE=1

pub fn adcclkmode(&mut self) -> ADCCLKMODE_W<'_>

Bit 7 - ADC Clock Mode

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:14 - Prescalar Setting for ADC Sample and Conversion Clock

pub fn timebase(&mut self) -> TIMEBASE_W<'_>

Bits 16:22 - 1us Time Base

pub fn ovsrsel(&mut self) -> OVSRSEL_W<'_>

Bits 24:27 - Oversample Rate Select

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 28 - Debug Mode Halt Enable

pub fn chconmode(&mut self) -> CHCONMODE_W<'_>

Bit 29 - Channel Connect

pub fn chconrefwarmidle(&mut self) -> CHCONREFWARMIDLE_W<'_>

Bits 30:31 - Channel Connect and Reference Warm Sel When ADC is IDLE

impl W<u32, Reg<u32, _CMD>>

pub fn singlestart(&mut self) -> SINGLESTART_W<'_>

Bit 0 - Single Channel Conversion Start

pub fn singlestop(&mut self) -> SINGLESTOP_W<'_>

Bit 1 - Single Channel Conversion Stop

pub fn scanstart(&mut self) -> SCANSTART_W<'_>

Bit 2 - Scan Sequence Start

pub fn scanstop(&mut self) -> SCANSTOP_W<'_>

Bit 3 - Scan Sequence Stop

impl W<u32, Reg<u32, _SINGLECTRL>>

pub fn rep(&mut self) -> REP_W<'_>

Bit 0 - Single Channel Repetitive Mode

pub fn diff(&mut self) -> DIFF_W<'_>

Bit 1 - Single Channel Differential Mode

pub fn adj(&mut self) -> ADJ_W<'_>

Bit 2 - Single Channel Result Adjustment

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - Single Channel Resolution Select

pub fn ref_(&mut self) -> REF_W<'_>

Bits 5:7 - Single Channel Reference Selection

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 8:15 - Single Channel Positive Input Selection

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 16:23 - Single Channel Negative Input Selection

pub fn at(&mut self) -> AT_W<'_>

Bits 24:27 - Single Channel Acquisition Time

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 29 - Single Channel PRS Trigger Enable

pub fn cmpen(&mut self) -> CMPEN_W<'_>

Bit 31 - Compare Logic Enable for Single Channel

impl W<u32, Reg<u32, _SINGLECTRLX>>

pub fn vrefsel(&mut self) -> VREFSEL_W<'_>

Bits 0:2 - Single Channel Reference Selection

pub fn vrefattfix(&mut self) -> VREFATTFIX_W<'_>

Bit 3 - Enable Fixed Scaling on VREF

pub fn vrefatt(&mut self) -> VREFATT_W<'_>

Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5

pub fn vinatt(&mut self) -> VINATT_W<'_>

Bits 8:11 - Code for VIN Attenuation Factor

pub fn dvl(&mut self) -> DVL_W<'_>

Bits 12:13 - Single Channel DV Level Select

pub fn fifoofact(&mut self) -> FIFOOFACT_W<'_>

Bit 14 - Single Channel FIFO Overflow Action

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 16 - Single Channel PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 17:21 - Single Channel PRS Trigger Select

pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W<'_>

Bits 22:26 - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set

pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W<'_>

Bit 27 - Enable Delaying Next Conversion Start

pub fn repdelay(&mut self) -> REPDELAY_W<'_>

Bits 29:31 - REPDELAY Select for SINGLE REP Mode

impl W<u32, Reg<u32, _SCANCTRL>>

pub fn rep(&mut self) -> REP_W<'_>

Bit 0 - Scan Sequence Repetitive Mode

pub fn diff(&mut self) -> DIFF_W<'_>

Bit 1 - Scan Sequence Differential Mode

pub fn adj(&mut self) -> ADJ_W<'_>

Bit 2 - Scan Sequence Result Adjustment

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - Scan Sequence Resolution Select

pub fn ref_(&mut self) -> REF_W<'_>

Bits 5:7 - Scan Sequence Reference Selection

pub fn at(&mut self) -> AT_W<'_>

Bits 24:27 - Scan Acquisition Time

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 29 - Scan Sequence PRS Trigger Enable

pub fn cmpen(&mut self) -> CMPEN_W<'_>

Bit 31 - Compare Logic Enable for Scan

impl W<u32, Reg<u32, _SCANCTRLX>>

pub fn vrefsel(&mut self) -> VREFSEL_W<'_>

Bits 0:2 - Scan Channel Reference Selection

pub fn vrefattfix(&mut self) -> VREFATTFIX_W<'_>

Bit 3 - Enable Fixed Scaling on VREF

pub fn vrefatt(&mut self) -> VREFATT_W<'_>

Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5

pub fn vinatt(&mut self) -> VINATT_W<'_>

Bits 8:11 - Code for VIN Attenuation Factor

pub fn dvl(&mut self) -> DVL_W<'_>

Bits 12:13 - Scan DV Level Select

pub fn fifoofact(&mut self) -> FIFOOFACT_W<'_>

Bit 14 - Scan FIFO Overflow Action

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 16 - Scan PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 17:21 - Scan Sequence PRS Trigger Select

pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W<'_>

Bits 22:26 - Delay Next Conversion Start If CONVSTARTDELAYEN is Set

pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W<'_>

Bit 27 - Enable Delaying Next Conversion Start

pub fn repdelay(&mut self) -> REPDELAY_W<'_>

Bits 29:31 - REPDELAY Select for SCAN REP Mode

impl W<u32, Reg<u32, _SCANMASK>>

pub fn scaninputen(&mut self) -> SCANINPUTEN_W<'_>

Bits 0:31 - Scan Sequence Input Mask

impl W<u32, Reg<u32, _SCANINPUTSEL>>

pub fn input0to7sel(&mut self) -> INPUT0TO7SEL_W<'_>

Bits 0:4 - Inputs Chosen for ADCn_INPUT7-ADCn_INPUT0 as Referred in SCANMASK

pub fn input8to15sel(&mut self) -> INPUT8TO15SEL_W<'_>

Bits 8:12 - Inputs Chosen for ADCn_INPUT8-ADCn_INPUT15 as Referred in SCANMASK

pub fn input16to23sel(&mut self) -> INPUT16TO23SEL_W<'_>

Bits 16:20 - Inputs Chosen for ADCn_INPUT16-ADCn_INPUT23 as Referred in SCANMASK

pub fn input24to31sel(&mut self) -> INPUT24TO31SEL_W<'_>

Bits 24:28 - Inputs Chosen for ADCn_INPUT24-ADCn_INPUT31 as Referred in SCANMASK

impl W<u32, Reg<u32, _SCANNEGSEL>>

pub fn input0negsel(&mut self) -> INPUT0NEGSEL_W<'_>

Bits 0:1 - Negative Input Select Register for ADCn_INPUT0 in Differential Scan Mode

pub fn input2negsel(&mut self) -> INPUT2NEGSEL_W<'_>

Bits 2:3 - Negative Input Select Register for ADCn_INPUT2 in Differential Scan Mode

pub fn input4negsel(&mut self) -> INPUT4NEGSEL_W<'_>

Bits 4:5 - Negative Input Select Register for ADCn_INPUT4 in Differential Scan Mode

pub fn input6negsel(&mut self) -> INPUT6NEGSEL_W<'_>

Bits 6:7 - Negative Input Select Register for ADCn_INPUT1 in Differential Scan Mode

pub fn input9negsel(&mut self) -> INPUT9NEGSEL_W<'_>

Bits 8:9 - Negative Input Select Register for ADCn_INPUT9 in Differential Scan Mode

pub fn input11negsel(&mut self) -> INPUT11NEGSEL_W<'_>

Bits 10:11 - Negative Input Select Register for ADCn_INPUT11 in Differential Scan Mode

pub fn input13negsel(&mut self) -> INPUT13NEGSEL_W<'_>

Bits 12:13 - Negative Input Select Register for ADCn_INPUT13 in Differential Scan Mode

pub fn input15negsel(&mut self) -> INPUT15NEGSEL_W<'_>

Bits 14:15 - Negative Input Select Register for ADCn_INPUT15 in Differential Scan Mode

impl W<u32, Reg<u32, _CMPTHR>>

pub fn adlt(&mut self) -> ADLT_W<'_>

Bits 0:15 - Less Than Compare Threshold

pub fn adgt(&mut self) -> ADGT_W<'_>

Bits 16:31 - Greater Than Compare Threshold

impl W<u32, Reg<u32, _BIASPROG>>

pub fn adcbiasprog(&mut self) -> ADCBIASPROG_W<'_>

Bits 0:3 - Bias Programming Value of Analog ADC Block

pub fn vfaultclr(&mut self) -> VFAULTCLR_W<'_>

Bit 12 - Clear VREFOF Flag

pub fn gpbiasacc(&mut self) -> GPBIASACC_W<'_>

Bit 16 - Accuracy Setting for the System Bias During ADC Operation

impl W<u32, Reg<u32, _CAL>>

pub fn singleoffset(&mut self) -> SINGLEOFFSET_W<'_>

Bits 0:3 - Single Mode Offset Calibration Value for Differential or Positive Single-ended Mode

pub fn singleoffsetinv(&mut self) -> SINGLEOFFSETINV_W<'_>

Bits 4:7 - Single Mode Offset Calibration Value for Negative Single-ended Mode

pub fn singlegain(&mut self) -> SINGLEGAIN_W<'_>

Bits 8:14 - Single Mode Gain Calibration Value

pub fn offsetinvmode(&mut self) -> OFFSETINVMODE_W<'_>

Bit 15 - Negative Single-ended Offset Calibration is Enabled

pub fn scanoffset(&mut self) -> SCANOFFSET_W<'_>

Bits 16:19 - Scan Mode Offset Calibration Value for Differential or Positive Single-ended Mode

pub fn scanoffsetinv(&mut self) -> SCANOFFSETINV_W<'_>

Bits 20:23 - Scan Mode Offset Calibration Value for Negative Single-ended Mode

pub fn scangain(&mut self) -> SCANGAIN_W<'_>

Bits 24:30 - Scan Mode Gain Calibration Value

pub fn calen(&mut self) -> CALEN_W<'_>

Bit 31 - Calibration Mode is Enabled

impl W<u32, Reg<u32, _IFS>>

pub fn singleof(&mut self) -> SINGLEOF_W<'_>

Bit 8 - Set SINGLEOF Interrupt Flag

pub fn scanof(&mut self) -> SCANOF_W<'_>

Bit 9 - Set SCANOF Interrupt Flag

pub fn singleuf(&mut self) -> SINGLEUF_W<'_>

Bit 10 - Set SINGLEUF Interrupt Flag

pub fn scanuf(&mut self) -> SCANUF_W<'_>

Bit 11 - Set SCANUF Interrupt Flag

pub fn singlecmp(&mut self) -> SINGLECMP_W<'_>

Bit 16 - Set SINGLECMP Interrupt Flag

pub fn scancmp(&mut self) -> SCANCMP_W<'_>

Bit 17 - Set SCANCMP Interrupt Flag

pub fn vrefov(&mut self) -> VREFOV_W<'_>

Bit 24 - Set VREFOV Interrupt Flag

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 25 - Set PROGERR Interrupt Flag

pub fn scanextpend(&mut self) -> SCANEXTPEND_W<'_>

Bit 26 - Set SCANEXTPEND Interrupt Flag

pub fn scanpend(&mut self) -> SCANPEND_W<'_>

Bit 27 - Set SCANPEND Interrupt Flag

pub fn prstimederr(&mut self) -> PRSTIMEDERR_W<'_>

Bit 28 - Set PRSTIMEDERR Interrupt Flag

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 29 - Set EM23ERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn singleof(&mut self) -> SINGLEOF_W<'_>

Bit 8 - Clear SINGLEOF Interrupt Flag

pub fn scanof(&mut self) -> SCANOF_W<'_>

Bit 9 - Clear SCANOF Interrupt Flag

pub fn singleuf(&mut self) -> SINGLEUF_W<'_>

Bit 10 - Clear SINGLEUF Interrupt Flag

pub fn scanuf(&mut self) -> SCANUF_W<'_>

Bit 11 - Clear SCANUF Interrupt Flag

pub fn singlecmp(&mut self) -> SINGLECMP_W<'_>

Bit 16 - Clear SINGLECMP Interrupt Flag

pub fn scancmp(&mut self) -> SCANCMP_W<'_>

Bit 17 - Clear SCANCMP Interrupt Flag

pub fn vrefov(&mut self) -> VREFOV_W<'_>

Bit 24 - Clear VREFOV Interrupt Flag

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 25 - Clear PROGERR Interrupt Flag

pub fn scanextpend(&mut self) -> SCANEXTPEND_W<'_>

Bit 26 - Clear SCANEXTPEND Interrupt Flag

pub fn scanpend(&mut self) -> SCANPEND_W<'_>

Bit 27 - Clear SCANPEND Interrupt Flag

pub fn prstimederr(&mut self) -> PRSTIMEDERR_W<'_>

Bit 28 - Clear PRSTIMEDERR Interrupt Flag

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 29 - Clear EM23ERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn single(&mut self) -> SINGLE_W<'_>

Bit 0 - SINGLE Interrupt Enable

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 1 - SCAN Interrupt Enable

pub fn singleof(&mut self) -> SINGLEOF_W<'_>

Bit 8 - SINGLEOF Interrupt Enable

pub fn scanof(&mut self) -> SCANOF_W<'_>

Bit 9 - SCANOF Interrupt Enable

pub fn singleuf(&mut self) -> SINGLEUF_W<'_>

Bit 10 - SINGLEUF Interrupt Enable

pub fn scanuf(&mut self) -> SCANUF_W<'_>

Bit 11 - SCANUF Interrupt Enable

pub fn singlecmp(&mut self) -> SINGLECMP_W<'_>

Bit 16 - SINGLECMP Interrupt Enable

pub fn scancmp(&mut self) -> SCANCMP_W<'_>

Bit 17 - SCANCMP Interrupt Enable

pub fn vrefov(&mut self) -> VREFOV_W<'_>

Bit 24 - VREFOV Interrupt Enable

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 25 - PROGERR Interrupt Enable

pub fn scanextpend(&mut self) -> SCANEXTPEND_W<'_>

Bit 26 - SCANEXTPEND Interrupt Enable

pub fn scanpend(&mut self) -> SCANPEND_W<'_>

Bit 27 - SCANPEND Interrupt Enable

pub fn prstimederr(&mut self) -> PRSTIMEDERR_W<'_>

Bit 28 - PRSTIMEDERR Interrupt Enable

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 29 - EM23ERR Interrupt Enable

impl W<u32, Reg<u32, _SINGLEFIFOCLEAR>>

pub fn singlefifoclear(&mut self) -> SINGLEFIFOCLEAR_W<'_>

Bit 0 - Clear Single FIFO Content

impl W<u32, Reg<u32, _SCANFIFOCLEAR>>

pub fn scanfifoclear(&mut self) -> SCANFIFOCLEAR_W<'_>

Bit 0 - Clear Scan FIFO Content

impl W<u32, Reg<u32, _APORTMASTERDIS>>

pub fn aport1xmasterdis(&mut self) -> APORT1XMASTERDIS_W<'_>

Bit 2 - APORT1X Master Disable

pub fn aport1ymasterdis(&mut self) -> APORT1YMASTERDIS_W<'_>

Bit 3 - APORT1Y Master Disable

pub fn aport2xmasterdis(&mut self) -> APORT2XMASTERDIS_W<'_>

Bit 4 - APORT2X Master Disable

pub fn aport2ymasterdis(&mut self) -> APORT2YMASTERDIS_W<'_>

Bit 5 - APORT2Y Master Disable

pub fn aport3xmasterdis(&mut self) -> APORT3XMASTERDIS_W<'_>

Bit 6 - APORT3X Master Disable

pub fn aport3ymasterdis(&mut self) -> APORT3YMASTERDIS_W<'_>

Bit 7 - APORT3Y Master Disable

pub fn aport4xmasterdis(&mut self) -> APORT4XMASTERDIS_W<'_>

Bit 8 - APORT4X Master Disable

pub fn aport4ymasterdis(&mut self) -> APORT4YMASTERDIS_W<'_>

Bit 9 - APORT4Y Master Disable

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Analog Comparator Enable

pub fn inactval(&mut self) -> INACTVAL_W<'_>

Bit 2 - Inactive Value

pub fn gpioinv(&mut self) -> GPIOINV_W<'_>

Bit 3 - Comparator GPIO Output Invert

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 8 - APORT Bus X Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 9 - APORT Bus Y Master Disable

pub fn aportvmasterdis(&mut self) -> APORTVMASTERDIS_W<'_>

Bit 10 - APORT Bus Master Disable for Bus Selected By VASEL

pub fn pwrsel(&mut self) -> PWRSEL_W<'_>

Bits 12:14 - Power Select

pub fn accuracy(&mut self) -> ACCURACY_W<'_>

Bit 15 - ACMP Accuracy Mode

pub fn inputrange(&mut self) -> INPUTRANGE_W<'_>

Bits 18:19 - Input Range

pub fn irise(&mut self) -> IRISE_W<'_>

Bit 20 - Rising Edge Interrupt Sense

pub fn ifall(&mut self) -> IFALL_W<'_>

Bit 21 - Falling Edge Interrupt Sense

pub fn biasprog(&mut self) -> BIASPROG_W<'_>

Bits 24:29 - Bias Configuration

pub fn fullbias(&mut self) -> FULLBIAS_W<'_>

Bit 31 - Full Bias Current

impl W<u32, Reg<u32, _INPUTSEL>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - Positive Input Select

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - Negative Input Select

pub fn vasel(&mut self) -> VASEL_W<'_>

Bits 16:21 - VA Selection

pub fn vbsel(&mut self) -> VBSEL_W<'_>

Bit 22 - VB Selection

pub fn vlpsel(&mut self) -> VLPSEL_W<'_>

Bit 24 - Low-Power Sampled Voltage Selection

pub fn csresen(&mut self) -> CSRESEN_W<'_>

Bit 26 - Capacitive Sense Mode Internal Resistor Enable

pub fn csressel(&mut self) -> CSRESSEL_W<'_>

Bits 28:30 - Capacitive Sense Mode Internal Resistor Select

impl W<u32, Reg<u32, _IFS>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - Set EDGE Interrupt Flag

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - Set WARMUP Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - Set APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - Clear EDGE Interrupt Flag

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - Clear WARMUP Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - Clear APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - EDGE Interrupt Enable

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - WARMUP Interrupt Enable

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - APORTCONFLICT Interrupt Enable

impl W<u32, Reg<u32, _HYSTERESIS0>>

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 0:3 - Hysteresis Select When ACMPOUT=0

pub fn divva(&mut self) -> DIVVA_W<'_>

Bits 16:21 - Divider for VA Voltage When ACMPOUT=0

pub fn divvb(&mut self) -> DIVVB_W<'_>

Bits 24:29 - Divider for VB Voltage When ACMPOUT=0

impl W<u32, Reg<u32, _HYSTERESIS1>>

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 0:3 - Hysteresis Select When ACMPOUT=1

pub fn divva(&mut self) -> DIVVA_W<'_>

Bits 16:21 - Divider for VA Voltage When ACMPOUT=1

pub fn divvb(&mut self) -> DIVVB_W<'_>

Bits 24:29 - Divider for VB Voltage When ACMPOUT=1

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn outpen(&mut self) -> OUTPEN_W<'_>

Bit 0 - ACMP Output Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn outloc(&mut self) -> OUTLOC_W<'_>

Bits 0:5 - I/O Location

impl W<u32, Reg<u32, _EXTIFCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable External Interface

pub fn aportsel(&mut self) -> APORTSEL_W<'_>

Bits 4:7 - APORT Selection for External Interface

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Analog Comparator Enable

pub fn inactval(&mut self) -> INACTVAL_W<'_>

Bit 2 - Inactive Value

pub fn gpioinv(&mut self) -> GPIOINV_W<'_>

Bit 3 - Comparator GPIO Output Invert

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 8 - APORT Bus X Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 9 - APORT Bus Y Master Disable

pub fn aportvmasterdis(&mut self) -> APORTVMASTERDIS_W<'_>

Bit 10 - APORT Bus Master Disable for Bus Selected By VASEL

pub fn pwrsel(&mut self) -> PWRSEL_W<'_>

Bits 12:14 - Power Select

pub fn accuracy(&mut self) -> ACCURACY_W<'_>

Bit 15 - ACMP Accuracy Mode

pub fn inputrange(&mut self) -> INPUTRANGE_W<'_>

Bits 18:19 - Input Range

pub fn irise(&mut self) -> IRISE_W<'_>

Bit 20 - Rising Edge Interrupt Sense

pub fn ifall(&mut self) -> IFALL_W<'_>

Bit 21 - Falling Edge Interrupt Sense

pub fn biasprog(&mut self) -> BIASPROG_W<'_>

Bits 24:29 - Bias Configuration

pub fn fullbias(&mut self) -> FULLBIAS_W<'_>

Bit 31 - Full Bias Current

impl W<u32, Reg<u32, _INPUTSEL>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - Positive Input Select

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - Negative Input Select

pub fn vasel(&mut self) -> VASEL_W<'_>

Bits 16:21 - VA Selection

pub fn vbsel(&mut self) -> VBSEL_W<'_>

Bit 22 - VB Selection

pub fn vlpsel(&mut self) -> VLPSEL_W<'_>

Bit 24 - Low-Power Sampled Voltage Selection

pub fn csresen(&mut self) -> CSRESEN_W<'_>

Bit 26 - Capacitive Sense Mode Internal Resistor Enable

pub fn csressel(&mut self) -> CSRESSEL_W<'_>

Bits 28:30 - Capacitive Sense Mode Internal Resistor Select

impl W<u32, Reg<u32, _IFS>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - Set EDGE Interrupt Flag

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - Set WARMUP Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - Set APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - Clear EDGE Interrupt Flag

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - Clear WARMUP Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - Clear APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - EDGE Interrupt Enable

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - WARMUP Interrupt Enable

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - APORTCONFLICT Interrupt Enable

impl W<u32, Reg<u32, _HYSTERESIS0>>

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 0:3 - Hysteresis Select When ACMPOUT=0

pub fn divva(&mut self) -> DIVVA_W<'_>

Bits 16:21 - Divider for VA Voltage When ACMPOUT=0

pub fn divvb(&mut self) -> DIVVB_W<'_>

Bits 24:29 - Divider for VB Voltage When ACMPOUT=0

impl W<u32, Reg<u32, _HYSTERESIS1>>

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 0:3 - Hysteresis Select When ACMPOUT=1

pub fn divva(&mut self) -> DIVVA_W<'_>

Bits 16:21 - Divider for VA Voltage When ACMPOUT=1

pub fn divvb(&mut self) -> DIVVB_W<'_>

Bits 24:29 - Divider for VB Voltage When ACMPOUT=1

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn outpen(&mut self) -> OUTPEN_W<'_>

Bit 0 - ACMP Output Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn outloc(&mut self) -> OUTLOC_W<'_>

Bits 0:5 - I/O Location

impl W<u32, Reg<u32, _EXTIFCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable External Interface

pub fn aportsel(&mut self) -> APORTSEL_W<'_>

Bits 4:7 - APORT Selection for External Interface

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Analog Comparator Enable

pub fn inactval(&mut self) -> INACTVAL_W<'_>

Bit 2 - Inactive Value

pub fn gpioinv(&mut self) -> GPIOINV_W<'_>

Bit 3 - Comparator GPIO Output Invert

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 8 - APORT Bus X Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 9 - APORT Bus Y Master Disable

pub fn aportvmasterdis(&mut self) -> APORTVMASTERDIS_W<'_>

Bit 10 - APORT Bus Master Disable for Bus Selected By VASEL

pub fn pwrsel(&mut self) -> PWRSEL_W<'_>

Bits 12:14 - Power Select

pub fn accuracy(&mut self) -> ACCURACY_W<'_>

Bit 15 - ACMP Accuracy Mode

pub fn inputrange(&mut self) -> INPUTRANGE_W<'_>

Bits 18:19 - Input Range

pub fn irise(&mut self) -> IRISE_W<'_>

Bit 20 - Rising Edge Interrupt Sense

pub fn ifall(&mut self) -> IFALL_W<'_>

Bit 21 - Falling Edge Interrupt Sense

pub fn biasprog(&mut self) -> BIASPROG_W<'_>

Bits 24:29 - Bias Configuration

pub fn fullbias(&mut self) -> FULLBIAS_W<'_>

Bit 31 - Full Bias Current

impl W<u32, Reg<u32, _INPUTSEL>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - Positive Input Select

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - Negative Input Select

pub fn vasel(&mut self) -> VASEL_W<'_>

Bits 16:21 - VA Selection

pub fn vbsel(&mut self) -> VBSEL_W<'_>

Bit 22 - VB Selection

pub fn vlpsel(&mut self) -> VLPSEL_W<'_>

Bit 24 - Low-Power Sampled Voltage Selection

pub fn csresen(&mut self) -> CSRESEN_W<'_>

Bit 26 - Capacitive Sense Mode Internal Resistor Enable

pub fn csressel(&mut self) -> CSRESSEL_W<'_>

Bits 28:30 - Capacitive Sense Mode Internal Resistor Select

impl W<u32, Reg<u32, _IFS>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - Set EDGE Interrupt Flag

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - Set WARMUP Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - Set APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - Clear EDGE Interrupt Flag

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - Clear WARMUP Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - Clear APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - EDGE Interrupt Enable

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - WARMUP Interrupt Enable

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - APORTCONFLICT Interrupt Enable

impl W<u32, Reg<u32, _HYSTERESIS0>>

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 0:3 - Hysteresis Select When ACMPOUT=0

pub fn divva(&mut self) -> DIVVA_W<'_>

Bits 16:21 - Divider for VA Voltage When ACMPOUT=0

pub fn divvb(&mut self) -> DIVVB_W<'_>

Bits 24:29 - Divider for VB Voltage When ACMPOUT=0

impl W<u32, Reg<u32, _HYSTERESIS1>>

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 0:3 - Hysteresis Select When ACMPOUT=1

pub fn divva(&mut self) -> DIVVA_W<'_>

Bits 16:21 - Divider for VA Voltage When ACMPOUT=1

pub fn divvb(&mut self) -> DIVVB_W<'_>

Bits 24:29 - Divider for VB Voltage When ACMPOUT=1

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn outpen(&mut self) -> OUTPEN_W<'_>

Bit 0 - ACMP Output Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn outloc(&mut self) -> OUTLOC_W<'_>

Bits 0:5 - I/O Location

impl W<u32, Reg<u32, _EXTIFCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable External Interface

pub fn aportsel(&mut self) -> APORTSEL_W<'_>

Bits 4:7 - APORT Selection for External Interface

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Analog Comparator Enable

pub fn inactval(&mut self) -> INACTVAL_W<'_>

Bit 2 - Inactive Value

pub fn gpioinv(&mut self) -> GPIOINV_W<'_>

Bit 3 - Comparator GPIO Output Invert

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 8 - APORT Bus X Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 9 - APORT Bus Y Master Disable

pub fn aportvmasterdis(&mut self) -> APORTVMASTERDIS_W<'_>

Bit 10 - APORT Bus Master Disable for Bus Selected By VASEL

pub fn pwrsel(&mut self) -> PWRSEL_W<'_>

Bits 12:14 - Power Select

pub fn accuracy(&mut self) -> ACCURACY_W<'_>

Bit 15 - ACMP Accuracy Mode

pub fn inputrange(&mut self) -> INPUTRANGE_W<'_>

Bits 18:19 - Input Range

pub fn irise(&mut self) -> IRISE_W<'_>

Bit 20 - Rising Edge Interrupt Sense

pub fn ifall(&mut self) -> IFALL_W<'_>

Bit 21 - Falling Edge Interrupt Sense

pub fn biasprog(&mut self) -> BIASPROG_W<'_>

Bits 24:29 - Bias Configuration

pub fn fullbias(&mut self) -> FULLBIAS_W<'_>

Bit 31 - Full Bias Current

impl W<u32, Reg<u32, _INPUTSEL>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - Positive Input Select

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - Negative Input Select

pub fn vasel(&mut self) -> VASEL_W<'_>

Bits 16:21 - VA Selection

pub fn vbsel(&mut self) -> VBSEL_W<'_>

Bit 22 - VB Selection

pub fn vlpsel(&mut self) -> VLPSEL_W<'_>

Bit 24 - Low-Power Sampled Voltage Selection

pub fn csresen(&mut self) -> CSRESEN_W<'_>

Bit 26 - Capacitive Sense Mode Internal Resistor Enable

pub fn csressel(&mut self) -> CSRESSEL_W<'_>

Bits 28:30 - Capacitive Sense Mode Internal Resistor Select

impl W<u32, Reg<u32, _IFS>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - Set EDGE Interrupt Flag

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - Set WARMUP Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - Set APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - Clear EDGE Interrupt Flag

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - Clear WARMUP Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - Clear APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - EDGE Interrupt Enable

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - WARMUP Interrupt Enable

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - APORTCONFLICT Interrupt Enable

impl W<u32, Reg<u32, _HYSTERESIS0>>

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 0:3 - Hysteresis Select When ACMPOUT=0

pub fn divva(&mut self) -> DIVVA_W<'_>

Bits 16:21 - Divider for VA Voltage When ACMPOUT=0

pub fn divvb(&mut self) -> DIVVB_W<'_>

Bits 24:29 - Divider for VB Voltage When ACMPOUT=0

impl W<u32, Reg<u32, _HYSTERESIS1>>

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 0:3 - Hysteresis Select When ACMPOUT=1

pub fn divva(&mut self) -> DIVVA_W<'_>

Bits 16:21 - Divider for VA Voltage When ACMPOUT=1

pub fn divvb(&mut self) -> DIVVB_W<'_>

Bits 24:29 - Divider for VB Voltage When ACMPOUT=1

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn outpen(&mut self) -> OUTPEN_W<'_>

Bit 0 - ACMP Output Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn outloc(&mut self) -> OUTLOC_W<'_>

Bits 0:5 - I/O Location

impl W<u32, Reg<u32, _EXTIFCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable External Interface

pub fn aportsel(&mut self) -> APORTSEL_W<'_>

Bits 4:7 - APORT Selection for External Interface

impl W<u32, Reg<u32, _CTRL>>

pub fn diff(&mut self) -> DIFF_W<'_>

Bit 0 - Differential Mode

pub fn sinemode(&mut self) -> SINEMODE_W<'_>

Bit 4 - Sine Mode

pub fn outenprs(&mut self) -> OUTENPRS_W<'_>

Bit 5 - PRS Controlled Output Enable

pub fn ch0prescrst(&mut self) -> CH0PRESCRST_W<'_>

Bit 6 - Channel 0 Start Reset Prescaler

pub fn refsel(&mut self) -> REFSEL_W<'_>

Bits 8:10 - Reference Selection

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 16:22 - Prescaler Setting for DAC Clock

pub fn refreshperiod(&mut self) -> REFRESHPERIOD_W<'_>

Bits 24:25 - Refresh Period

pub fn warmupmode(&mut self) -> WARMUPMODE_W<'_>

Bit 28 - Warm-up Mode

pub fn dacclkmode(&mut self) -> DACCLKMODE_W<'_>

Bit 31 - Clock Mode

impl W<u32, Reg<u32, _CH0CTRL>>

pub fn convmode(&mut self) -> CONVMODE_W<'_>

Bit 0 - Conversion Mode

pub fn trigmode(&mut self) -> TRIGMODE_W<'_>

Bits 4:6 - Channel 0 Trigger Mode

pub fn prsasync(&mut self) -> PRSASYNC_W<'_>

Bit 8 - Channel 0 PRS Asynchronous Enable

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 12:16 - Channel 0 PRS Trigger Select

impl W<u32, Reg<u32, _CH1CTRL>>

pub fn convmode(&mut self) -> CONVMODE_W<'_>

Bit 0 - Conversion Mode

pub fn trigmode(&mut self) -> TRIGMODE_W<'_>

Bits 4:6 - Channel 1 Trigger Mode

pub fn prsasync(&mut self) -> PRSASYNC_W<'_>

Bit 8 - Channel 1 PRS Asynchronous Enable

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 12:16 - Channel 1 PRS Trigger Select

impl W<u32, Reg<u32, _CMD>>

pub fn ch0en(&mut self) -> CH0EN_W<'_>

Bit 0 - DAC Channel 0 Enable

pub fn ch0dis(&mut self) -> CH0DIS_W<'_>

Bit 1 - DAC Channel 0 Disable

pub fn ch1en(&mut self) -> CH1EN_W<'_>

Bit 2 - DAC Channel 1 Enable

pub fn ch1dis(&mut self) -> CH1DIS_W<'_>

Bit 3 - DAC Channel 1 Disable

pub fn opa0en(&mut self) -> OPA0EN_W<'_>

Bit 16 - OPA0 Enable

pub fn opa0dis(&mut self) -> OPA0DIS_W<'_>

Bit 17 - OPA0 Disable

pub fn opa1en(&mut self) -> OPA1EN_W<'_>

Bit 18 - OPA1 Enable

pub fn opa1dis(&mut self) -> OPA1DIS_W<'_>

Bit 19 - OPA1 Disable

pub fn opa2en(&mut self) -> OPA2EN_W<'_>

Bit 20 - OPA2 Enable

pub fn opa2dis(&mut self) -> OPA2DIS_W<'_>

Bit 21 - OPA2 Disable

pub fn opa3en(&mut self) -> OPA3EN_W<'_>

Bit 22 - OPA3 Enable

pub fn opa3dis(&mut self) -> OPA3DIS_W<'_>

Bit 23 - OPA3 Disable

impl W<u32, Reg<u32, _IFS>>

pub fn ch0cd(&mut self) -> CH0CD_W<'_>

Bit 0 - Set CH0CD Interrupt Flag

pub fn ch1cd(&mut self) -> CH1CD_W<'_>

Bit 1 - Set CH1CD Interrupt Flag

pub fn ch0of(&mut self) -> CH0OF_W<'_>

Bit 2 - Set CH0OF Interrupt Flag

pub fn ch1of(&mut self) -> CH1OF_W<'_>

Bit 3 - Set CH1OF Interrupt Flag

pub fn ch0uf(&mut self) -> CH0UF_W<'_>

Bit 4 - Set CH0UF Interrupt Flag

pub fn ch1uf(&mut self) -> CH1UF_W<'_>

Bit 5 - Set CH1UF Interrupt Flag

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 15 - Set EM23ERR Interrupt Flag

pub fn opa0aportconflict(&mut self) -> OPA0APORTCONFLICT_W<'_>

Bit 16 - Set OPA0APORTCONFLICT Interrupt Flag

pub fn opa1aportconflict(&mut self) -> OPA1APORTCONFLICT_W<'_>

Bit 17 - Set OPA1APORTCONFLICT Interrupt Flag

pub fn opa2aportconflict(&mut self) -> OPA2APORTCONFLICT_W<'_>

Bit 18 - Set OPA2APORTCONFLICT Interrupt Flag

pub fn opa3aportconflict(&mut self) -> OPA3APORTCONFLICT_W<'_>

Bit 19 - Set OPA3APORTCONFLICT Interrupt Flag

pub fn opa0prstimederr(&mut self) -> OPA0PRSTIMEDERR_W<'_>

Bit 20 - Set OPA0PRSTIMEDERR Interrupt Flag

pub fn opa1prstimederr(&mut self) -> OPA1PRSTIMEDERR_W<'_>

Bit 21 - Set OPA1PRSTIMEDERR Interrupt Flag

pub fn opa2prstimederr(&mut self) -> OPA2PRSTIMEDERR_W<'_>

Bit 22 - Set OPA2PRSTIMEDERR Interrupt Flag

pub fn opa3prstimederr(&mut self) -> OPA3PRSTIMEDERR_W<'_>

Bit 23 - Set OPA3PRSTIMEDERR Interrupt Flag

pub fn opa0outvalid(&mut self) -> OPA0OUTVALID_W<'_>

Bit 28 - Set OPA0OUTVALID Interrupt Flag

pub fn opa1outvalid(&mut self) -> OPA1OUTVALID_W<'_>

Bit 29 - Set OPA1OUTVALID Interrupt Flag

pub fn opa2outvalid(&mut self) -> OPA2OUTVALID_W<'_>

Bit 30 - Set OPA2OUTVALID Interrupt Flag

pub fn opa3outvalid(&mut self) -> OPA3OUTVALID_W<'_>

Bit 31 - Set OPA3OUTVALID Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn ch0cd(&mut self) -> CH0CD_W<'_>

Bit 0 - Clear CH0CD Interrupt Flag

pub fn ch1cd(&mut self) -> CH1CD_W<'_>

Bit 1 - Clear CH1CD Interrupt Flag

pub fn ch0of(&mut self) -> CH0OF_W<'_>

Bit 2 - Clear CH0OF Interrupt Flag

pub fn ch1of(&mut self) -> CH1OF_W<'_>

Bit 3 - Clear CH1OF Interrupt Flag

pub fn ch0uf(&mut self) -> CH0UF_W<'_>

Bit 4 - Clear CH0UF Interrupt Flag

pub fn ch1uf(&mut self) -> CH1UF_W<'_>

Bit 5 - Clear CH1UF Interrupt Flag

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 15 - Clear EM23ERR Interrupt Flag

pub fn opa0aportconflict(&mut self) -> OPA0APORTCONFLICT_W<'_>

Bit 16 - Clear OPA0APORTCONFLICT Interrupt Flag

pub fn opa1aportconflict(&mut self) -> OPA1APORTCONFLICT_W<'_>

Bit 17 - Clear OPA1APORTCONFLICT Interrupt Flag

pub fn opa2aportconflict(&mut self) -> OPA2APORTCONFLICT_W<'_>

Bit 18 - Clear OPA2APORTCONFLICT Interrupt Flag

pub fn opa3aportconflict(&mut self) -> OPA3APORTCONFLICT_W<'_>

Bit 19 - Clear OPA3APORTCONFLICT Interrupt Flag

pub fn opa0prstimederr(&mut self) -> OPA0PRSTIMEDERR_W<'_>

Bit 20 - Clear OPA0PRSTIMEDERR Interrupt Flag

pub fn opa1prstimederr(&mut self) -> OPA1PRSTIMEDERR_W<'_>

Bit 21 - Clear OPA1PRSTIMEDERR Interrupt Flag

pub fn opa2prstimederr(&mut self) -> OPA2PRSTIMEDERR_W<'_>

Bit 22 - Clear OPA2PRSTIMEDERR Interrupt Flag

pub fn opa3prstimederr(&mut self) -> OPA3PRSTIMEDERR_W<'_>

Bit 23 - Clear OPA3PRSTIMEDERR Interrupt Flag

pub fn opa0outvalid(&mut self) -> OPA0OUTVALID_W<'_>

Bit 28 - Clear OPA0OUTVALID Interrupt Flag

pub fn opa1outvalid(&mut self) -> OPA1OUTVALID_W<'_>

Bit 29 - Clear OPA1OUTVALID Interrupt Flag

pub fn opa2outvalid(&mut self) -> OPA2OUTVALID_W<'_>

Bit 30 - Clear OPA2OUTVALID Interrupt Flag

pub fn opa3outvalid(&mut self) -> OPA3OUTVALID_W<'_>

Bit 31 - Clear OPA3OUTVALID Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn ch0cd(&mut self) -> CH0CD_W<'_>

Bit 0 - CH0CD Interrupt Enable

pub fn ch1cd(&mut self) -> CH1CD_W<'_>

Bit 1 - CH1CD Interrupt Enable

pub fn ch0of(&mut self) -> CH0OF_W<'_>

Bit 2 - CH0OF Interrupt Enable

pub fn ch1of(&mut self) -> CH1OF_W<'_>

Bit 3 - CH1OF Interrupt Enable

pub fn ch0uf(&mut self) -> CH0UF_W<'_>

Bit 4 - CH0UF Interrupt Enable

pub fn ch1uf(&mut self) -> CH1UF_W<'_>

Bit 5 - CH1UF Interrupt Enable

pub fn ch0bl(&mut self) -> CH0BL_W<'_>

Bit 6 - CH0BL Interrupt Enable

pub fn ch1bl(&mut self) -> CH1BL_W<'_>

Bit 7 - CH1BL Interrupt Enable

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 15 - EM23ERR Interrupt Enable

pub fn opa0aportconflict(&mut self) -> OPA0APORTCONFLICT_W<'_>

Bit 16 - OPA0APORTCONFLICT Interrupt Enable

pub fn opa1aportconflict(&mut self) -> OPA1APORTCONFLICT_W<'_>

Bit 17 - OPA1APORTCONFLICT Interrupt Enable

pub fn opa2aportconflict(&mut self) -> OPA2APORTCONFLICT_W<'_>

Bit 18 - OPA2APORTCONFLICT Interrupt Enable

pub fn opa3aportconflict(&mut self) -> OPA3APORTCONFLICT_W<'_>

Bit 19 - OPA3APORTCONFLICT Interrupt Enable

pub fn opa0prstimederr(&mut self) -> OPA0PRSTIMEDERR_W<'_>

Bit 20 - OPA0PRSTIMEDERR Interrupt Enable

pub fn opa1prstimederr(&mut self) -> OPA1PRSTIMEDERR_W<'_>

Bit 21 - OPA1PRSTIMEDERR Interrupt Enable

pub fn opa2prstimederr(&mut self) -> OPA2PRSTIMEDERR_W<'_>

Bit 22 - OPA2PRSTIMEDERR Interrupt Enable

pub fn opa3prstimederr(&mut self) -> OPA3PRSTIMEDERR_W<'_>

Bit 23 - OPA3PRSTIMEDERR Interrupt Enable

pub fn opa0outvalid(&mut self) -> OPA0OUTVALID_W<'_>

Bit 28 - OPA0OUTVALID Interrupt Enable

pub fn opa1outvalid(&mut self) -> OPA1OUTVALID_W<'_>

Bit 29 - OPA1OUTVALID Interrupt Enable

pub fn opa2outvalid(&mut self) -> OPA2OUTVALID_W<'_>

Bit 30 - OPA2OUTVALID Interrupt Enable

pub fn opa3outvalid(&mut self) -> OPA3OUTVALID_W<'_>

Bit 31 - OPA3OUTVALID Interrupt Enable

impl W<u32, Reg<u32, _CH0DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:11 - Channel 0 Data

impl W<u32, Reg<u32, _CH1DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:11 - Channel 1 Data

impl W<u32, Reg<u32, _COMBDATA>>

pub fn ch0data(&mut self) -> CH0DATA_W<'_>

Bits 0:11 - Channel 0 Data

pub fn ch1data(&mut self) -> CH1DATA_W<'_>

Bits 16:27 - Channel 1 Data

impl W<u32, Reg<u32, _CAL>>

pub fn offsettrim(&mut self) -> OFFSETTRIM_W<'_>

Bits 0:2 - Input Buffer Offset Calibration Value

pub fn gainerrtrim(&mut self) -> GAINERRTRIM_W<'_>

Bits 8:13 - Gain Error Trim Value

pub fn gainerrtrimch1(&mut self) -> GAINERRTRIMCH1_W<'_>

Bits 16:19 - Gain Error Trim Value for CH1

impl W<u32, Reg<u32, _OPA0_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bits 0:1 - OPAx Operation Mode

pub fn incbw(&mut self) -> INCBW_W<'_>

Bit 2 - OPAx Unity Gain Bandwidth Scale

pub fn hcmdis(&mut self) -> HCMDIS_W<'_>

Bit 3 - High Common Mode Disable

pub fn outscale(&mut self) -> OUTSCALE_W<'_>

Bit 4 - Scale OPAx Output Driving Strength

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 8 - OPAx PRS Trigger Enable

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 9 - OPAx PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 10:14 - OPAx PRS Trigger Select

pub fn prsoutmode(&mut self) -> PRSOUTMODE_W<'_>

Bit 16 - OPAx PRS Output Select

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 20 - APORT Bus Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 21 - APORT Bus Master Disable

impl W<u32, Reg<u32, _OPA0_TIMER>>

pub fn startupdly(&mut self) -> STARTUPDLY_W<'_>

Bits 0:5 - OPAx Startup Delay Count Value

pub fn warmuptime(&mut self) -> WARMUPTIME_W<'_>

Bits 8:14 - OPAx Warmup Time Count Value

pub fn settletime(&mut self) -> SETTLETIME_W<'_>

Bits 16:25 - OPAx Output Settling Timeout Value

impl W<u32, Reg<u32, _OPA0_MUX>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - OPAx Non-inverting Input Mux

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - OPAx Inverting Input Mux

pub fn resinmux(&mut self) -> RESINMUX_W<'_>

Bits 16:18 - OPAx Resistor Ladder Input Mux

pub fn gain3x(&mut self) -> GAIN3X_W<'_>

Bit 20 - OPAx Dedicated 3x Gain Resistor Ladder

pub fn ressel(&mut self) -> RESSEL_W<'_>

Bits 24:26 - OPAx Resistor Ladder Select

impl W<u32, Reg<u32, _OPA0_OUT>>

pub fn mainouten(&mut self) -> MAINOUTEN_W<'_>

Bit 0 - OPAx Main Output Enable

pub fn altouten(&mut self) -> ALTOUTEN_W<'_>

Bit 1 - OPAx Alternative Output Enable

pub fn aportouten(&mut self) -> APORTOUTEN_W<'_>

Bit 2 - OPAx Aport Output Enable

pub fn short(&mut self) -> SHORT_W<'_>

Bit 3 - OPAx Main and Alternative Output Short

pub fn altoutpaden(&mut self) -> ALTOUTPADEN_W<'_>

Bits 4:8 - OPAx Output Enable Value

pub fn aportoutsel(&mut self) -> APORTOUTSEL_W<'_>

Bits 16:23 - OPAx APORT Output

impl W<u32, Reg<u32, _OPA0_CAL>>

pub fn cm1(&mut self) -> CM1_W<'_>

Bits 0:3 - Compensation Cap Cm1 Trim Value

pub fn cm2(&mut self) -> CM2_W<'_>

Bits 5:8 - Compensation Cap Cm2 Trim Value

pub fn cm3(&mut self) -> CM3_W<'_>

Bits 10:11 - Compensation Cap Cm3 Trim Value

pub fn gm(&mut self) -> GM_W<'_>

Bits 13:15 - Gm Trim Value

pub fn gm3(&mut self) -> GM3_W<'_>

Bits 17:18 - Gm3 Trim Value

pub fn offsetp(&mut self) -> OFFSETP_W<'_>

Bits 20:24 - OPAx Non-Inverting Input Offset Configuration Value

pub fn offsetn(&mut self) -> OFFSETN_W<'_>

Bits 26:30 - OPAx Inverting Input Offset Configuration Value

impl W<u32, Reg<u32, _OPA1_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bits 0:1 - OPAx Operation Mode

pub fn incbw(&mut self) -> INCBW_W<'_>

Bit 2 - OPAx Unity Gain Bandwidth Scale

pub fn hcmdis(&mut self) -> HCMDIS_W<'_>

Bit 3 - High Common Mode Disable

pub fn outscale(&mut self) -> OUTSCALE_W<'_>

Bit 4 - Scale OPAx Output Driving Strength

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 8 - OPAx PRS Trigger Enable

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 9 - OPAx PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 10:14 - OPAx PRS Trigger Select

pub fn prsoutmode(&mut self) -> PRSOUTMODE_W<'_>

Bit 16 - OPAx PRS Output Select

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 20 - APORT Bus Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 21 - APORT Bus Master Disable

impl W<u32, Reg<u32, _OPA1_TIMER>>

pub fn startupdly(&mut self) -> STARTUPDLY_W<'_>

Bits 0:5 - OPAx Startup Delay Count Value

pub fn warmuptime(&mut self) -> WARMUPTIME_W<'_>

Bits 8:14 - OPAx Warmup Time Count Value

pub fn settletime(&mut self) -> SETTLETIME_W<'_>

Bits 16:25 - OPAx Output Settling Timeout Value

impl W<u32, Reg<u32, _OPA1_MUX>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - OPAx Non-inverting Input Mux

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - OPAx Inverting Input Mux

pub fn resinmux(&mut self) -> RESINMUX_W<'_>

Bits 16:18 - OPAx Resistor Ladder Input Mux

pub fn gain3x(&mut self) -> GAIN3X_W<'_>

Bit 20 - OPAx Dedicated 3x Gain Resistor Ladder

pub fn ressel(&mut self) -> RESSEL_W<'_>

Bits 24:26 - OPAx Resistor Ladder Select

impl W<u32, Reg<u32, _OPA1_OUT>>

pub fn mainouten(&mut self) -> MAINOUTEN_W<'_>

Bit 0 - OPAx Main Output Enable

pub fn altouten(&mut self) -> ALTOUTEN_W<'_>

Bit 1 - OPAx Alternative Output Enable

pub fn aportouten(&mut self) -> APORTOUTEN_W<'_>

Bit 2 - OPAx Aport Output Enable

pub fn short(&mut self) -> SHORT_W<'_>

Bit 3 - OPAx Main and Alternative Output Short

pub fn altoutpaden(&mut self) -> ALTOUTPADEN_W<'_>

Bits 4:8 - OPAx Output Enable Value

pub fn aportoutsel(&mut self) -> APORTOUTSEL_W<'_>

Bits 16:23 - OPAx APORT Output

impl W<u32, Reg<u32, _OPA1_CAL>>

pub fn cm1(&mut self) -> CM1_W<'_>

Bits 0:3 - Compensation Cap Cm1 Trim Value

pub fn cm2(&mut self) -> CM2_W<'_>

Bits 5:8 - Compensation Cap Cm2 Trim Value

pub fn cm3(&mut self) -> CM3_W<'_>

Bits 10:11 - Compensation Cap Cm3 Trim Value

pub fn gm(&mut self) -> GM_W<'_>

Bits 13:15 - Gm Trim Value

pub fn gm3(&mut self) -> GM3_W<'_>

Bits 17:18 - Gm3 Trim Value

pub fn offsetp(&mut self) -> OFFSETP_W<'_>

Bits 20:24 - OPAx Non-Inverting Input Offset Configuration Value

pub fn offsetn(&mut self) -> OFFSETN_W<'_>

Bits 26:30 - OPAx Inverting Input Offset Configuration Value

impl W<u32, Reg<u32, _OPA2_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bits 0:1 - OPAx Operation Mode

pub fn incbw(&mut self) -> INCBW_W<'_>

Bit 2 - OPAx Unity Gain Bandwidth Scale

pub fn hcmdis(&mut self) -> HCMDIS_W<'_>

Bit 3 - High Common Mode Disable

pub fn outscale(&mut self) -> OUTSCALE_W<'_>

Bit 4 - Scale OPAx Output Driving Strength

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 8 - OPAx PRS Trigger Enable

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 9 - OPAx PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 10:14 - OPAx PRS Trigger Select

pub fn prsoutmode(&mut self) -> PRSOUTMODE_W<'_>

Bit 16 - OPAx PRS Output Select

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 20 - APORT Bus Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 21 - APORT Bus Master Disable

impl W<u32, Reg<u32, _OPA2_TIMER>>

pub fn startupdly(&mut self) -> STARTUPDLY_W<'_>

Bits 0:5 - OPAx Startup Delay Count Value

pub fn warmuptime(&mut self) -> WARMUPTIME_W<'_>

Bits 8:14 - OPAx Warmup Time Count Value

pub fn settletime(&mut self) -> SETTLETIME_W<'_>

Bits 16:25 - OPAx Output Settling Timeout Value

impl W<u32, Reg<u32, _OPA2_MUX>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - OPAx Non-inverting Input Mux

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - OPAx Inverting Input Mux

pub fn resinmux(&mut self) -> RESINMUX_W<'_>

Bits 16:18 - OPAx Resistor Ladder Input Mux

pub fn gain3x(&mut self) -> GAIN3X_W<'_>

Bit 20 - OPAx Dedicated 3x Gain Resistor Ladder

pub fn ressel(&mut self) -> RESSEL_W<'_>

Bits 24:26 - OPAx Resistor Ladder Select

impl W<u32, Reg<u32, _OPA2_OUT>>

pub fn mainouten(&mut self) -> MAINOUTEN_W<'_>

Bit 0 - OPAx Main Output Enable

pub fn altouten(&mut self) -> ALTOUTEN_W<'_>

Bit 1 - OPAx Alternative Output Enable

pub fn aportouten(&mut self) -> APORTOUTEN_W<'_>

Bit 2 - OPAx Aport Output Enable

pub fn short(&mut self) -> SHORT_W<'_>

Bit 3 - OPAx Main and Alternative Output Short

pub fn altoutpaden(&mut self) -> ALTOUTPADEN_W<'_>

Bits 4:8 - OPAx Output Enable Value

pub fn aportoutsel(&mut self) -> APORTOUTSEL_W<'_>

Bits 16:23 - OPAx APORT Output

impl W<u32, Reg<u32, _OPA2_CAL>>

pub fn cm1(&mut self) -> CM1_W<'_>

Bits 0:3 - Compensation Cap Cm1 Trim Value

pub fn cm2(&mut self) -> CM2_W<'_>

Bits 5:8 - Compensation Cap Cm2 Trim Value

pub fn cm3(&mut self) -> CM3_W<'_>

Bits 10:11 - Compensation Cap Cm3 Trim Value

pub fn gm(&mut self) -> GM_W<'_>

Bits 13:15 - Gm Trim Value

pub fn gm3(&mut self) -> GM3_W<'_>

Bits 17:18 - Gm3 Trim Value

pub fn offsetp(&mut self) -> OFFSETP_W<'_>

Bits 20:24 - OPAx Non-Inverting Input Offset Configuration Value

pub fn offsetn(&mut self) -> OFFSETN_W<'_>

Bits 26:30 - OPAx Inverting Input Offset Configuration Value

impl W<u32, Reg<u32, _OPA3_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bits 0:1 - OPAx Operation Mode

pub fn incbw(&mut self) -> INCBW_W<'_>

Bit 2 - OPAx Unity Gain Bandwidth Scale

pub fn hcmdis(&mut self) -> HCMDIS_W<'_>

Bit 3 - High Common Mode Disable

pub fn outscale(&mut self) -> OUTSCALE_W<'_>

Bit 4 - Scale OPAx Output Driving Strength

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 8 - OPAx PRS Trigger Enable

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 9 - OPAx PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 10:14 - OPAx PRS Trigger Select

pub fn prsoutmode(&mut self) -> PRSOUTMODE_W<'_>

Bit 16 - OPAx PRS Output Select

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 20 - APORT Bus Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 21 - APORT Bus Master Disable

impl W<u32, Reg<u32, _OPA3_TIMER>>

pub fn startupdly(&mut self) -> STARTUPDLY_W<'_>

Bits 0:5 - OPAx Startup Delay Count Value

pub fn warmuptime(&mut self) -> WARMUPTIME_W<'_>

Bits 8:14 - OPAx Warmup Time Count Value

pub fn settletime(&mut self) -> SETTLETIME_W<'_>

Bits 16:25 - OPAx Output Settling Timeout Value

impl W<u32, Reg<u32, _OPA3_MUX>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - OPAx Non-inverting Input Mux

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - OPAx Inverting Input Mux

pub fn resinmux(&mut self) -> RESINMUX_W<'_>

Bits 16:18 - OPAx Resistor Ladder Input Mux

pub fn gain3x(&mut self) -> GAIN3X_W<'_>

Bit 20 - OPAx Dedicated 3x Gain Resistor Ladder

pub fn ressel(&mut self) -> RESSEL_W<'_>

Bits 24:26 - OPAx Resistor Ladder Select

impl W<u32, Reg<u32, _OPA3_OUT>>

pub fn mainouten(&mut self) -> MAINOUTEN_W<'_>

Bit 0 - OPAx Main Output Enable

pub fn altouten(&mut self) -> ALTOUTEN_W<'_>

Bit 1 - OPAx Alternative Output Enable

pub fn aportouten(&mut self) -> APORTOUTEN_W<'_>

Bit 2 - OPAx Aport Output Enable

pub fn short(&mut self) -> SHORT_W<'_>

Bit 3 - OPAx Main and Alternative Output Short

pub fn altoutpaden(&mut self) -> ALTOUTPADEN_W<'_>

Bits 4:8 - OPAx Output Enable Value

pub fn aportoutsel(&mut self) -> APORTOUTSEL_W<'_>

Bits 16:23 - OPAx APORT Output

impl W<u32, Reg<u32, _OPA3_CAL>>

pub fn cm1(&mut self) -> CM1_W<'_>

Bits 0:3 - Compensation Cap Cm1 Trim Value

pub fn cm2(&mut self) -> CM2_W<'_>

Bits 5:8 - Compensation Cap Cm2 Trim Value

pub fn cm3(&mut self) -> CM3_W<'_>

Bits 10:11 - Compensation Cap Cm3 Trim Value

pub fn gm(&mut self) -> GM_W<'_>

Bits 13:15 - Gm Trim Value

pub fn gm3(&mut self) -> GM3_W<'_>

Bits 17:18 - Gm3 Trim Value

pub fn offsetp(&mut self) -> OFFSETP_W<'_>

Bits 20:24 - OPAx Non-Inverting Input Offset Configuration Value

pub fn offsetn(&mut self) -> OFFSETN_W<'_>

Bits 26:30 - OPAx Inverting Input Offset Configuration Value

impl W<u32, Reg<u32, _CTRL>>

pub fn vbusenap(&mut self) -> VBUSENAP_W<'_>

Bit 0 - VBUSEN Active Polarity

pub fn selfpowered(&mut self) -> SELFPOWERED_W<'_>

Bit 3 - PHY Power

pub fn lemoscctrl(&mut self) -> LEMOSCCTRL_W<'_>

Bits 4:5 - Low Energy Mode Oscillator Control

pub fn lemphyctrl(&mut self) -> LEMPHYCTRL_W<'_>

Bit 7 - Low Energy Mode USB PHY Control

pub fn lemidleen(&mut self) -> LEMIDLEEN_W<'_>

Bit 9 - Low Energy Mode on Bus Idle Enable

pub fn idcden(&mut self) -> IDCDEN_W<'_>

Bit 12 - ID Pull-up Enable

pub fn otgclkcdis(&mut self) -> OTGCLKCDIS_W<'_>

Bit 25 - OTG CLKC Disable

pub fn otgidindis(&mut self) -> OTGIDINDIS_W<'_>

Bit 26 - OTG ID Input Disable

pub fn otgphyctrldis(&mut self) -> OTGPHYCTRLDIS_W<'_>

Bit 27 - OTG Control Signals to PHY Disable

pub fn dcden(&mut self) -> DCDEN_W<'_>

Bits 28:29 - Data Contact Detection Enable

pub fn pden(&mut self) -> PDEN_W<'_>

Bit 30 - Primary Detection Enable

pub fn sden(&mut self) -> SDEN_W<'_>

Bit 31 - Secondary Detection Enable

impl W<u32, Reg<u32, _IFS>>

pub fn vbusdeth(&mut self) -> VBUSDETH_W<'_>

Bit 0 - Set VBUSDETH Interrupt Flag

pub fn vbusdetl(&mut self) -> VBUSDETL_W<'_>

Bit 1 - Set VBUSDETL Interrupt Flag

pub fn err(&mut self) -> ERR_W<'_>

Bit 8 - Set ERR Interrupt Flag

pub fn dcd(&mut self) -> DCD_W<'_>

Bit 9 - Set DCD Interrupt Flag

pub fn pd(&mut self) -> PD_W<'_>

Bit 10 - Set PD Interrupt Flag

pub fn sd(&mut self) -> SD_W<'_>

Bit 11 - Set SD Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn vbusdeth(&mut self) -> VBUSDETH_W<'_>

Bit 0 - Clear VBUSDETH Interrupt Flag

pub fn vbusdetl(&mut self) -> VBUSDETL_W<'_>

Bit 1 - Clear VBUSDETL Interrupt Flag

pub fn err(&mut self) -> ERR_W<'_>

Bit 8 - Clear ERR Interrupt Flag

pub fn dcd(&mut self) -> DCD_W<'_>

Bit 9 - Clear DCD Interrupt Flag

pub fn pd(&mut self) -> PD_W<'_>

Bit 10 - Clear PD Interrupt Flag

pub fn sd(&mut self) -> SD_W<'_>

Bit 11 - Clear SD Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn vbusdeth(&mut self) -> VBUSDETH_W<'_>

Bit 0 - VBUSDETH Interrupt Enable

pub fn vbusdetl(&mut self) -> VBUSDETL_W<'_>

Bit 1 - VBUSDETL Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 8 - ERR Interrupt Enable

pub fn dcd(&mut self) -> DCD_W<'_>

Bit 9 - DCD Interrupt Enable

pub fn pd(&mut self) -> PD_W<'_>

Bit 10 - PD Interrupt Enable

pub fn sd(&mut self) -> SD_W<'_>

Bit 11 - SD Interrupt Enable

impl W<u32, Reg<u32, _ROUTE>>

pub fn phypen(&mut self) -> PHYPEN_W<'_>

Bit 0 - USB PHY Pin Enable

pub fn vbusenpen(&mut self) -> VBUSENPEN_W<'_>

Bit 1 - VBUSEN Pin Enable

impl W<u32, Reg<u32, _CDCONF>>

pub fn dcdtoconf(&mut self) -> DCDTOCONF_W<'_>

Bits 0:9 - DCD Timeout (TDCD_TIMEOUT) Configuration

impl W<u32, Reg<u32, _CMD>>

pub fn startcd(&mut self) -> STARTCD_W<'_>

Bit 0 - Start Charger Detection Enabled

pub fn stopcd(&mut self) -> STOPCD_W<'_>

Bit 1 - Start Charger Detection in Progress

impl W<u32, Reg<u32, _DATTRIM1>>

pub fn rout(&mut self) -> ROUT_W<'_>

Bits 0:5 - Trim for DP and DM Output Impedance for Both FS and LS

pub fn endlypullup(&mut self) -> ENDLYPULLUP_W<'_>

Bit 7 - Enables Delay of Pull in TX Mode for Both FS and LS

pub fn dlypullupfs(&mut self) -> DLYPULLUPFS_W<'_>

Bits 8:9 - Trim for Rising Crossover Voltage in FS

pub fn vcrsfs(&mut self) -> VCRSFS_W<'_>

Bits 10:11 - Trim for Falling Crossover Voltage in FS

pub fn tfdmfs(&mut self) -> TFDMFS_W<'_>

Bits 12:13 - Trim for DM Fall Time in FS

pub fn trdmfs(&mut self) -> TRDMFS_W<'_>

Bits 14:15 - Trim for DM Rise Time in FS

pub fn tfdpfs(&mut self) -> TFDPFS_W<'_>

Bits 16:17 - Trim for DP Fall Time in FS

pub fn trdpfs(&mut self) -> TRDPFS_W<'_>

Bits 18:19 - Trim for DP Rise Time in FS

impl W<u32, Reg<u32, _LEMCTRL>>

pub fn timebase(&mut self) -> TIMEBASE_W<'_>

Bits 0:9 - Set the Number of LFC Clk Counts to Form 3ms

impl W<u32, Reg<u32, _GOTGCTL>>

pub fn sesreq(&mut self) -> SESREQ_W<'_>

Bit 1 - Session Request

pub fn vbvalidoven(&mut self) -> VBVALIDOVEN_W<'_>

Bit 2 - VBUS Valid Override Enable

pub fn vbvalidovval(&mut self) -> VBVALIDOVVAL_W<'_>

Bit 3 - VBUS Valid OverrideValue

pub fn avalidoven(&mut self) -> AVALIDOVEN_W<'_>

Bit 4 - A-Peripheral Session Valid Override Enable

pub fn avalidovval(&mut self) -> AVALIDOVVAL_W<'_>

Bit 5 - A-Peripheral Session Valid OverrideValue

pub fn bvalidoven(&mut self) -> BVALIDOVEN_W<'_>

Bit 6 - B-Peripheral Session Valid Override Enable

pub fn bvalidovval(&mut self) -> BVALIDOVVAL_W<'_>

Bit 7 - B-Peripheral Session Valid OverrideValue

pub fn hnpreq(&mut self) -> HNPREQ_W<'_>

Bit 9 - HNP Request

pub fn hstsethnpen(&mut self) -> HSTSETHNPEN_W<'_>

Bit 10 - Host Set HNP Enable

pub fn devhnpen(&mut self) -> DEVHNPEN_W<'_>

Bit 11 - Device HNP Enabled

pub fn ehen(&mut self) -> EHEN_W<'_>

Bit 12 - Embedded Host Enable

pub fn dbncefltrbypass(&mut self) -> DBNCEFLTRBYPASS_W<'_>

Bit 15 - Debounce Filter Bypass

pub fn otgver(&mut self) -> OTGVER_W<'_>

Bit 20 - OTG Version

impl W<u32, Reg<u32, _GOTGINT>>

pub fn sesenddet(&mut self) -> SESENDDET_W<'_>

Bit 2 - Session End Detected

pub fn sesreqsucstschng(&mut self) -> SESREQSUCSTSCHNG_W<'_>

Bit 8 - Session Request Success Status Change

pub fn hstnegsucstschng(&mut self) -> HSTNEGSUCSTSCHNG_W<'_>

Bit 9 - Host Negotiation Success Status Change

pub fn hstnegdet(&mut self) -> HSTNEGDET_W<'_>

Bit 17 - Host Negotiation Detected

pub fn adevtoutchg(&mut self) -> ADEVTOUTCHG_W<'_>

Bit 18 - A-Device Timeout Change

pub fn dbncedone(&mut self) -> DBNCEDONE_W<'_>

Bit 19 - Debounce Done

impl W<u32, Reg<u32, _GAHBCFG>>

pub fn glblintrmsk(&mut self) -> GLBLINTRMSK_W<'_>

Bit 0 - Global Interrupt Mask

pub fn hbstlen(&mut self) -> HBSTLEN_W<'_>

Bits 1:4 - Burst Length/Type

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 5 - DMA Enable

pub fn nptxfemplvl(&mut self) -> NPTXFEMPLVL_W<'_>

Bit 7 - Non-Periodic TxFIFO Empty Level

pub fn ptxfemplvl(&mut self) -> PTXFEMPLVL_W<'_>

Bit 8 - Periodic TxFIFO Empty Level

pub fn remmemsupp(&mut self) -> REMMEMSUPP_W<'_>

Bit 21 - Remote Memory Support

pub fn notialldmawrit(&mut self) -> NOTIALLDMAWRIT_W<'_>

Bit 22 - Notify All Dma Write Transactions

pub fn ahbsingle(&mut self) -> AHBSINGLE_W<'_>

Bit 23 - AHB Single Support

impl W<u32, Reg<u32, _GUSBCFG>>

pub fn toutcal(&mut self) -> TOUTCAL_W<'_>

Bits 0:2 - Timeout Calibration (host and device)

pub fn fsintf(&mut self) -> FSINTF_W<'_>

Bit 5 - Full-Speed Serial Interface Select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>

Bit 8 - SRP-Capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>

Bit 9 - HNP-Capable

pub fn usbtrdtim(&mut self) -> USBTRDTIM_W<'_>

Bits 10:13 - USB Turnaround Time

pub fn termseldlpulse(&mut self) -> TERMSELDLPULSE_W<'_>

Bit 22 - TermSel DLine Pulsing Selection

pub fn txenddelay(&mut self) -> TXENDDELAY_W<'_>

Bit 28 - Tx End Delay

pub fn forcehstmode(&mut self) -> FORCEHSTMODE_W<'_>

Bit 29 - Force Host Mode

pub fn forcedevmode(&mut self) -> FORCEDEVMODE_W<'_>

Bit 30 - Force Device Mode

pub fn corrupttxpkt(&mut self) -> CORRUPTTXPKT_W<'_>

Bit 31 - Corrupt Tx packet (host and device)

impl W<u32, Reg<u32, _GRSTCTL>>

pub fn csftrst(&mut self) -> CSFTRST_W<'_>

Bit 0 - Core Soft Reset (host and device)

pub fn piufssftrst(&mut self) -> PIUFSSFTRST_W<'_>

Bit 1 - PIU FS Dedicated Controller Soft Reset

pub fn frmcntrrst(&mut self) -> FRMCNTRRST_W<'_>

Bit 2 - Host Frame Counter Reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO Flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO Flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO Number (host and device)

impl W<u32, Reg<u32, _GINTSTS>>

pub fn modemis(&mut self) -> MODEMIS_W<'_>

Bit 1 - Mode Mismatch Interrupt (host and device)

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of Frame (host and device)

pub fn erlysusp(&mut self) -> ERLYSUSP_W<'_>

Bit 10 - Early Suspend (device only)

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB Suspend (device only)

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB Reset (device only)

pub fn enumdone(&mut self) -> ENUMDONE_W<'_>

Bit 13 - Enumeration Done (device only)

pub fn isooutdrop(&mut self) -> ISOOUTDROP_W<'_>

Bit 14 - Isochronous OUT Packet Dropped Interrupt (device only)

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of Periodic Frame Interrupt

pub fn epmis(&mut self) -> EPMIS_W<'_>

Bit 17 - Endpoint Mismatch Interrupt (device only)

pub fn incompisoin(&mut self) -> INCOMPISOIN_W<'_>

Bit 20 - Incomplete Isochronous IN Transfer (device only)

pub fn incomplp(&mut self) -> INCOMPLP_W<'_>

Bit 21 - Incomplete Periodic Transfer (device only)

pub fn fetsusp(&mut self) -> FETSUSP_W<'_>

Bit 22 - Data Fetch Suspended (device only)

pub fn resetdet(&mut self) -> RESETDET_W<'_>

Bit 23 - Reset detected Interrupt (device only)

pub fn conidstschng(&mut self) -> CONIDSTSCHNG_W<'_>

Bit 28 - Connector ID Status Change (host and device)

pub fn disconnint(&mut self) -> DISCONNINT_W<'_>

Bit 29 - Disconnect Detected Interrupt (host only)

pub fn sessreqint(&mut self) -> SESSREQINT_W<'_>

Bit 30 - Session Request/New Session Detected Interrupt (host and device)

pub fn wkupint(&mut self) -> WKUPINT_W<'_>

Bit 31 - Resume/Remote Wakeup Detected Interrupt (host and device)

impl W<u32, Reg<u32, _GINTMSK>>

pub fn modemismsk(&mut self) -> MODEMISMSK_W<'_>

Bit 1 - Mode Mismatch Interrupt Mask (host and device)

pub fn otgintmsk(&mut self) -> OTGINTMSK_W<'_>

Bit 2 - OTG Interrupt Mask (host and device)

pub fn sofmsk(&mut self) -> SOFMSK_W<'_>

Bit 3 - Start of Frame Mask (host and device)

pub fn rxflvlmsk(&mut self) -> RXFLVLMSK_W<'_>

Bit 4 - Receive FIFO Non-Empty Mask (host and device)

pub fn nptxfempmsk(&mut self) -> NPTXFEMPMSK_W<'_>

Bit 5 - Non-Periodic TxFIFO Empty Mask (host only)

pub fn ginnakeffmsk(&mut self) -> GINNAKEFFMSK_W<'_>

Bit 6 - Global Non-periodic IN NAK Effective Mask (device only)

pub fn goutnakeffmsk(&mut self) -> GOUTNAKEFFMSK_W<'_>

Bit 7 - Global OUT NAK Effective Mask (device only)

pub fn erlysuspmsk(&mut self) -> ERLYSUSPMSK_W<'_>

Bit 10 - Early Suspend Mask (device only)

pub fn usbsuspmsk(&mut self) -> USBSUSPMSK_W<'_>

Bit 11 - USB Suspend Mask (device only)

pub fn usbrstmsk(&mut self) -> USBRSTMSK_W<'_>

Bit 12 - USB Reset Mask (device only)

pub fn enumdonemsk(&mut self) -> ENUMDONEMSK_W<'_>

Bit 13 - Enumeration Done Mask (device only)

pub fn isooutdropmsk(&mut self) -> ISOOUTDROPMSK_W<'_>

Bit 14 - Isochronous OUT Packet Dropped Interrupt Mask (device only)

pub fn eopfmsk(&mut self) -> EOPFMSK_W<'_>

Bit 15 - End of Periodic Frame Interrupt Mask (device only)

pub fn epmismsk(&mut self) -> EPMISMSK_W<'_>

Bit 17 - Endpoint Mismatch Interrupt Mask (device only)

pub fn iepintmsk(&mut self) -> IEPINTMSK_W<'_>

Bit 18 - IN Endpoints Interrupt Mask (device only)

pub fn oepintmsk(&mut self) -> OEPINTMSK_W<'_>

Bit 19 - OUT Endpoints Interrupt Mask (device only)

pub fn incompisoinmsk(&mut self) -> INCOMPISOINMSK_W<'_>

Bit 20 - Incomplete Isochronous IN Transfer Mask (device only)

pub fn incomplpmsk(&mut self) -> INCOMPLPMSK_W<'_>

Bit 21 - Incomplete Periodic Transfer Mask (host only)

pub fn fetsuspmsk(&mut self) -> FETSUSPMSK_W<'_>

Bit 22 - Data Fetch Suspended Mask (device only)

pub fn resetdetmsk(&mut self) -> RESETDETMSK_W<'_>

Bit 23 - Reset detected Interrupt Mask (device only)

pub fn prtintmsk(&mut self) -> PRTINTMSK_W<'_>

Bit 24 - Host Port Interrupt Mask (host only)

pub fn hchintmsk(&mut self) -> HCHINTMSK_W<'_>

Bit 25 - Host Channels Interrupt Mask (host only)

pub fn ptxfempmsk(&mut self) -> PTXFEMPMSK_W<'_>

Bit 26 - Periodic TxFIFO Empty Mask (host only)

pub fn conidstschngmsk(&mut self) -> CONIDSTSCHNGMSK_W<'_>

Bit 28 - Connector ID Status Change Mask (host and device)

pub fn disconnintmsk(&mut self) -> DISCONNINTMSK_W<'_>

Bit 29 - Disconnect Detected Interrupt Mask (host and device)

pub fn sessreqintmsk(&mut self) -> SESSREQINTMSK_W<'_>

Bit 30 - Session Request/New Session Detected Interrupt Mask (host and device)

pub fn wkupintmsk(&mut self) -> WKUPINTMSK_W<'_>

Bit 31 - Resume/Remote Wakeup Detected Interrupt Mask (host and device)

impl W<u32, Reg<u32, _GRXFSIZ>>

pub fn rxfdep(&mut self) -> RXFDEP_W<'_>

Bits 0:9 - RxFIFO Depth

impl W<u32, Reg<u32, _GNPTXFSIZ>>

pub fn nptxfstaddr(&mut self) -> NPTXFSTADDR_W<'_>

Bits 0:15 - Non-periodic Transmit RAM Start Address

pub fn nptxfineptxf0dep(&mut self) -> NPTXFINEPTXF0DEP_W<'_>

Bits 16:31 - Non-periodic TxFIFO Depth (host only) / IN Endpoint TxFIFO 0 Depth (device only)

impl W<u32, Reg<u32, _GDFIFOCFG>>

pub fn gdfifocfg(&mut self) -> GDFIFOCFG_W<'_>

Bits 0:15

pub fn epinfobaseaddr(&mut self) -> EPINFOBASEADDR_W<'_>

Bits 16:31

impl W<u32, Reg<u32, _HPTXFSIZ>>

pub fn ptxfstaddr(&mut self) -> PTXFSTADDR_W<'_>

Bits 0:10 - Host Periodic TxFIFO Start Address

pub fn ptxfsize(&mut self) -> PTXFSIZE_W<'_>

Bits 16:25 - Host Periodic TxFIFO Depth

impl W<u32, Reg<u32, _DIEPTXF1>>

pub fn inepntxfstaddr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:10 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepntxfdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:25 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _DIEPTXF2>>

pub fn inepntxfstaddr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:10 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepntxfdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:25 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _DIEPTXF3>>

pub fn inepntxfstaddr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:11 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepntxfdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:25 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _DIEPTXF4>>

pub fn inepntxfstaddr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:11 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepntxfdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:25 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _DIEPTXF5>>

pub fn inepntxfstaddr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:11 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepntxfdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:25 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _DIEPTXF6>>

pub fn inepntxfstaddr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:11 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepntxfdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:25 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _HCFG>>

pub fn fslspclksel(&mut self) -> FSLSPCLKSEL_W<'_>

Bits 0:1 - FS/LS PHY Clock Select

pub fn fslssupp(&mut self) -> FSLSSUPP_W<'_>

Bit 2 - FS- and LS-Only Support

pub fn ena32khzs(&mut self) -> ENA32KHZS_W<'_>

Bit 7 - Enable 32 kHz Suspend Mode

pub fn resvalid(&mut self) -> RESVALID_W<'_>

Bits 8:15 - Resume Validation Period

pub fn modechtimen(&mut self) -> MODECHTIMEN_W<'_>

Bit 31 - Mode Change Time

impl W<u32, Reg<u32, _HFIR>>

pub fn frint(&mut self) -> FRINT_W<'_>

Bits 0:15 - Frame Interval

pub fn hfirrldctrl(&mut self) -> HFIRRLDCTRL_W<'_>

Bit 16 - Reload Control

impl W<u32, Reg<u32, _HAINTMSK>>

pub fn haintmsk(&mut self) -> HAINTMSK_W<'_>

Bits 0:13 - Channel Interrupt Mask for channel 0 - 13

impl W<u32, Reg<u32, _HPRT>>

pub fn prtconndet(&mut self) -> PRTCONNDET_W<'_>

Bit 1 - Port Connect Detected

pub fn prtena(&mut self) -> PRTENA_W<'_>

Bit 2 - Port Enable

pub fn prtenchng(&mut self) -> PRTENCHNG_W<'_>

Bit 3 - Port Enable/Disable Change

pub fn prtovrcurrchng(&mut self) -> PRTOVRCURRCHNG_W<'_>

Bit 5 - Port Overcurrent Change

pub fn prtres(&mut self) -> PRTRES_W<'_>

Bit 6 - Port Resume

pub fn prtsusp(&mut self) -> PRTSUSP_W<'_>

Bit 7 - Port Suspend

pub fn prtrst(&mut self) -> PRTRST_W<'_>

Bit 8 - Port Reset

pub fn prtpwr(&mut self) -> PRTPWR_W<'_>

Bit 12 - Port Power

pub fn prttstctl(&mut self) -> PRTTSTCTL_W<'_>

Bits 13:16 - Port Test Control

impl W<u32, Reg<u32, _HC0_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC0_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC0_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC0_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC0_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC0_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC1_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC1_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC1_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC1_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC1_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC1_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC2_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC2_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC2_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC2_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC2_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC2_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC3_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC3_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC3_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC3_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC3_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC3_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC4_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC4_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC4_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC4_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC4_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC4_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC5_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC5_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC5_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC5_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC5_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC5_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC6_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC6_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC6_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC6_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC6_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC6_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC7_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC7_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC7_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC7_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC7_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC7_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC8_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC8_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC8_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC8_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC8_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC8_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC9_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC9_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC9_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC9_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC9_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC9_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC10_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC10_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC10_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC10_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC10_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC10_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC11_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC11_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC11_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC11_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC11_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC11_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC12_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC12_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC12_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC12_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC12_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC12_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _HC13_CHAR>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn epnum(&mut self) -> EPNUM_W<'_>

Bits 11:14 - Endpoint Number

pub fn epdir(&mut self) -> EPDIR_W<'_>

Bit 15 - Endpoint Direction

pub fn lspddev(&mut self) -> LSPDDEV_W<'_>

Bit 17 - Low-Speed Device

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn mc(&mut self) -> MC_W<'_>

Bits 20:21 - Multi Count (MC) / Error Count

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 22:28 - Device Address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>

Bit 29 - Odd Frame

pub fn chdis(&mut self) -> CHDIS_W<'_>

Bit 30 - Channel Disable

pub fn chena(&mut self) -> CHENA_W<'_>

Bit 31 - Channel Enable

impl W<u32, Reg<u32, _HC13_SPLT>>

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>

Bits 0:6 - Port Address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>

Bits 7:13 - Hub Address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>

Bits 14:15 - Transaction Position

pub fn compsplt(&mut self) -> COMPSPLT_W<'_>

Bit 16 - Do Complete Split

pub fn spltena(&mut self) -> SPLTENA_W<'_>

Bit 31 - Split Enable

impl W<u32, Reg<u32, _HC13_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed

pub fn chhltd(&mut self) -> CHHLTD_W<'_>

Bit 1 - Channel Halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn stall(&mut self) -> STALL_W<'_>

Bit 3 - STALL Response Received Interrupt

pub fn nak(&mut self) -> NAK_W<'_>

Bit 4 - NAK Response Received Interrupt

pub fn ack(&mut self) -> ACK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt

pub fn xacterr(&mut self) -> XACTERR_W<'_>

Bit 7 - Transaction Error

pub fn bblerr(&mut self) -> BBLERR_W<'_>

Bit 8 - Babble Error

pub fn frmovrun(&mut self) -> FRMOVRUN_W<'_>

Bit 9 - Frame Overrun

pub fn datatglerr(&mut self) -> DATATGLERR_W<'_>

Bit 10 - Data Toggle Error

impl W<u32, Reg<u32, _HC13_INTMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Mask

pub fn chhltdmsk(&mut self) -> CHHLTDMSK_W<'_>

Bit 1 - Channel Halted Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn stallmsk(&mut self) -> STALLMSK_W<'_>

Bit 3 - STALL Response Received Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 4 - NAK Response Received Interrupt Mask

pub fn ackmsk(&mut self) -> ACKMSK_W<'_>

Bit 5 - ACK Response Received/Transmitted Interrupt Mask

pub fn xacterrmsk(&mut self) -> XACTERRMSK_W<'_>

Bit 7 - Transaction Error Mask

pub fn bblerrmsk(&mut self) -> BBLERRMSK_W<'_>

Bit 8 - Babble Error Mask

pub fn frmovrunmsk(&mut self) -> FRMOVRUNMSK_W<'_>

Bit 9 - Frame Overrun Mask

pub fn datatglerrmsk(&mut self) -> DATATGLERRMSK_W<'_>

Bit 10 - Data Toggle Error Mask

impl W<u32, Reg<u32, _HC13_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn pid(&mut self) -> PID_W<'_>

Bits 29:30 - The Application Programs This Field With the Type of

impl W<u32, Reg<u32, _HC13_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _DCFG>>

pub fn devspd(&mut self) -> DEVSPD_W<'_>

Bits 0:1 - Device Speed

pub fn nzstsouthshk(&mut self) -> NZSTSOUTHSHK_W<'_>

Bit 2 - Non-Zero-Length Status OUT Handshake

pub fn ena32khzsusp(&mut self) -> ENA32KHZSUSP_W<'_>

Bit 3 - Enable 32 kHz Suspend Mode

pub fn devaddr(&mut self) -> DEVADDR_W<'_>

Bits 4:10 - Device Address

pub fn perfrint(&mut self) -> PERFRINT_W<'_>

Bits 11:12 - Periodic Frame Interval

pub fn endevoutnak(&mut self) -> ENDEVOUTNAK_W<'_>

Bit 13 - Enable Device OUT NAK

pub fn xcvrdly(&mut self) -> XCVRDLY_W<'_>

Bit 14

pub fn erraticintmsk(&mut self) -> ERRATICINTMSK_W<'_>

Bit 15

pub fn resvalid(&mut self) -> RESVALID_W<'_>

Bits 26:31 - Resume Validation Period

impl W<u32, Reg<u32, _DCTL>>

pub fn rmtwkupsig(&mut self) -> RMTWKUPSIG_W<'_>

Bit 0 - Remote Wakeup Signaling

pub fn sftdiscon(&mut self) -> SFTDISCON_W<'_>

Bit 1 - Soft Disconnect

pub fn tstctl(&mut self) -> TSTCTL_W<'_>

Bits 4:6 - Test Control

pub fn sgnpinnak(&mut self) -> SGNPINNAK_W<'_>

Bit 7 - Set Global Non-periodic IN NAK

pub fn cgnpinnak(&mut self) -> CGNPINNAK_W<'_>

Bit 8 - Clear Global Non-periodic IN NAK

pub fn sgoutnak(&mut self) -> SGOUTNAK_W<'_>

Bit 9 - Set Global OUT NAK

pub fn cgoutnak(&mut self) -> CGOUTNAK_W<'_>

Bit 10 - Clear Global OUT NAK

pub fn pwronprgdone(&mut self) -> PWRONPRGDONE_W<'_>

Bit 11 - Power-On Programming Done

pub fn ignrfrmnum(&mut self) -> IGNRFRMNUM_W<'_>

Bit 15 - Ignore Frame number For Isochronous End points

pub fn nakonbble(&mut self) -> NAKONBBLE_W<'_>

Bit 16 - NAK on Babble Error

impl W<u32, Reg<u32, _DIEPMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Interrupt Mask

pub fn epdisbldmsk(&mut self) -> EPDISBLDMSK_W<'_>

Bit 1 - Endpoint Disabled Interrupt Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn timeoutmsk(&mut self) -> TIMEOUTMSK_W<'_>

Bit 3 - Timeout Condition Mask

pub fn intkntxfempmsk(&mut self) -> INTKNTXFEMPMSK_W<'_>

Bit 4 - IN Token Received When TxFIFO Empty Mask

pub fn intknepmismsk(&mut self) -> INTKNEPMISMSK_W<'_>

Bit 5 - IN Token received with EP Mismatch Mask

pub fn inepnakeffmsk(&mut self) -> INEPNAKEFFMSK_W<'_>

Bit 6 - IN Endpoint NAK Effective Mask

pub fn txfifoundrnmsk(&mut self) -> TXFIFOUNDRNMSK_W<'_>

Bit 8 - Fifo Underrun Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 13 - NAK interrupt Mask

impl W<u32, Reg<u32, _DOEPMSK>>

pub fn xfercomplmsk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Interrupt Mask

pub fn epdisbldmsk(&mut self) -> EPDISBLDMSK_W<'_>

Bit 1 - Endpoint Disabled Interrupt Mask

pub fn ahberrmsk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error

pub fn setupmsk(&mut self) -> SETUPMSK_W<'_>

Bit 3 - SETUP Phase Done Mask

pub fn outtknepdismsk(&mut self) -> OUTTKNEPDISMSK_W<'_>

Bit 4 - OUT Token Received when Endpoint Disabled Mask

pub fn stsphsercvdmsk(&mut self) -> STSPHSERCVDMSK_W<'_>

Bit 5 - Status Phase Received Mask

pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<'_>

Bit 6 - Back-to-Back SETUP Packets Received Mask

pub fn outpkterrmsk(&mut self) -> OUTPKTERRMSK_W<'_>

Bit 8 - OUT Packet Error Mask

pub fn bbleerrmsk(&mut self) -> BBLEERRMSK_W<'_>

Bit 12 - Babble Error interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 13 - NAK interrupt Mask

impl W<u32, Reg<u32, _DAINTMSK>>

pub fn inepmsk0(&mut self) -> INEPMSK0_W<'_>

Bit 0 - IN Endpoint 0 Interrupt mask Bit

pub fn inepmsk1(&mut self) -> INEPMSK1_W<'_>

Bit 1 - IN Endpoint 1 Interrupt mask Bit

pub fn inepmsk2(&mut self) -> INEPMSK2_W<'_>

Bit 2 - IN Endpoint 2 Interrupt mask Bit

pub fn inepmsk3(&mut self) -> INEPMSK3_W<'_>

Bit 3 - IN Endpoint 3 Interrupt mask Bit

pub fn inepmsk4(&mut self) -> INEPMSK4_W<'_>

Bit 4 - IN Endpoint 4 Interrupt mask Bit

pub fn inepmsk5(&mut self) -> INEPMSK5_W<'_>

Bit 5 - IN Endpoint 5 Interrupt mask Bit

pub fn inepmsk6(&mut self) -> INEPMSK6_W<'_>

Bit 6 - IN Endpoint 6 Interrupt mask Bit

pub fn outepmsk0(&mut self) -> OUTEPMSK0_W<'_>

Bit 16 - OUT Endpoint 0 Interrupt mask Bit

pub fn outepmsk1(&mut self) -> OUTEPMSK1_W<'_>

Bit 17 - OUT Endpoint 1 Interrupt mask Bit

pub fn outepmsk2(&mut self) -> OUTEPMSK2_W<'_>

Bit 18 - OUT Endpoint 2 Interrupt mask Bit

pub fn outepmsk3(&mut self) -> OUTEPMSK3_W<'_>

Bit 19 - OUT Endpoint 3 Interrupt mask Bit

pub fn outepmsk4(&mut self) -> OUTEPMSK4_W<'_>

Bit 20 - OUT Endpoint 4 Interrupt mask Bit

pub fn outepmsk5(&mut self) -> OUTEPMSK5_W<'_>

Bit 21 - OUT Endpoint 5 Interrupt mask Bit

pub fn outepmsk6(&mut self) -> OUTEPMSK6_W<'_>

Bit 22 - OUT Endpoint 6 Interrupt mask Bit

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn dvbusdis(&mut self) -> DVBUSDIS_W<'_>

Bits 0:15 - Device VBUS Discharge Time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbuspulse(&mut self) -> DVBUSPULSE_W<'_>

Bits 0:11 - Device VBUS Pulsing Time

impl W<u32, Reg<u32, _DTHRCTL>>

pub fn nonisothren(&mut self) -> NONISOTHREN_W<'_>

Bit 0 - Non-ISO IN Endpoints Threshold Enable

pub fn isothren(&mut self) -> ISOTHREN_W<'_>

Bit 1 - ISO IN Endpoints Threshold Enable

pub fn txthrlen(&mut self) -> TXTHRLEN_W<'_>

Bits 2:10 - Transmit Threshold Length

pub fn ahbthrratio(&mut self) -> AHBTHRRATIO_W<'_>

Bits 11:12 - AHB Threshold Ratio

pub fn rxthren(&mut self) -> RXTHREN_W<'_>

Bit 16 - Receive Threshold Enable

pub fn rxthrlen(&mut self) -> RXTHRLEN_W<'_>

Bits 17:25 - Receive Threshold Length

pub fn arbprken(&mut self) -> ARBPRKEN_W<'_>

Bit 27 - Arbiter Parking Enable

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn ineptxfempmsk(&mut self) -> INEPTXFEMPMSK_W<'_>

Bits 0:15 - IN EP Tx FIFO Empty Interrupt Mask Bits

impl W<u32, Reg<u32, _DIEP0CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:1 - Maximum Packet Size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DIEP0INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 3 - Timeout Condition

pub fn intkntxfemp(&mut self) -> INTKNTXFEMP_W<'_>

Bit 4 - IN Token Received When TxFIFO is Empty

pub fn intknepmis(&mut self) -> INTKNEPMIS_W<'_>

Bit 5 - IN Token Received with EP Mismatch

pub fn inepnakeff(&mut self) -> INEPNAKEFF_W<'_>

Bit 6 - IN Endpoint NAK Effective

pub fn txfifoundrn(&mut self) -> TXFIFOUNDRN_W<'_>

Bit 8 - Fifo Underrun

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Interrupt

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

impl W<u32, Reg<u32, _DIEP0TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:6 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet Count

impl W<u32, Reg<u32, _DIEP0DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DIEP0_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DIEP0_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 3 - Timeout Condition

pub fn intkntxfemp(&mut self) -> INTKNTXFEMP_W<'_>

Bit 4 - IN Token Received When TxFIFO is Empty

pub fn intknepmis(&mut self) -> INTKNEPMIS_W<'_>

Bit 5 - IN Token Received with EP Mismatch

pub fn inepnakeff(&mut self) -> INEPNAKEFF_W<'_>

Bit 6 - IN Endpoint NAK Effective

pub fn txfifoundrn(&mut self) -> TXFIFOUNDRN_W<'_>

Bit 8 - Fifo Underrun

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Interrupt

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

impl W<u32, Reg<u32, _DIEP0_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn mc(&mut self) -> MC_W<'_>

Bits 29:30 - Multi Count

impl W<u32, Reg<u32, _DIEP0_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DIEP1_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DIEP1_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 3 - Timeout Condition

pub fn intkntxfemp(&mut self) -> INTKNTXFEMP_W<'_>

Bit 4 - IN Token Received When TxFIFO is Empty

pub fn intknepmis(&mut self) -> INTKNEPMIS_W<'_>

Bit 5 - IN Token Received with EP Mismatch

pub fn inepnakeff(&mut self) -> INEPNAKEFF_W<'_>

Bit 6 - IN Endpoint NAK Effective

pub fn txfifoundrn(&mut self) -> TXFIFOUNDRN_W<'_>

Bit 8 - Fifo Underrun

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Interrupt

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

impl W<u32, Reg<u32, _DIEP1_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn mc(&mut self) -> MC_W<'_>

Bits 29:30 - Multi Count

impl W<u32, Reg<u32, _DIEP1_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DIEP2_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DIEP2_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 3 - Timeout Condition

pub fn intkntxfemp(&mut self) -> INTKNTXFEMP_W<'_>

Bit 4 - IN Token Received When TxFIFO is Empty

pub fn intknepmis(&mut self) -> INTKNEPMIS_W<'_>

Bit 5 - IN Token Received with EP Mismatch

pub fn inepnakeff(&mut self) -> INEPNAKEFF_W<'_>

Bit 6 - IN Endpoint NAK Effective

pub fn txfifoundrn(&mut self) -> TXFIFOUNDRN_W<'_>

Bit 8 - Fifo Underrun

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Interrupt

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

impl W<u32, Reg<u32, _DIEP2_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn mc(&mut self) -> MC_W<'_>

Bits 29:30 - Multi Count

impl W<u32, Reg<u32, _DIEP2_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DIEP3_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DIEP3_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 3 - Timeout Condition

pub fn intkntxfemp(&mut self) -> INTKNTXFEMP_W<'_>

Bit 4 - IN Token Received When TxFIFO is Empty

pub fn intknepmis(&mut self) -> INTKNEPMIS_W<'_>

Bit 5 - IN Token Received with EP Mismatch

pub fn inepnakeff(&mut self) -> INEPNAKEFF_W<'_>

Bit 6 - IN Endpoint NAK Effective

pub fn txfifoundrn(&mut self) -> TXFIFOUNDRN_W<'_>

Bit 8 - Fifo Underrun

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Interrupt

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

impl W<u32, Reg<u32, _DIEP3_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn mc(&mut self) -> MC_W<'_>

Bits 29:30 - Multi Count

impl W<u32, Reg<u32, _DIEP3_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DIEP4_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DIEP4_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 3 - Timeout Condition

pub fn intkntxfemp(&mut self) -> INTKNTXFEMP_W<'_>

Bit 4 - IN Token Received When TxFIFO is Empty

pub fn intknepmis(&mut self) -> INTKNEPMIS_W<'_>

Bit 5 - IN Token Received with EP Mismatch

pub fn inepnakeff(&mut self) -> INEPNAKEFF_W<'_>

Bit 6 - IN Endpoint NAK Effective

pub fn txfifoundrn(&mut self) -> TXFIFOUNDRN_W<'_>

Bit 8 - Fifo Underrun

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Interrupt

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

impl W<u32, Reg<u32, _DIEP4_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn mc(&mut self) -> MC_W<'_>

Bits 29:30 - Multi Count

impl W<u32, Reg<u32, _DIEP4_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DIEP5_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DIEP5_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 3 - Timeout Condition

pub fn intkntxfemp(&mut self) -> INTKNTXFEMP_W<'_>

Bit 4 - IN Token Received When TxFIFO is Empty

pub fn intknepmis(&mut self) -> INTKNEPMIS_W<'_>

Bit 5 - IN Token Received with EP Mismatch

pub fn inepnakeff(&mut self) -> INEPNAKEFF_W<'_>

Bit 6 - IN Endpoint NAK Effective

pub fn txfifoundrn(&mut self) -> TXFIFOUNDRN_W<'_>

Bit 8 - Fifo Underrun

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Interrupt

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

impl W<u32, Reg<u32, _DIEP5_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn mc(&mut self) -> MC_W<'_>

Bits 29:30 - Multi Count

impl W<u32, Reg<u32, _DIEP5_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DOEP0CTL>>

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - Handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DOEP0INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 3 - Setup Phase Done

pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W<'_>

Bit 4 - OUT Token Received When Endpoint Disabled

pub fn stsphsercvd(&mut self) -> STSPHSERCVD_W<'_>

Bit 5 - Status Phase Received For Control Write

pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<'_>

Bit 6 - Back-to-Back SETUP Packets Received

pub fn outpkterr(&mut self) -> OUTPKTERR_W<'_>

Bit 8 - OUT Packet Error

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - NAK Interrupt

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

pub fn stuppktrcvd(&mut self) -> STUPPKTRCVD_W<'_>

Bit 15

impl W<u32, Reg<u32, _DOEP0TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:6 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bit 19 - Packet Count

pub fn supcnt(&mut self) -> SUPCNT_W<'_>

Bits 29:30 - SETUP Packet Count

impl W<u32, Reg<u32, _DOEP0DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DOEP0_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DOEP0_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 3 - Setup Phase Done

pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W<'_>

Bit 4 - OUT Token Received When Endpoint Disabled

pub fn stsphsercvd(&mut self) -> STSPHSERCVD_W<'_>

Bit 5 - Status Phase Received For Control Write

pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<'_>

Bit 6 - Back-to-Back SETUP Packets Received

pub fn outpkterr(&mut self) -> OUTPKTERR_W<'_>

Bit 8 - OUT Packet Error

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Error

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

pub fn stuppktrcvd(&mut self) -> STUPPKTRCVD_W<'_>

Bit 15

impl W<u32, Reg<u32, _DOEP0_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

impl W<u32, Reg<u32, _DOEP0_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DOEP1_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DOEP1_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 3 - Setup Phase Done

pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W<'_>

Bit 4 - OUT Token Received When Endpoint Disabled

pub fn stsphsercvd(&mut self) -> STSPHSERCVD_W<'_>

Bit 5 - Status Phase Received For Control Write

pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<'_>

Bit 6 - Back-to-Back SETUP Packets Received

pub fn outpkterr(&mut self) -> OUTPKTERR_W<'_>

Bit 8 - OUT Packet Error

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Error

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

pub fn stuppktrcvd(&mut self) -> STUPPKTRCVD_W<'_>

Bit 15

impl W<u32, Reg<u32, _DOEP1_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

impl W<u32, Reg<u32, _DOEP1_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DOEP2_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DOEP2_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 3 - Setup Phase Done

pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W<'_>

Bit 4 - OUT Token Received When Endpoint Disabled

pub fn stsphsercvd(&mut self) -> STSPHSERCVD_W<'_>

Bit 5 - Status Phase Received For Control Write

pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<'_>

Bit 6 - Back-to-Back SETUP Packets Received

pub fn outpkterr(&mut self) -> OUTPKTERR_W<'_>

Bit 8 - OUT Packet Error

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Error

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

pub fn stuppktrcvd(&mut self) -> STUPPKTRCVD_W<'_>

Bit 15

impl W<u32, Reg<u32, _DOEP2_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

impl W<u32, Reg<u32, _DOEP2_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DOEP3_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DOEP3_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 3 - Setup Phase Done

pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W<'_>

Bit 4 - OUT Token Received When Endpoint Disabled

pub fn stsphsercvd(&mut self) -> STSPHSERCVD_W<'_>

Bit 5 - Status Phase Received For Control Write

pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<'_>

Bit 6 - Back-to-Back SETUP Packets Received

pub fn outpkterr(&mut self) -> OUTPKTERR_W<'_>

Bit 8 - OUT Packet Error

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Error

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

pub fn stuppktrcvd(&mut self) -> STUPPKTRCVD_W<'_>

Bit 15

impl W<u32, Reg<u32, _DOEP3_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

impl W<u32, Reg<u32, _DOEP3_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DOEP4_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DOEP4_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 3 - Setup Phase Done

pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W<'_>

Bit 4 - OUT Token Received When Endpoint Disabled

pub fn stsphsercvd(&mut self) -> STSPHSERCVD_W<'_>

Bit 5 - Status Phase Received For Control Write

pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<'_>

Bit 6 - Back-to-Back SETUP Packets Received

pub fn outpkterr(&mut self) -> OUTPKTERR_W<'_>

Bit 8 - OUT Packet Error

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Error

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

pub fn stuppktrcvd(&mut self) -> STUPPKTRCVD_W<'_>

Bit 15

impl W<u32, Reg<u32, _DOEP4_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

impl W<u32, Reg<u32, _DOEP4_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DOEP5_CTL>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbactep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<'_>

Bit 28 - Set DATA0 PID / Even Frame

pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<'_>

Bit 29 - Set DATA1 PID / Odd Frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DOEP5_INT>>

pub fn xfercompl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 3 - Setup Phase Done

pub fn outtknepdis(&mut self) -> OUTTKNEPDIS_W<'_>

Bit 4 - OUT Token Received When Endpoint Disabled

pub fn stsphsercvd(&mut self) -> STSPHSERCVD_W<'_>

Bit 5 - Status Phase Received For Control Write

pub fn back2backsetup(&mut self) -> BACK2BACKSETUP_W<'_>

Bit 6 - Back-to-Back SETUP Packets Received

pub fn outpkterr(&mut self) -> OUTPKTERR_W<'_>

Bit 8 - OUT Packet Error

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Drop Status

pub fn bbleerr(&mut self) -> BBLEERR_W<'_>

Bit 12 - Babble Error

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK Interrupt

pub fn stuppktrcvd(&mut self) -> STUPPKTRCVD_W<'_>

Bit 15

impl W<u32, Reg<u32, _DOEP5_TSIZ>>

pub fn xfersize(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

impl W<u32, Reg<u32, _DOEP5_DMAADDR>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PCGCCTL>>

pub fn stoppclk(&mut self) -> STOPPCLK_W<'_>

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate HCLK

pub fn pwrclmp(&mut self) -> PWRCLMP_W<'_>

Bit 2 - Power Clamp

pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W<'_>

Bit 3 - Reset Power-Down Modules

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Current DAC Enable

pub fn cursink(&mut self) -> CURSINK_W<'_>

Bit 1 - Current Sink Enable

pub fn minouttrans(&mut self) -> MINOUTTRANS_W<'_>

Bit 2 - Minimum Output Transition Enable

pub fn aportouten(&mut self) -> APORTOUTEN_W<'_>

Bit 3 - APORT Output Enable

pub fn aportoutsel(&mut self) -> APORTOUTSEL_W<'_>

Bits 4:11 - APORT Output Select

pub fn pwrsel(&mut self) -> PWRSEL_W<'_>

Bit 12 - Power Select

pub fn em2delay(&mut self) -> EM2DELAY_W<'_>

Bit 13 - EM2 Delay

pub fn aportmasterdis(&mut self) -> APORTMASTERDIS_W<'_>

Bit 14 - APORT Bus Master Disable

pub fn aportoutenprs(&mut self) -> APORTOUTENPRS_W<'_>

Bit 16 - PRS Controlled APORT Output Enable

pub fn mainouten(&mut self) -> MAINOUTEN_W<'_>

Bit 18 - Output Enable

pub fn mainoutenprs(&mut self) -> MAINOUTENPRS_W<'_>

Bit 19 - PRS Controlled Main Pad Output Enable

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 20:24 - IDAC Output Enable PRS Channel Select

impl W<u32, Reg<u32, _CURPROG>>

pub fn rangesel(&mut self) -> RANGESEL_W<'_>

Bits 0:1 - Current Range Select

pub fn stepsel(&mut self) -> STEPSEL_W<'_>

Bits 8:12 - Current Step Size Select

pub fn tuning(&mut self) -> TUNING_W<'_>

Bits 16:23 - Tune the Current to Given Accuracy

impl W<u32, Reg<u32, _DUTYCONFIG>>

pub fn em2dutycycledis(&mut self) -> EM2DUTYCYCLEDIS_W<'_>

Bit 1 - Duty Cycle Enable

impl W<u32, Reg<u32, _IFS>>

pub fn curstable(&mut self) -> CURSTABLE_W<'_>

Bit 0 - Set CURSTABLE Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 1 - Set APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn curstable(&mut self) -> CURSTABLE_W<'_>

Bit 0 - Clear CURSTABLE Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 1 - Clear APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn curstable(&mut self) -> CURSTABLE_W<'_>

Bit 0 - CURSTABLE Interrupt Enable

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 1 - APORTCONFLICT Interrupt Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 1 - CSEN Enable

pub fn cmppol(&mut self) -> CMPPOL_W<'_>

Bit 2 - CSEN Digital Comparator Polarity Select

pub fn cm(&mut self) -> CM_W<'_>

Bits 4:5 - CSEN Conversion Mode Select

pub fn sarcr(&mut self) -> SARCR_W<'_>

Bits 8:9 - SAR Conversion Resolution.

pub fn acu(&mut self) -> ACU_W<'_>

Bits 12:14 - CSEN Accumulator Mode Select

pub fn mcen(&mut self) -> MCEN_W<'_>

Bit 15 - CSEN Multiple Channel Enable

pub fn stm(&mut self) -> STM_W<'_>

Bits 16:17 - Start Trigger Select

pub fn cmpen(&mut self) -> CMPEN_W<'_>

Bit 18 - CSEN Digital Comparator Enable

pub fn drsf(&mut self) -> DRSF_W<'_>

Bit 19 - CSEN Disable Right-Shift

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 20 - CSEN DMA Enable Bit

pub fn convsel(&mut self) -> CONVSEL_W<'_>

Bit 21 - CSEN Converter Select

pub fn chopen(&mut self) -> CHOPEN_W<'_>

Bit 22 - CSEN Chop Enable

pub fn autognd(&mut self) -> AUTOGND_W<'_>

Bit 23 - CSEN Automatic Ground Enable

pub fn mxuc(&mut self) -> MXUC_W<'_>

Bit 24 - CSEN Mux Disconnect

pub fn emacmpen(&mut self) -> EMACMPEN_W<'_>

Bit 25 - Greater and Less Than Comparison Using the Exponential Moving Average (EMA) is Enabled

pub fn warmupmode(&mut self) -> WARMUPMODE_W<'_>

Bit 26 - Select Warmup Mode for CSEN

pub fn localsens(&mut self) -> LOCALSENS_W<'_>

Bit 27 - Local Sensing Enable

pub fn cpaccuracy(&mut self) -> CPACCURACY_W<'_>

Bit 28 - Charge Pump Accuracy

impl W<u32, Reg<u32, _TIMCTRL>>

pub fn pcpresc(&mut self) -> PCPRESC_W<'_>

Bits 0:2 - Period Counter Prescaler

pub fn pctop(&mut self) -> PCTOP_W<'_>

Bits 8:15 - Period Counter Top Value

pub fn warmupcnt(&mut self) -> WARMUPCNT_W<'_>

Bits 16:17 - Warmup Period Counter

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Software-Triggered Conversions

impl W<u32, Reg<u32, _PRSSEL>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 0:4 - PRS Channel Select

impl W<u32, Reg<u32, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Output Data

impl W<u32, Reg<u32, _SCANMASK0>>

pub fn scaninputen(&mut self) -> SCANINPUTEN_W<'_>

Bits 0:31 - Scan Channel Mask

impl W<u32, Reg<u32, _SCANINPUTSEL0>>

pub fn input0to7sel(&mut self) -> INPUT0TO7SEL_W<'_>

Bits 0:3 - CSEN_INPUT0-7 Select

pub fn input8to15sel(&mut self) -> INPUT8TO15SEL_W<'_>

Bits 8:11 - CSEN_INPUT8-15 Select

pub fn input16to23sel(&mut self) -> INPUT16TO23SEL_W<'_>

Bits 16:19 - CSEN_INPUT16-23 Select

pub fn input24to31sel(&mut self) -> INPUT24TO31SEL_W<'_>

Bits 24:27 - CSEN_INPUT24-31 Select

impl W<u32, Reg<u32, _SCANMASK1>>

pub fn scaninputen(&mut self) -> SCANINPUTEN_W<'_>

Bits 0:31 - Scan Channel Mask.

impl W<u32, Reg<u32, _SCANINPUTSEL1>>

pub fn input32to39sel(&mut self) -> INPUT32TO39SEL_W<'_>

Bits 0:3 - CSEN_INPUT32-39 Select

pub fn input40to47sel(&mut self) -> INPUT40TO47SEL_W<'_>

Bits 8:11 - CSEN_INPUT40-47 Select

pub fn input48to55sel(&mut self) -> INPUT48TO55SEL_W<'_>

Bits 16:19 - CSEN_INPUT48-55 Select

pub fn input56to63sel(&mut self) -> INPUT56TO63SEL_W<'_>

Bits 24:27 - CSEN_INPUT56-63 Select

impl W<u32, Reg<u32, _CMPTHR>>

pub fn cmpthr(&mut self) -> CMPTHR_W<'_>

Bits 0:15 - Comparator Threshold.

impl W<u32, Reg<u32, _EMA>>

pub fn ema(&mut self) -> EMA_W<'_>

Bits 0:21 - Calculated Exponential Moving Average

impl W<u32, Reg<u32, _EMACTRL>>

pub fn emasample(&mut self) -> EMASAMPLE_W<'_>

Bits 0:2 - EMA Sample Weight

impl W<u32, Reg<u32, _SINGLECTRL>>

pub fn singlesel(&mut self) -> SINGLESEL_W<'_>

Bits 4:10 - Single Channel Input Select

impl W<u32, Reg<u32, _DMBASELINE>>

pub fn baselineup(&mut self) -> BASELINEUP_W<'_>

Bits 0:15 - Delta Modulator Integrator Initial Value

pub fn baselinedn(&mut self) -> BASELINEDN_W<'_>

Bits 16:31 - Delta Modulator Integrator Initial Value

impl W<u32, Reg<u32, _DMCFG>>

pub fn dmg(&mut self) -> DMG_W<'_>

Bits 0:7 - Delta Modulator Gain Step

pub fn dmr(&mut self) -> DMR_W<'_>

Bits 8:11 - Delta Modulator Gain Reduction Interval

pub fn dmcr(&mut self) -> DMCR_W<'_>

Bits 16:19 - Delta Modulator Conversion Rate

pub fn crmode(&mut self) -> CRMODE_W<'_>

Bits 20:21 - Delta Modulator Conversion Resolution.

pub fn dmgrdis(&mut self) -> DMGRDIS_W<'_>

Bit 28 - Delta Modulation Gain Step Reduction Disable

impl W<u32, Reg<u32, _ANACTRL>>

pub fn irefprog(&mut self) -> IREFPROG_W<'_>

Bits 4:6 - Reference Current Control.

pub fn idacirefs(&mut self) -> IDACIREFS_W<'_>

Bits 8:10 - Current DAC and Reference Current Scale

pub fn trstprog(&mut self) -> TRSTPROG_W<'_>

Bits 20:22 - Reset Timing

impl W<u32, Reg<u32, _IFS>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bit 0 - Set CMP Interrupt Flag

pub fn conv(&mut self) -> CONV_W<'_>

Bit 1 - Set CONV Interrupt Flag

pub fn eos(&mut self) -> EOS_W<'_>

Bit 2 - Set EOS Interrupt Flag

pub fn dmaof(&mut self) -> DMAOF_W<'_>

Bit 3 - Set DMAOF Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 4 - Set APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bit 0 - Clear CMP Interrupt Flag

pub fn conv(&mut self) -> CONV_W<'_>

Bit 1 - Clear CONV Interrupt Flag

pub fn eos(&mut self) -> EOS_W<'_>

Bit 2 - Clear EOS Interrupt Flag

pub fn dmaof(&mut self) -> DMAOF_W<'_>

Bit 3 - Clear DMAOF Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 4 - Clear APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bit 0 - CMP Interrupt Enable

pub fn conv(&mut self) -> CONV_W<'_>

Bit 1 - CONV Interrupt Enable

pub fn eos(&mut self) -> EOS_W<'_>

Bit 2 - EOS Interrupt Enable

pub fn dmaof(&mut self) -> DMAOF_W<'_>

Bit 3 - DMAOF Interrupt Enable

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 4 - APORTCONFLICT Interrupt Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - LCD Enable

pub fn udctrl(&mut self) -> UDCTRL_W<'_>

Bits 1:2 - Update Data Control

pub fn dsc(&mut self) -> DSC_W<'_>

Bit 23 - Direct Segment Control

impl W<u32, Reg<u32, _DISPCTRL>>

pub fn mux(&mut self) -> MUX_W<'_>

Bits 0:2 - Mux Configuration

pub fn wave(&mut self) -> WAVE_W<'_>

Bit 4 - Waveform Selection

pub fn contrast(&mut self) -> CONTRAST_W<'_>

Bits 8:13 - Contrast Control

pub fn chgrdst(&mut self) -> CHGRDST_W<'_>

Bits 20:22 - Charge Redistribution Cycles

pub fn bias(&mut self) -> BIAS_W<'_>

Bits 24:25 - Bias Configuration

pub fn mode(&mut self) -> MODE_W<'_>

Bits 28:29 - Mode Setting

impl W<u32, Reg<u32, _SEGEN>>

pub fn segen(&mut self) -> SEGEN_W<'_>

Bits 0:31 - Segment Enable

impl W<u32, Reg<u32, _BACTRL>>

pub fn blinken(&mut self) -> BLINKEN_W<'_>

Bit 0 - Blink Enable

pub fn blank(&mut self) -> BLANK_W<'_>

Bit 1 - Blank Display

pub fn aen(&mut self) -> AEN_W<'_>

Bit 2 - Animation Enable

pub fn aregasc(&mut self) -> AREGASC_W<'_>

Bits 3:4 - Animate Register a Shift Control

pub fn aregbsc(&mut self) -> AREGBSC_W<'_>

Bits 5:6 - Animate Register B Shift Control

pub fn alogsel(&mut self) -> ALOGSEL_W<'_>

Bit 7 - Animate Logic Function Select

pub fn fcen(&mut self) -> FCEN_W<'_>

Bit 8 - Frame Counter Enable

pub fn fcpresc(&mut self) -> FCPRESC_W<'_>

Bits 16:17 - Frame Counter Prescaler

pub fn fctop(&mut self) -> FCTOP_W<'_>

Bits 18:23 - Frame Counter Top Value

pub fn aloc(&mut self) -> ALOC_W<'_>

Bit 28 - Animation Location

impl W<u32, Reg<u32, _AREGA>>

pub fn arega(&mut self) -> AREGA_W<'_>

Bits 0:7 - Animation Register a Data

impl W<u32, Reg<u32, _AREGB>>

pub fn aregb(&mut self) -> AREGB_W<'_>

Bits 0:7 - Animation Register B Data

impl W<u32, Reg<u32, _IFS>>

pub fn fc(&mut self) -> FC_W<'_>

Bit 0 - Frame Counter Interrupt Flag Set

impl W<u32, Reg<u32, _IFC>>

pub fn fc(&mut self) -> FC_W<'_>

Bit 0 - Frame Counter Interrupt Flag Clear

impl W<u32, Reg<u32, _IEN>>

pub fn fc(&mut self) -> FC_W<'_>

Bit 0 - Frame Counter Interrupt Enable

impl W<u32, Reg<u32, _BIASCTRL>>

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 0:2 - SPEED Adjustment

pub fn bufdrv(&mut self) -> BUFDRV_W<'_>

Bits 4:7 - Buffer Drive Strength

pub fn bufbias(&mut self) -> BUFBIAS_W<'_>

Bits 10:12 - Buffer Bias Setting

impl W<u32, Reg<u32, _SEGD0L>>

pub fn segd0l(&mut self) -> SEGD0L_W<'_>

Bits 0:31 - COM0 Segment Data Low

impl W<u32, Reg<u32, _SEGD1L>>

pub fn segd1l(&mut self) -> SEGD1L_W<'_>

Bits 0:31 - COM1 Segment Data Low

impl W<u32, Reg<u32, _SEGD2L>>

pub fn segd2l(&mut self) -> SEGD2L_W<'_>

Bits 0:31 - COM2 Segment Data Low

impl W<u32, Reg<u32, _SEGD3L>>

pub fn segd3l(&mut self) -> SEGD3L_W<'_>

Bits 0:31 - COM3 Segment Data Low

impl W<u32, Reg<u32, _SEGD0H>>

pub fn segd0h(&mut self) -> SEGD0H_W<'_>

Bits 0:7 - COM0 Segment Data High

impl W<u32, Reg<u32, _SEGD1H>>

pub fn segd1h(&mut self) -> SEGD1H_W<'_>

Bits 0:7 - COM1 Segment Data High

impl W<u32, Reg<u32, _SEGD2H>>

pub fn segd2h(&mut self) -> SEGD2H_W<'_>

Bits 0:7 - COM2 Segment Data High

impl W<u32, Reg<u32, _SEGD3H>>

pub fn segd3h(&mut self) -> SEGD3H_W<'_>

Bits 0:7 - COM3 Segment Data High

impl W<u32, Reg<u32, _SEGD4L>>

pub fn segd4l(&mut self) -> SEGD4L_W<'_>

Bits 0:31 - COM4 Segment Data

impl W<u32, Reg<u32, _SEGD5L>>

pub fn segd5l(&mut self) -> SEGD5L_W<'_>

Bits 0:31 - COM5 Segment Data

impl W<u32, Reg<u32, _SEGD6L>>

pub fn segd6l(&mut self) -> SEGD6L_W<'_>

Bits 0:31 - COM6 Segment Data

impl W<u32, Reg<u32, _SEGD7L>>

pub fn segd7l(&mut self) -> SEGD7L_W<'_>

Bits 0:31 - COM7 Segment Data

impl W<u32, Reg<u32, _SEGD4H>>

pub fn segd4h(&mut self) -> SEGD4H_W<'_>

Bits 0:7 - COM0 Segment Data High

impl W<u32, Reg<u32, _SEGD5H>>

pub fn segd5h(&mut self) -> SEGD5H_W<'_>

Bits 0:7 - COM1 Segment Data High

impl W<u32, Reg<u32, _SEGD6H>>

pub fn segd6h(&mut self) -> SEGD6H_W<'_>

Bits 0:7 - COM2 Segment Data High

impl W<u32, Reg<u32, _SEGD7H>>

pub fn segd7h(&mut self) -> SEGD7H_W<'_>

Bits 0:7 - COM3 Segment Data High

impl W<u32, Reg<u32, _FREEZE>>

pub fn regfreeze(&mut self) -> REGFREEZE_W<'_>

Bit 0 - Register Update Freeze

pub fn lcdgate(&mut self) -> LCDGATE_W<'_>

Bit 1 - LCD Gate

impl W<u32, Reg<u32, _FRAMERATE>>

pub fn frdiv(&mut self) -> FRDIV_W<'_>

Bits 0:8 - Frame Rate Divider

impl W<u32, Reg<u32, _SEGEN2>>

pub fn segen2(&mut self) -> SEGEN2_W<'_>

Bits 0:7 - Segment Enable (second Group)

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - RTC Enable

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 1 - Debug Mode Run Enable

pub fn comp0top(&mut self) -> COMP0TOP_W<'_>

Bit 2 - Compare Channel 0 is Top Value

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:23 - Counter Value

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn comp(&mut self) -> COMP_W<'_>

Bits 1:6 - Set COMP Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn comp(&mut self) -> COMP_W<'_>

Bits 1:6 - Clear COMP Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn comp(&mut self) -> COMP_W<'_>

Bits 1:6 - COMP Interrupt Enable

impl W<u32, Reg<u32, _COMPA_COMP>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:23 - Compare Value

impl W<u32, Reg<u32, _COMPB_COMP>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:23 - Compare Value

impl W<u32, Reg<u32, _COMPC_COMP>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:23 - Compare Value

impl W<u32, Reg<u32, _COMPD_COMP>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:23 - Compare Value

impl W<u32, Reg<u32, _COMPE_COMP>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:23 - Compare Value

impl W<u32, Reg<u32, _COMPF_COMP>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:23 - Compare Value

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - RTCC Enable

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 2 - Debug Mode Run Enable

pub fn preccv0top(&mut self) -> PRECCV0TOP_W<'_>

Bit 4 - Pre-counter CCV0 Top Value Enable

pub fn ccv1top(&mut self) -> CCV1TOP_W<'_>

Bit 5 - CCV1 Top Value Enable

pub fn cntpresc(&mut self) -> CNTPRESC_W<'_>

Bits 8:11 - Counter Prescaler Value

pub fn cnttick(&mut self) -> CNTTICK_W<'_>

Bit 12 - Counter Prescaler Mode

pub fn bumodetsen(&mut self) -> BUMODETSEN_W<'_>

Bit 14 - Backup Mode Timestamp Enable

pub fn oscfdeten(&mut self) -> OSCFDETEN_W<'_>

Bit 15 - Oscillator Failure Detection Enable

pub fn cntmode(&mut self) -> CNTMODE_W<'_>

Bit 16 - Main Counter Mode

pub fn lyearcorrdis(&mut self) -> LYEARCORRDIS_W<'_>

Bit 17 - Leap Year Correction Disabled

impl W<u32, Reg<u32, _PRECNT>>

pub fn precnt(&mut self) -> PRECNT_W<'_>

Bits 0:14 - Pre-Counter Value

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _TIME>>

pub fn secu(&mut self) -> SECU_W<'_>

Bits 0:3 - Seconds, Units

pub fn sect(&mut self) -> SECT_W<'_>

Bits 4:6 - Seconds, Tens

pub fn minu(&mut self) -> MINU_W<'_>

Bits 8:11 - Minutes, Units

pub fn mint(&mut self) -> MINT_W<'_>

Bits 12:14 - Minutes, Tens

pub fn houru(&mut self) -> HOURU_W<'_>

Bits 16:19 - Hours, Units

pub fn hourt(&mut self) -> HOURT_W<'_>

Bits 20:21 - Hours, Tens

impl W<u32, Reg<u32, _DATE>>

pub fn dayomu(&mut self) -> DAYOMU_W<'_>

Bits 0:3 - Day of Month, Units

pub fn dayomt(&mut self) -> DAYOMT_W<'_>

Bits 4:5 - Day of Month, Tens

pub fn monthu(&mut self) -> MONTHU_W<'_>

Bits 8:11 - Month, Units

pub fn montht(&mut self) -> MONTHT_W<'_>

Bit 12 - Month, Tens

pub fn yearu(&mut self) -> YEARU_W<'_>

Bits 16:19 - Year, Units

pub fn yeart(&mut self) -> YEART_W<'_>

Bits 20:23 - Year, Tens

pub fn dayow(&mut self) -> DAYOW_W<'_>

Bits 24:26 - Day of Week

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 1 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 2 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 3 - Set CC2 Interrupt Flag

pub fn oscfail(&mut self) -> OSCFAIL_W<'_>

Bit 4 - Set OSCFAIL Interrupt Flag

pub fn cnttick(&mut self) -> CNTTICK_W<'_>

Bit 5 - Set CNTTICK Interrupt Flag

pub fn mintick(&mut self) -> MINTICK_W<'_>

Bit 6 - Set MINTICK Interrupt Flag

pub fn hourtick(&mut self) -> HOURTICK_W<'_>

Bit 7 - Set HOURTICK Interrupt Flag

pub fn daytick(&mut self) -> DAYTICK_W<'_>

Bit 8 - Set DAYTICK Interrupt Flag

pub fn dayowof(&mut self) -> DAYOWOF_W<'_>

Bit 9 - Set DAYOWOF Interrupt Flag

pub fn monthtick(&mut self) -> MONTHTICK_W<'_>

Bit 10 - Set MONTHTICK Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 1 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 2 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 3 - Clear CC2 Interrupt Flag

pub fn oscfail(&mut self) -> OSCFAIL_W<'_>

Bit 4 - Clear OSCFAIL Interrupt Flag

pub fn cnttick(&mut self) -> CNTTICK_W<'_>

Bit 5 - Clear CNTTICK Interrupt Flag

pub fn mintick(&mut self) -> MINTICK_W<'_>

Bit 6 - Clear MINTICK Interrupt Flag

pub fn hourtick(&mut self) -> HOURTICK_W<'_>

Bit 7 - Clear HOURTICK Interrupt Flag

pub fn daytick(&mut self) -> DAYTICK_W<'_>

Bit 8 - Clear DAYTICK Interrupt Flag

pub fn dayowof(&mut self) -> DAYOWOF_W<'_>

Bit 9 - Clear DAYOWOF Interrupt Flag

pub fn monthtick(&mut self) -> MONTHTICK_W<'_>

Bit 10 - Clear MONTHTICK Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 1 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 2 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 3 - CC2 Interrupt Enable

pub fn oscfail(&mut self) -> OSCFAIL_W<'_>

Bit 4 - OSCFAIL Interrupt Enable

pub fn cnttick(&mut self) -> CNTTICK_W<'_>

Bit 5 - CNTTICK Interrupt Enable

pub fn mintick(&mut self) -> MINTICK_W<'_>

Bit 6 - MINTICK Interrupt Enable

pub fn hourtick(&mut self) -> HOURTICK_W<'_>

Bit 7 - HOURTICK Interrupt Enable

pub fn daytick(&mut self) -> DAYTICK_W<'_>

Bit 8 - DAYTICK Interrupt Enable

pub fn dayowof(&mut self) -> DAYOWOF_W<'_>

Bit 9 - DAYOWOF Interrupt Enable

pub fn monthtick(&mut self) -> MONTHTICK_W<'_>

Bit 10 - MONTHTICK Interrupt Enable

impl W<u32, Reg<u32, _CMD>>

pub fn clrstatus(&mut self) -> CLRSTATUS_W<'_>

Bit 0 - Clear RTCC_STATUS Register

impl W<u32, Reg<u32, _POWERDOWN>>

pub fn ram(&mut self) -> RAM_W<'_>

Bit 0 - Retention RAM Power-down

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock Key

impl W<u32, Reg<u32, _EM4WUEN>>

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bit 0 - EM4 Wake-up Enable

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 2:3 - Compare Match Output Action

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 4:5 - Input Capture Edge Select

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 6:10 - Compare/Capture Channel PRS Input Channel Selection

pub fn compbase(&mut self) -> COMPBASE_W<'_>

Bit 11 - Capture Compare Channel Comparison Base

pub fn compmask(&mut self) -> COMPMASK_W<'_>

Bits 12:16 - Capture Compare Channel Comparison Mask

pub fn daycc(&mut self) -> DAYCC_W<'_>

Bit 17 - Day Capture/Compare Selection

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - Capture/Compare Value

impl W<u32, Reg<u32, _CC0_TIME>>

pub fn secu(&mut self) -> SECU_W<'_>

Bits 0:3 - Seconds, Units

pub fn sect(&mut self) -> SECT_W<'_>

Bits 4:6 - Seconds, Tens

pub fn minu(&mut self) -> MINU_W<'_>

Bits 8:11 - Minutes, Units

pub fn mint(&mut self) -> MINT_W<'_>

Bits 12:14 - Minutes, Tens

pub fn houru(&mut self) -> HOURU_W<'_>

Bits 16:19 - Hours, Units

pub fn hourt(&mut self) -> HOURT_W<'_>

Bits 20:21 - Hours, Tens

impl W<u32, Reg<u32, _CC0_DATE>>

pub fn dayu(&mut self) -> DAYU_W<'_>

Bits 0:3 - Day of Month/week, Units

pub fn dayt(&mut self) -> DAYT_W<'_>

Bits 4:5 - Day of Month/week, Tens

pub fn monthu(&mut self) -> MONTHU_W<'_>

Bits 8:11 - Month, Units

pub fn montht(&mut self) -> MONTHT_W<'_>

Bit 12 - Month, Tens

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 2:3 - Compare Match Output Action

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 4:5 - Input Capture Edge Select

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 6:10 - Compare/Capture Channel PRS Input Channel Selection

pub fn compbase(&mut self) -> COMPBASE_W<'_>

Bit 11 - Capture Compare Channel Comparison Base

pub fn compmask(&mut self) -> COMPMASK_W<'_>

Bits 12:16 - Capture Compare Channel Comparison Mask

pub fn daycc(&mut self) -> DAYCC_W<'_>

Bit 17 - Day Capture/Compare Selection

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - Capture/Compare Value

impl W<u32, Reg<u32, _CC1_TIME>>

pub fn secu(&mut self) -> SECU_W<'_>

Bits 0:3 - Seconds, Units

pub fn sect(&mut self) -> SECT_W<'_>

Bits 4:6 - Seconds, Tens

pub fn minu(&mut self) -> MINU_W<'_>

Bits 8:11 - Minutes, Units

pub fn mint(&mut self) -> MINT_W<'_>

Bits 12:14 - Minutes, Tens

pub fn houru(&mut self) -> HOURU_W<'_>

Bits 16:19 - Hours, Units

pub fn hourt(&mut self) -> HOURT_W<'_>

Bits 20:21 - Hours, Tens

impl W<u32, Reg<u32, _CC1_DATE>>

pub fn dayu(&mut self) -> DAYU_W<'_>

Bits 0:3 - Day of Month/week, Units

pub fn dayt(&mut self) -> DAYT_W<'_>

Bits 4:5 - Day of Month/week, Tens

pub fn monthu(&mut self) -> MONTHU_W<'_>

Bits 8:11 - Month, Units

pub fn montht(&mut self) -> MONTHT_W<'_>

Bit 12 - Month, Tens

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 2:3 - Compare Match Output Action

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 4:5 - Input Capture Edge Select

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 6:10 - Compare/Capture Channel PRS Input Channel Selection

pub fn compbase(&mut self) -> COMPBASE_W<'_>

Bit 11 - Capture Compare Channel Comparison Base

pub fn compmask(&mut self) -> COMPMASK_W<'_>

Bits 12:16 - Capture Compare Channel Comparison Mask

pub fn daycc(&mut self) -> DAYCC_W<'_>

Bit 17 - Day Capture/Compare Selection

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - Capture/Compare Value

impl W<u32, Reg<u32, _CC2_TIME>>

pub fn secu(&mut self) -> SECU_W<'_>

Bits 0:3 - Seconds, Units

pub fn sect(&mut self) -> SECT_W<'_>

Bits 4:6 - Seconds, Tens

pub fn minu(&mut self) -> MINU_W<'_>

Bits 8:11 - Minutes, Units

pub fn mint(&mut self) -> MINT_W<'_>

Bits 12:14 - Minutes, Tens

pub fn houru(&mut self) -> HOURU_W<'_>

Bits 16:19 - Hours, Units

pub fn hourt(&mut self) -> HOURT_W<'_>

Bits 20:21 - Hours, Tens

impl W<u32, Reg<u32, _CC2_DATE>>

pub fn dayu(&mut self) -> DAYU_W<'_>

Bits 0:3 - Day of Month/week, Units

pub fn dayt(&mut self) -> DAYT_W<'_>

Bits 4:5 - Day of Month/week, Tens

pub fn monthu(&mut self) -> MONTHU_W<'_>

Bits 8:11 - Month, Units

pub fn montht(&mut self) -> MONTHT_W<'_>

Bit 12 - Month, Tens

impl W<u32, Reg<u32, _RET0_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET1_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET2_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET3_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET4_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET5_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET6_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET7_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET8_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET9_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET10_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET11_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET12_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET13_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET14_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET15_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET16_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET17_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET18_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET19_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET20_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET21_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET22_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET23_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET24_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET25_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET26_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET27_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET28_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET29_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET30_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET31_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Watchdog Timer Enable

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 1 - Debug Mode Run Enable

pub fn em2run(&mut self) -> EM2RUN_W<'_>

Bit 2 - Energy Mode 2 Run Enable

pub fn em3run(&mut self) -> EM3RUN_W<'_>

Bit 3 - Energy Mode 3 Run Enable

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 4 - Configuration Lock

pub fn em4block(&mut self) -> EM4BLOCK_W<'_>

Bit 5 - Energy Mode 4 Block

pub fn swoscblock(&mut self) -> SWOSCBLOCK_W<'_>

Bit 6 - Software Oscillator Disable Block

pub fn persel(&mut self) -> PERSEL_W<'_>

Bits 8:11 - Watchdog Timeout Period Select

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 12:13 - Watchdog Clock Select

pub fn warnsel(&mut self) -> WARNSEL_W<'_>

Bits 16:17 - Watchdog Timeout Period Select

pub fn winsel(&mut self) -> WINSEL_W<'_>

Bits 24:26 - Watchdog Illegal Window Select

pub fn clrsrc(&mut self) -> CLRSRC_W<'_>

Bit 30 - Watchdog Clear Source

pub fn wdogrstdis(&mut self) -> WDOGRSTDIS_W<'_>

Bit 31 - Watchdog Reset Disable

impl W<u32, Reg<u32, _CMD>>

pub fn clear(&mut self) -> CLEAR_W<'_>

Bit 0 - Watchdog Timer Clear

impl W<u32, Reg<u32, _PCH0_PRSCTRL>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 0:4 - PRS Channel PRS Select

pub fn prsmissrsten(&mut self) -> PRSMISSRSTEN_W<'_>

Bit 8 - PRS Missing Event Will Trigger a Watchdog Reset

impl W<u32, Reg<u32, _PCH1_PRSCTRL>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 0:4 - PRS Channel PRS Select

pub fn prsmissrsten(&mut self) -> PRSMISSRSTEN_W<'_>

Bit 8 - PRS Missing Event Will Trigger a Watchdog Reset

impl W<u32, Reg<u32, _IFS>>

pub fn tout(&mut self) -> TOUT_W<'_>

Bit 0 - Set TOUT Interrupt Flag

pub fn warn(&mut self) -> WARN_W<'_>

Bit 1 - Set WARN Interrupt Flag

pub fn win(&mut self) -> WIN_W<'_>

Bit 2 - Set WIN Interrupt Flag

pub fn pem0(&mut self) -> PEM0_W<'_>

Bit 3 - Set PEM0 Interrupt Flag

pub fn pem1(&mut self) -> PEM1_W<'_>

Bit 4 - Set PEM1 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn tout(&mut self) -> TOUT_W<'_>

Bit 0 - Clear TOUT Interrupt Flag

pub fn warn(&mut self) -> WARN_W<'_>

Bit 1 - Clear WARN Interrupt Flag

pub fn win(&mut self) -> WIN_W<'_>

Bit 2 - Clear WIN Interrupt Flag

pub fn pem0(&mut self) -> PEM0_W<'_>

Bit 3 - Clear PEM0 Interrupt Flag

pub fn pem1(&mut self) -> PEM1_W<'_>

Bit 4 - Clear PEM1 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn tout(&mut self) -> TOUT_W<'_>

Bit 0 - TOUT Interrupt Enable

pub fn warn(&mut self) -> WARN_W<'_>

Bit 1 - WARN Interrupt Enable

pub fn win(&mut self) -> WIN_W<'_>

Bit 2 - WIN Interrupt Enable

pub fn pem0(&mut self) -> PEM0_W<'_>

Bit 3 - PEM0 Interrupt Enable

pub fn pem1(&mut self) -> PEM1_W<'_>

Bit 4 - PEM1 Interrupt Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Watchdog Timer Enable

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 1 - Debug Mode Run Enable

pub fn em2run(&mut self) -> EM2RUN_W<'_>

Bit 2 - Energy Mode 2 Run Enable

pub fn em3run(&mut self) -> EM3RUN_W<'_>

Bit 3 - Energy Mode 3 Run Enable

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 4 - Configuration Lock

pub fn em4block(&mut self) -> EM4BLOCK_W<'_>

Bit 5 - Energy Mode 4 Block

pub fn swoscblock(&mut self) -> SWOSCBLOCK_W<'_>

Bit 6 - Software Oscillator Disable Block

pub fn persel(&mut self) -> PERSEL_W<'_>

Bits 8:11 - Watchdog Timeout Period Select

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 12:13 - Watchdog Clock Select

pub fn warnsel(&mut self) -> WARNSEL_W<'_>

Bits 16:17 - Watchdog Timeout Period Select

pub fn winsel(&mut self) -> WINSEL_W<'_>

Bits 24:26 - Watchdog Illegal Window Select

pub fn clrsrc(&mut self) -> CLRSRC_W<'_>

Bit 30 - Watchdog Clear Source

pub fn wdogrstdis(&mut self) -> WDOGRSTDIS_W<'_>

Bit 31 - Watchdog Reset Disable

impl W<u32, Reg<u32, _CMD>>

pub fn clear(&mut self) -> CLEAR_W<'_>

Bit 0 - Watchdog Timer Clear

impl W<u32, Reg<u32, _PCH0_PRSCTRL>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 0:4 - PRS Channel PRS Select

pub fn prsmissrsten(&mut self) -> PRSMISSRSTEN_W<'_>

Bit 8 - PRS Missing Event Will Trigger a Watchdog Reset

impl W<u32, Reg<u32, _PCH1_PRSCTRL>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 0:4 - PRS Channel PRS Select

pub fn prsmissrsten(&mut self) -> PRSMISSRSTEN_W<'_>

Bit 8 - PRS Missing Event Will Trigger a Watchdog Reset

impl W<u32, Reg<u32, _IFS>>

pub fn tout(&mut self) -> TOUT_W<'_>

Bit 0 - Set TOUT Interrupt Flag

pub fn warn(&mut self) -> WARN_W<'_>

Bit 1 - Set WARN Interrupt Flag

pub fn win(&mut self) -> WIN_W<'_>

Bit 2 - Set WIN Interrupt Flag

pub fn pem0(&mut self) -> PEM0_W<'_>

Bit 3 - Set PEM0 Interrupt Flag

pub fn pem1(&mut self) -> PEM1_W<'_>

Bit 4 - Set PEM1 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn tout(&mut self) -> TOUT_W<'_>

Bit 0 - Clear TOUT Interrupt Flag

pub fn warn(&mut self) -> WARN_W<'_>

Bit 1 - Clear WARN Interrupt Flag

pub fn win(&mut self) -> WIN_W<'_>

Bit 2 - Clear WIN Interrupt Flag

pub fn pem0(&mut self) -> PEM0_W<'_>

Bit 3 - Clear PEM0 Interrupt Flag

pub fn pem1(&mut self) -> PEM1_W<'_>

Bit 4 - Clear PEM1 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn tout(&mut self) -> TOUT_W<'_>

Bit 0 - TOUT Interrupt Enable

pub fn warn(&mut self) -> WARN_W<'_>

Bit 1 - WARN Interrupt Enable

pub fn win(&mut self) -> WIN_W<'_>

Bit 2 - WIN Interrupt Enable

pub fn pem0(&mut self) -> PEM0_W<'_>

Bit 3 - PEM0 Interrupt Enable

pub fn pem1(&mut self) -> PEM1_W<'_>

Bit 4 - PEM1 Interrupt Enable

impl W<u32, Reg<u32, _ETMCR>>

pub fn powerdwn(&mut self) -> POWERDWN_W<'_>

Bit 0 - ETM Control in low power mode

pub fn portsize(&mut self) -> PORTSIZE_W<'_>

Bits 4:6 - ETM Port Size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 7 - Stall Processor

pub fn branchoutput(&mut self) -> BRANCHOUTPUT_W<'_>

Bit 8 - Branch Output

pub fn dbgreqctrl(&mut self) -> DBGREQCTRL_W<'_>

Bit 9 - Debug Request Control

pub fn etmprog(&mut self) -> ETMPROG_W<'_>

Bit 10 - ETM Programming

pub fn etmportsel(&mut self) -> ETMPORTSEL_W<'_>

Bit 11 - ETM Port Selection

pub fn portmode2(&mut self) -> PORTMODE2_W<'_>

Bit 13 - Port Mode[2]

pub fn portmode(&mut self) -> PORTMODE_W<'_>

Bits 16:17 - Port Mode Control

pub fn eportsize(&mut self) -> EPORTSIZE_W<'_>

Bits 21:22 - Port Size[3]

pub fn tstampen(&mut self) -> TSTAMPEN_W<'_>

Bit 28 - Time Stamp Enable

impl W<u32, Reg<u32, _ETMTRIGGER>>

pub fn resa(&mut self) -> RESA_W<'_>

Bits 0:6 - ETM Resource A

pub fn resb(&mut self) -> RESB_W<'_>

Bits 7:13 - ETM Resource B

pub fn etmfcn(&mut self) -> ETMFCN_W<'_>

Bits 14:16 - ETM Function

impl W<u32, Reg<u32, _ETMSR>>

pub fn tracestat(&mut self) -> TRACESTAT_W<'_>

Bit 2 - Trace Start/Stop Status

pub fn trigbit(&mut self) -> TRIGBIT_W<'_>

Bit 3 - Trigger Bit

impl W<u32, Reg<u32, _ETMTEEVR>>

pub fn resa(&mut self) -> RESA_W<'_>

Bits 0:6 - ETM Resource A Trace Enable

pub fn resb(&mut self) -> RESB_W<'_>

Bits 7:13 - ETM Resource B Trace Enable

pub fn etmfcnen(&mut self) -> ETMFCNEN_W<'_>

Bits 14:16 - ETM Function Trace Enable

impl W<u32, Reg<u32, _ETMTECR1>>

pub fn adrcmp(&mut self) -> ADRCMP_W<'_>

Bits 0:7 - Address Comparator

pub fn memmap(&mut self) -> MEMMAP_W<'_>

Bits 8:23 - Memmap

pub fn incexctl(&mut self) -> INCEXCTL_W<'_>

Bit 24 - Trace Include/Exclude Flag

pub fn tce(&mut self) -> TCE_W<'_>

Bit 25 - Trace Control Enable

impl W<u32, Reg<u32, _ETMFFLR>>

pub fn bytenum(&mut self) -> BYTENUM_W<'_>

Bits 0:7 - Bytes left in FIFO

impl W<u32, Reg<u32, _ETMCNTRLDVR1>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Free running counter reload value

impl W<u32, Reg<u32, _ETMSYNCFR>>

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:11 - Synchronisation Frequency Value

impl W<u32, Reg<u32, _ETMTESSEICR>>

pub fn startrsel(&mut self) -> STARTRSEL_W<'_>

Bits 0:3 - Stop Resource Selection

pub fn stoprsel(&mut self) -> STOPRSEL_W<'_>

Bits 16:19 - Stop Resource Selection

impl W<u32, Reg<u32, _ETMTSEVR>>

pub fn resaevt(&mut self) -> RESAEVT_W<'_>

Bits 0:6 - ETM Resource A Event

pub fn resbevt(&mut self) -> RESBEVT_W<'_>

Bits 7:13 - ETM Resource B Event

pub fn etmfcnevt(&mut self) -> ETMFCNEVT_W<'_>

Bits 14:16 - ETM Function Event

impl W<u32, Reg<u32, _ETMTRACEIDR>>

pub fn traceid(&mut self) -> TRACEID_W<'_>

Bits 0:6 - Trace ID

impl W<u32, Reg<u32, _ETMISCIN>>

pub fn extin(&mut self) -> EXTIN_W<'_>

Bits 0:1 - EXTIN Value

pub fn corehalt(&mut self) -> COREHALT_W<'_>

Bit 4 - Core Halt

impl W<u32, Reg<u32, _ITTRIGOUT>>

pub fn triggerout(&mut self) -> TRIGGEROUT_W<'_>

Bit 0 - Trigger output value

impl W<u32, Reg<u32, _ETMITATBCTR0>>

pub fn atvalid(&mut self) -> ATVALID_W<'_>

Bit 0 - ATVALID Output Value

impl W<u32, Reg<u32, _ETMITCTRL>>

pub fn iten(&mut self) -> ITEN_W<'_>

Bit 0 - Integration Mode Enable

impl W<u32, Reg<u32, _ETMCLAIMSET>>

pub fn settag(&mut self) -> SETTAG_W<'_>

Bits 0:7 - Tag Bits

impl W<u32, Reg<u32, _ETMCLAIMCLR>>

pub fn clrtag(&mut self) -> CLRTAG_W<'_>

Bit 0 - Tag Bits

impl W<u32, Reg<u32, _ETMLAR>>

pub fn key(&mut self) -> KEY_W<'_>

Bit 0 - Key Value

impl W<u32, Reg<u32, _IFS>>

pub fn ppupriv(&mut self) -> PPUPRIV_W<'_>

Bit 0 - Set PPUPRIV Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn ppupriv(&mut self) -> PPUPRIV_W<'_>

Bit 0 - Clear PPUPRIV Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn ppupriv(&mut self) -> PPUPRIV_W<'_>

Bit 0 - PPUPRIV Interrupt Enable

impl W<u32, Reg<u32, _PPUCTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0

impl W<u32, Reg<u32, _PPUPATD0>>

pub fn acmp0(&mut self) -> ACMP0_W<'_>

Bit 0 - Analog Comparator 0 access control bit

pub fn acmp1(&mut self) -> ACMP1_W<'_>

Bit 1 - Analog Comparator 1 access control bit

pub fn acmp2(&mut self) -> ACMP2_W<'_>

Bit 2 - Analog Comparator 1 access control bit

pub fn acmp3(&mut self) -> ACMP3_W<'_>

Bit 3 - Analog Comparator 3 access control bit

pub fn adc0(&mut self) -> ADC0_W<'_>

Bit 4 - Analog to Digital Converter 0 access control bit

pub fn adc1(&mut self) -> ADC1_W<'_>

Bit 5 - Analog to Digital Converter 0 access control bit

pub fn can0(&mut self) -> CAN0_W<'_>

Bit 6 - CAN 0 access control bit

pub fn can1(&mut self) -> CAN1_W<'_>

Bit 7 - CAN 1 access control bit

pub fn cmu(&mut self) -> CMU_W<'_>

Bit 8 - Clock Management Unit access control bit

pub fn cryotimer(&mut self) -> CRYOTIMER_W<'_>

Bit 9 - CRYOTIMER access control bit

pub fn crypto0(&mut self) -> CRYPTO0_W<'_>

Bit 10 - Advanced Encryption Standard Accelerator access control bit

pub fn csen(&mut self) -> CSEN_W<'_>

Bit 11 - Capacitive touch sense module access control bit

pub fn vdac0(&mut self) -> VDAC0_W<'_>

Bit 12 - Digital to Analog Converter 0 access control bit

pub fn prs(&mut self) -> PRS_W<'_>

Bit 13 - Peripheral Reflex System access control bit

pub fn ebi(&mut self) -> EBI_W<'_>

Bit 14 - External Bus Interface access control bit

pub fn emu(&mut self) -> EMU_W<'_>

Bit 15 - Energy Management Unit access control bit

pub fn eth(&mut self) -> ETH_W<'_>

Bit 16 - Ethernet Controller access control bit

pub fn fpueh(&mut self) -> FPUEH_W<'_>

Bit 17 - FPU Exception Handler access control bit

pub fn gpcrc(&mut self) -> GPCRC_W<'_>

Bit 18 - General Purpose CRC access control bit

pub fn gpio(&mut self) -> GPIO_W<'_>

Bit 19 - General purpose Input/Output access control bit

pub fn i2c0(&mut self) -> I2C0_W<'_>

Bit 20 - I2C 0 access control bit

pub fn i2c1(&mut self) -> I2C1_W<'_>

Bit 21 - I2C 1 access control bit

pub fn i2c2(&mut self) -> I2C2_W<'_>

Bit 22 - I2C 2 access control bit

pub fn idac0(&mut self) -> IDAC0_W<'_>

Bit 23 - Current Digital to Analog Converter 0 access control bit

pub fn msc(&mut self) -> MSC_W<'_>

Bit 24 - Memory System Controller access control bit

pub fn lcd(&mut self) -> LCD_W<'_>

Bit 25 - Liquid Crystal Display Controller access control bit

pub fn ldma(&mut self) -> LDMA_W<'_>

Bit 26 - Linked Direct Memory Access Controller access control bit

pub fn lesense(&mut self) -> LESENSE_W<'_>

Bit 27 - Low Energy Sensor Interface access control bit

pub fn letimer0(&mut self) -> LETIMER0_W<'_>

Bit 28 - Low Energy Timer 0 access control bit

pub fn letimer1(&mut self) -> LETIMER1_W<'_>

Bit 29 - Low Energy Timer 1 access control bit

pub fn leuart0(&mut self) -> LEUART0_W<'_>

Bit 30 - Low Energy UART 0 access control bit

pub fn leuart1(&mut self) -> LEUART1_W<'_>

Bit 31 - Low Energy UART 1 access control bit

impl W<u32, Reg<u32, _PPUPATD1>>

pub fn pcnt0(&mut self) -> PCNT0_W<'_>

Bit 0 - Pulse Counter 0 access control bit

pub fn pcnt1(&mut self) -> PCNT1_W<'_>

Bit 1 - Pulse Counter 1 access control bit

pub fn pcnt2(&mut self) -> PCNT2_W<'_>

Bit 2 - Pulse Counter 2 access control bit

pub fn qspi0(&mut self) -> QSPI0_W<'_>

Bit 3 - Quad-SPI access control bit

pub fn rmu(&mut self) -> RMU_W<'_>

Bit 4 - Reset Management Unit access control bit

pub fn rtc(&mut self) -> RTC_W<'_>

Bit 5 - Real-Time Counter access control bit

pub fn rtcc(&mut self) -> RTCC_W<'_>

Bit 6 - Real-Time Counter and Calendar access control bit

pub fn sdio(&mut self) -> SDIO_W<'_>

Bit 7 - SDIO Controller access control bit

pub fn smu(&mut self) -> SMU_W<'_>

Bit 8 - Security Management Unit access control bit

pub fn timer0(&mut self) -> TIMER0_W<'_>

Bit 9 - Timer 0 access control bit

pub fn timer1(&mut self) -> TIMER1_W<'_>

Bit 10 - Timer 1 access control bit

pub fn timer2(&mut self) -> TIMER2_W<'_>

Bit 11 - Timer 2 access control bit

pub fn timer3(&mut self) -> TIMER3_W<'_>

Bit 12 - Timer 3 access control bit

pub fn timer4(&mut self) -> TIMER4_W<'_>

Bit 13 - Timer 4 access control bit

pub fn timer5(&mut self) -> TIMER5_W<'_>

Bit 14 - Timer 5 access control bit

pub fn timer6(&mut self) -> TIMER6_W<'_>

Bit 15 - Timer 6 access control bit

pub fn trng0(&mut self) -> TRNG0_W<'_>

Bit 16 - True Random Number Generator 0 access control bit

pub fn uart0(&mut self) -> UART0_W<'_>

Bit 17 - Universal Asynchronous Receiver/Transmitter 0 access control bit

pub fn uart1(&mut self) -> UART1_W<'_>

Bit 18 - Universal Asynchronous Receiver/Transmitter 1 access control bit

pub fn usart0(&mut self) -> USART0_W<'_>

Bit 19 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit

pub fn usart1(&mut self) -> USART1_W<'_>

Bit 20 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit

pub fn usart2(&mut self) -> USART2_W<'_>

Bit 21 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit

pub fn usart3(&mut self) -> USART3_W<'_>

Bit 22 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit

pub fn usart4(&mut self) -> USART4_W<'_>

Bit 23 - Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit

pub fn usart5(&mut self) -> USART5_W<'_>

Bit 24 - Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit

pub fn usb(&mut self) -> USB_W<'_>

Bit 25 - Universal Serial Bus Interface access control bit

pub fn wdog0(&mut self) -> WDOG0_W<'_>

Bit 26 - Watchdog access control bit

pub fn wdog1(&mut self) -> WDOG1_W<'_>

Bit 27 - Watchdog access control bit

pub fn wtimer0(&mut self) -> WTIMER0_W<'_>

Bit 28 - Wide Timer 0 access control bit

pub fn wtimer1(&mut self) -> WTIMER1_W<'_>

Bit 29 - Wide Timer 0 access control bit

pub fn wtimer2(&mut self) -> WTIMER2_W<'_>

Bit 30 - Wide Timer 2 access control bit

pub fn wtimer3(&mut self) -> WTIMER3_W<'_>

Bit 31 - Wide Timer 3 access control bit

impl W<u32, Reg<u32, _CONTROL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - TRNG Module Enable

pub fn testen(&mut self) -> TESTEN_W<'_>

Bit 2 - Test Enable

pub fn condbypass(&mut self) -> CONDBYPASS_W<'_>

Bit 3 - Conditioning Bypass

pub fn repcountien(&mut self) -> REPCOUNTIEN_W<'_>

Bit 4 - Interrupt Enable for Repetition Count Test Failure

pub fn apt64ien(&mut self) -> APT64IEN_W<'_>

Bit 5 - Interrupt Enable for Adaptive Proportion Test Failure (64-sample Window)

pub fn apt4096ien(&mut self) -> APT4096IEN_W<'_>

Bit 6 - Interrupt Enable for Adaptive Proportion Test Failure (4096-sample Window)

pub fn fullien(&mut self) -> FULLIEN_W<'_>

Bit 7 - Interrupt Enable for FIFO Full

pub fn softreset(&mut self) -> SOFTRESET_W<'_>

Bit 8 - Software Reset

pub fn preien(&mut self) -> PREIEN_W<'_>

Bit 9 - Interrupt enable for AIS31 preliminary noise alarm

pub fn almien(&mut self) -> ALMIEN_W<'_>

Bit 10 - Interrupt enable for AIS31 noise alarm

pub fn forcerun(&mut self) -> FORCERUN_W<'_>

Bit 11 - Oscillator Force Run

pub fn bypnist(&mut self) -> BYPNIST_W<'_>

Bit 12 - NIST Start-up Test Bypass.

pub fn bypais31(&mut self) -> BYPAIS31_W<'_>

Bit 13 - AIS31 Start-up Test Bypass.

impl W<u32, Reg<u32, _KEY0>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Key 0

impl W<u32, Reg<u32, _KEY1>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Key 1

impl W<u32, Reg<u32, _KEY2>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Key 2

impl W<u32, Reg<u32, _KEY3>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Key 3

impl W<u32, Reg<u32, _TESTDATA>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Test data input to conditioning function or to the continuous tests

impl W<u32, Reg<u32, _STATUS>>

pub fn preif(&mut self) -> PREIF_W<'_>

Bit 8 - AIS31 Preliminary Noise Alarm interrupt status

impl W<u32, Reg<u32, _INITWAITVAL>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:7 - Wait counter value