Type Definition efm32gg11b::eth::ienc::W[][src]

type W = W<u32, IENC>;
Expand description

Writer for register IENC

Implementations

Bit 0 - Disable management done interrupt

Bit 1 - Disable receive complete interrupt

Bit 2 - Disable receive used bit read interrupt

Bit 3 - Disable transmit used bit read interrupt

Bit 4 - Disable transmit buffer under run interrupt

Bit 5 - Disable retry limit exceeded or late collision interrupt

Bit 6 - Disable transmit frame corruption due to AMBA (AHB) error interrupt

Bit 7 - Disable transmit complete interrupt

Bit 10 - Disable receive overrun interrupt

Bit 11 - Disable bresp/hresp not OK interrupt

Bit 12 - Disable pause frame with non-zero pause quantum interrupt

Bit 13 - Disable pause time zero interrupt

Bit 14 - Disable pause frame transmitted interrupt

Bit 18 - Disable PTP delay_req frame received interrupt

Bit 19 - Disable PTP sync frame received interrupt

Bit 20 - Disable PTP delay_req frame transmitted interrupt

Bit 21 - Disable PTP sync frame transmitted interrupt

Bit 22 - Disable PTP pdelay_req frame received interrupt

Bit 23 - Disable PTP pdelay_resp frame received interrupt

Bit 24 - Disable PTP pdelay_req frame transmitted interrupt

Bit 25 - Disable PTP pdelay_resp frame transmitted interrupt

Bit 26 - Disable TSU seconds register increment interrupt

Bit 27 - Disable RX LPI indication interrupt

Bit 28 - Disable WOL event received interrupt

Bit 29 - Disable TSU timer comparison interrupt.