Type Definition efm32gg11b::ebi::ctrl::W[][src]

type W = W<u32, CTRL>;
Expand description

Writer for register CTRL

Implementations

Bits 0:1 - Mode

Bits 2:3 - Mode 1

Bits 4:5 - Mode 2

Bits 6:7 - Mode 3

Bit 8 - Bank 0 Enable

Bit 9 - Bank 1 Enable

Bit 10 - Bank 2 Enable

Bit 11 - Bank 3 Enable

Bit 12 - No Idle Cycle Insertion on Bank 0

Bit 13 - No Idle Cycle Insertion on Bank 1

Bit 14 - No Idle Cycle Insertion on Bank 2

Bit 15 - No Idle Cycle Insertion on Bank 3

Bit 16 - ARDY Enable

Bit 17 - ARDY Timeout Disable

Bit 18 - ARDY Enable for Bank 1

Bit 19 - ARDY Timeout Disable for Bank 1

Bit 20 - ARDY Enable for Bank 2

Bit 21 - ARDY Timeout Disable for Bank 2

Bit 22 - ARDY Enable for Bank 3

Bit 23 - ARDY Timeout Disable for Bank 3

Bit 24 - Byte Lane Enable for Bank 0

Bit 25 - Byte Lane Enable for Bank 1

Bit 26 - Byte Lane Enable for Bank 2

Bit 27 - Byte Lane Enable for Bank 3

Bit 30 - Individual Timing Set, Line Polarity and Mode Definition Enable

Bit 31 - Alternative Address Map Enable