eeric/rv_core/instruction/executor/v/
vwadd.rs

1use crate::rv_core::instruction::executor::prelude::*;
2
3pub fn vv(
4    Opmvv {
5        dest: vd,
6        vs1,
7        vs2,
8        vm,
9    }: Opmvv,
10    v: &mut VectorContext<'_>,
11) -> Result<(), String> {
12    let vreg = izip!(v.get(vs2).iter_eew(), v.get(vs1).iter_eew())
13        .masked_map(
14            v.default_mask(vm),
15            v.get_wide(vd)?.iter_eew(),
16            |(vs2, vs1)| (vs2 as i64 as u128).wrapping_add(vs1 as i64 as u128),
17        )
18        .collect_with_wide_eew(v.vec_engine.sew);
19
20    v.apply(vd, vreg);
21
22    Ok(())
23}
24
25pub fn vx(
26    Opmvx {
27        dest: vd,
28        rs1,
29        vs2,
30        vm,
31    }: Opmvx,
32    v: &mut VectorContext<'_>,
33    x: &IntegerRegisters,
34) -> Result<(), String> {
35    let vreg = v
36        .get(vs2)
37        .iter_eew()
38        .masked_map(v.default_mask(vm), v.get_wide(vd)?.iter_eew(), |vs2| {
39            (vs2 as i64 as u128).wrapping_add(x[rs1] as i64 as u128)
40        })
41        .collect_with_wide_eew(v.vec_engine.sew);
42
43    v.apply(vd, vreg);
44
45    Ok(())
46}
47
48pub fn wv(
49    Opmvv {
50        dest: vd,
51        vs1,
52        vs2,
53        vm,
54    }: Opmvv,
55    v: &mut VectorContext<'_>,
56) -> Result<(), String> {
57    let vreg = izip!(v.get_wide(vs2)?.iter_eew(), v.get(vs1).iter_eew())
58        .masked_map(
59            v.default_mask(vm),
60            v.get_wide(vd)?.iter_eew(),
61            |(vs2, vs1)| vs2.wrapping_add(vs1 as i64 as u128),
62        )
63        .collect_with_wide_eew(v.vec_engine.sew);
64
65    v.apply(vd, vreg);
66
67    Ok(())
68}
69
70pub fn wx(
71    Opmvx {
72        dest: vd,
73        rs1,
74        vs2,
75        vm,
76    }: Opmvx,
77    v: &mut VectorContext<'_>,
78    x: &IntegerRegisters,
79) -> Result<(), String> {
80    let vreg = v
81        .get_wide(vs2)?
82        .iter_eew()
83        .masked_map(v.default_mask(vm), v.get_wide(vd)?.iter_eew(), |vs2| {
84            vs2.wrapping_add(x[rs1] as i64 as u128)
85        })
86        .collect_with_wide_eew(v.vec_engine.sew);
87
88    v.apply(vd, vreg);
89
90    Ok(())
91}
eeric/rv_core/instruction/executor/v/vwadd.rs

eeric/rv_core/instruction/executor/v/
vwadd.rs
