eeric/rv_core/instruction/executor/v/
vsadd.rs

1use crate::rv_core::instruction::executor::prelude::*;
2
3pub fn vv(Opivv { vd, vs1, vs2, vm }: Opivv, v: &mut VectorContext<'_>) {
4    let vreg = izip!(v.get(vs2).iter_eew(), v.get(vs1).iter_eew())
5        .masked_map(
6            v.default_mask(vm),
7            v.get(vd).iter_eew(),
8            |(vs2, vs1)| match v.vec_engine.sew {
9                BaseSew::E8 => (vs2 as i8).saturating_add(vs1 as i8) as u64,
10                BaseSew::E16 => (vs2 as i16).saturating_add(vs1 as i16) as u64,
11                BaseSew::E32 => (vs2 as i32).saturating_add(vs1 as i32) as u64,
12                BaseSew::E64 => (vs2 as i64).saturating_add(vs1 as i64) as u64,
13            },
14        )
15        .collect_with_eew(v.vec_engine.sew);
16
17    v.apply(vd, vreg);
18}
19
20pub fn vx(Opivx { vd, rs1, vs2, vm }: Opivx, v: &mut VectorContext<'_>, x: &IntegerRegisters) {
21    let vreg = v
22        .get(vs2)
23        .iter_eew()
24        .masked_map(v.default_mask(vm), v.get(vd).iter_eew(), |vs2| {
25            match v.vec_engine.sew {
26                BaseSew::E8 => (vs2 as i8).saturating_add(x[rs1] as i8) as u64,
27                BaseSew::E16 => (vs2 as i16).saturating_add(x[rs1] as i16) as u64,
28                BaseSew::E32 => (vs2 as i32).saturating_add(x[rs1] as i32) as u64,
29                BaseSew::E64 => (vs2 as i64).saturating_add(x[rs1] as i64) as u64,
30            }
31        })
32        .collect_with_eew(v.vec_engine.sew);
33
34    v.apply(vd, vreg);
35}
36
37pub fn vi(Opivi { vd, imm5, vs2, vm }: Opivi, v: &mut VectorContext<'_>) {
38    let vreg = v
39        .get(vs2)
40        .iter_eew()
41        .masked_map(v.default_mask(vm), v.get(vd).iter_eew(), |vs2| {
42            match v.vec_engine.sew {
43                BaseSew::E8 => (vs2 as i8).saturating_add(imm5 as i8) as u64,
44                BaseSew::E16 => (vs2 as i16).saturating_add(imm5 as i16) as u64,
45                BaseSew::E32 => (vs2 as i32).saturating_add(imm5) as u64,
46                BaseSew::E64 => (vs2 as i64).saturating_add(imm5 as i64) as u64,
47            }
48        })
49        .collect_with_eew(v.vec_engine.sew);
50
51    v.apply(vd, vreg);
52}
eeric/rv_core/instruction/executor/v/vsadd.rs

eeric/rv_core/instruction/executor/v/
vsadd.rs
