eeric 0.0.21

An easily embeddable RV64I core with MFDV extensions
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66

pub mod arbitrary_float;
pub mod instruction;
pub mod memory;
pub mod registers;
pub mod vector_engine;
pub mod snapshot;

use derive_builder::Builder;

use instruction::{executor::Executor, Instruction};
use memory::Memory;
use registers::Registers;

use self::vector_engine::VectorEngine;

#[derive(Builder, Clone, Default)]
#[cfg_attr(debug_assertions, derive(Debug))]
pub struct RvCore {
    #[builder(default)]
    pub memory: Memory,
    #[builder(default)]
    pub instructions: Vec<Instruction>,
    #[builder(default)]
    pub registers: Registers,
    #[builder(default)]
    pub vec_engine: VectorEngine
}

impl RvCore {
    pub fn step(&mut self) -> Option<()> {
        self.run().next()
    }

    pub fn run(&mut self) -> RunningRvCore {
        RunningRvCore { core: self }
    }
}

pub struct RunningRvCore<'core> {
    core: &'core mut RvCore,
}

impl Iterator for RunningRvCore<'_> {
    type Item = ();

    fn next(&mut self) -> Option<Self::Item> {
        let instruction_pointer = self.core.registers.pc / 4;
        let instruction = self
            .core
            .instructions
            .get(instruction_pointer as usize)?
            .clone();
        Executor::new(&mut self.core.registers, &mut self.core.memory, &mut self.core.vec_engine).execute(instruction);
        Some(())
    }
}

#[cfg(test)]
mod tests {
    use super::RvCoreBuilder;

    #[test]
    fn all_props_have_default_values() {
        RvCoreBuilder::default().build().unwrap();
    }
}