dynasm 5.0.0

// The base of this file was generated by tools/riscv_gen_opmap.py
Ops!(


// Extension(s) a

"amoadd.d" = [
    // amoadd.d rd, rs1, rs2, aq, rl (a)
    Single(0x0000302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoadd.d.aq" = [
    // amoadd.d.aq rd, rs1, rs2, aq, rl (a)
    Single(0x0400302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoadd.d.aqrl" = [
    // amoadd.d.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x0600302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoadd.d.rl" = [
    // amoadd.d.rl rd, rs1, rs2, aq, rl (a)
    Single(0x0200302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoadd.w" = [
    // amoadd.w rd, rs1, rs2, aq, rl (a)
    Single(0x0000202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoadd.w.aq" = [
    // amoadd.w.aq rd, rs1, rs2, aq, rl (a)
    Single(0x0400202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoadd.w.aqrl" = [
    // amoadd.w.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x0600202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoadd.w.rl" = [
    // amoadd.w.rl rd, rs1, rs2, aq, rl (a)
    Single(0x0200202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoand.d" = [
    // amoand.d rd, rs1, rs2, aq, rl (a)
    Single(0x6000302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoand.d.aq" = [
    // amoand.d.aq rd, rs1, rs2, aq, rl (a)
    Single(0x6400302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoand.d.aqrl" = [
    // amoand.d.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x6600302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoand.d.rl" = [
    // amoand.d.rl rd, rs1, rs2, aq, rl (a)
    Single(0x6200302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoand.w" = [
    // amoand.w rd, rs1, rs2, aq, rl (a)
    Single(0x6000202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoand.w.aq" = [
    // amoand.w.aq rd, rs1, rs2, aq, rl (a)
    Single(0x6400202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoand.w.aqrl" = [
    // amoand.w.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x6600202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoand.w.rl" = [
    // amoand.w.rl rd, rs1, rs2, aq, rl (a)
    Single(0x6200202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomax.d" = [
    // amomax.d rd, rs1, rs2, aq, rl (a)
    Single(0xA000302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomax.d.aq" = [
    // amomax.d.aq rd, rs1, rs2, aq, rl (a)
    Single(0xA400302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomax.d.aqrl" = [
    // amomax.d.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0xA600302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomax.d.rl" = [
    // amomax.d.rl rd, rs1, rs2, aq, rl (a)
    Single(0xA200302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomax.w" = [
    // amomax.w rd, rs1, rs2, aq, rl (a)
    Single(0xA000202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomax.w.aq" = [
    // amomax.w.aq rd, rs1, rs2, aq, rl (a)
    Single(0xA400202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomax.w.aqrl" = [
    // amomax.w.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0xA600202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomax.w.rl" = [
    // amomax.w.rl rd, rs1, rs2, aq, rl (a)
    Single(0xA200202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomaxu.d" = [
    // amomaxu.d rd, rs1, rs2, aq, rl (a)
    Single(0xE000302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomaxu.d.aq" = [
    // amomaxu.d.aq rd, rs1, rs2, aq, rl (a)
    Single(0xE400302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomaxu.d.aqrl" = [
    // amomaxu.d.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0xE600302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomaxu.d.rl" = [
    // amomaxu.d.rl rd, rs1, rs2, aq, rl (a)
    Single(0xE200302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomaxu.w" = [
    // amomaxu.w rd, rs1, rs2, aq, rl (a)
    Single(0xE000202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomaxu.w.aq" = [
    // amomaxu.w.aq rd, rs1, rs2, aq, rl (a)
    Single(0xE400202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomaxu.w.aqrl" = [
    // amomaxu.w.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0xE600202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomaxu.w.rl" = [
    // amomaxu.w.rl rd, rs1, rs2, aq, rl (a)
    Single(0xE200202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomin.d" = [
    // amomin.d rd, rs1, rs2, aq, rl (a)
    Single(0x8000302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomin.d.aq" = [
    // amomin.d.aq rd, rs1, rs2, aq, rl (a)
    Single(0x8400302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomin.d.aqrl" = [
    // amomin.d.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x8600302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomin.d.rl" = [
    // amomin.d.rl rd, rs1, rs2, aq, rl (a)
    Single(0x8200302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomin.w" = [
    // amomin.w rd, rs1, rs2, aq, rl (a)
    Single(0x8000202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomin.w.aq" = [
    // amomin.w.aq rd, rs1, rs2, aq, rl (a)
    Single(0x8400202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomin.w.aqrl" = [
    // amomin.w.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x8600202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amomin.w.rl" = [
    // amomin.w.rl rd, rs1, rs2, aq, rl (a)
    Single(0x8200202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amominu.d" = [
    // amominu.d rd, rs1, rs2, aq, rl (a)
    Single(0xC000302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amominu.d.aq" = [
    // amominu.d.aq rd, rs1, rs2, aq, rl (a)
    Single(0xC400302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amominu.d.aqrl" = [
    // amominu.d.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0xC600302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amominu.d.rl" = [
    // amominu.d.rl rd, rs1, rs2, aq, rl (a)
    Single(0xC200302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amominu.w" = [
    // amominu.w rd, rs1, rs2, aq, rl (a)
    Single(0xC000202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amominu.w.aq" = [
    // amominu.w.aq rd, rs1, rs2, aq, rl (a)
    Single(0xC400202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amominu.w.aqrl" = [
    // amominu.w.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0xC600202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amominu.w.rl" = [
    // amominu.w.rl rd, rs1, rs2, aq, rl (a)
    Single(0xC200202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoor.d" = [
    // amoor.d rd, rs1, rs2, aq, rl (a)
    Single(0x4000302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoor.d.aq" = [
    // amoor.d.aq rd, rs1, rs2, aq, rl (a)
    Single(0x4400302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoor.d.aqrl" = [
    // amoor.d.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x4600302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoor.d.rl" = [
    // amoor.d.rl rd, rs1, rs2, aq, rl (a)
    Single(0x4200302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoor.w" = [
    // amoor.w rd, rs1, rs2, aq, rl (a)
    Single(0x4000202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoor.w.aq" = [
    // amoor.w.aq rd, rs1, rs2, aq, rl (a)
    Single(0x4400202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoor.w.aqrl" = [
    // amoor.w.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x4600202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoor.w.rl" = [
    // amoor.w.rl rd, rs1, rs2, aq, rl (a)
    Single(0x4200202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoswap.d" = [
    // amoswap.d rd, rs1, rs2, aq, rl (a)
    Single(0x0800302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoswap.d.aq" = [
    // amoswap.d.aq rd, rs1, rs2, aq, rl (a)
    Single(0x0C00302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoswap.d.aqrl" = [
    // amoswap.d.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x0E00302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoswap.d.rl" = [
    // amoswap.d.rl rd, rs1, rs2, aq, rl (a)
    Single(0x0A00302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoswap.w" = [
    // amoswap.w rd, rs1, rs2, aq, rl (a)
    Single(0x0800202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoswap.w.aq" = [
    // amoswap.w.aq rd, rs1, rs2, aq, rl (a)
    Single(0x0C00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoswap.w.aqrl" = [
    // amoswap.w.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x0E00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoswap.w.rl" = [
    // amoswap.w.rl rd, rs1, rs2, aq, rl (a)
    Single(0x0A00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoxor.d" = [
    // amoxor.d rd, rs1, rs2, aq, rl (a)
    Single(0x2000302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoxor.d.aq" = [
    // amoxor.d.aq rd, rs1, rs2, aq, rl (a)
    Single(0x2400302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoxor.d.aqrl" = [
    // amoxor.d.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x2600302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoxor.d.rl" = [
    // amoxor.d.rl rd, rs1, rs2, aq, rl (a)
    Single(0x2200302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoxor.w" = [
    // amoxor.w rd, rs1, rs2, aq, rl (a)
    Single(0x2000202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoxor.w.aq" = [
    // amoxor.w.aq rd, rs1, rs2, aq, rl (a)
    Single(0x2400202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoxor.w.aqrl" = [
    // amoxor.w.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x2600202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"amoxor.w.rl" = [
    // amoxor.w.rl rd, rs1, rs2, aq, rl (a)
    Single(0x2200202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"lr.d" = [
    // lr.d rd, rs1, aq, rl (a)
    Single(0x1000302F),        RV64, [X, Ref] => [R(7), R(15)], [Ex_A];
],
"lr.d.aq" = [
    // lr.d.aq rd, rs1, aq, rl (a)
    Single(0x1400302F),        RV64, [X, Ref] => [R(7), R(15)], [Ex_A];
],
"lr.d.aqrl" = [
    // lr.d.aqrl rd, rs1, aq, rl (a)
    Single(0x1600302F),        RV64, [X, Ref] => [R(7), R(15)], [Ex_A];
],
"lr.d.rl" = [
    // lr.d.rl rd, rs1, aq, rl (a)
    Single(0x1200302F),        RV64, [X, Ref] => [R(7), R(15)], [Ex_A];
],
"lr.w" = [
    // lr.w rd, rs1, aq, rl (a)
    Single(0x1000202F), RV32 | RV64, [X, Ref] => [R(7), R(15)], [Ex_A];
],
"lr.w.aq" = [
    // lr.w.aq rd, rs1, aq, rl (a)
    Single(0x1400202F), RV32 | RV64, [X, Ref] => [R(7), R(15)], [Ex_A];
],
"lr.w.aqrl" = [
    // lr.w.aqrl rd, rs1, aq, rl (a)
    Single(0x1600202F), RV32 | RV64, [X, Ref] => [R(7), R(15)], [Ex_A];
],
"lr.w.rl" = [
    // lr.w.rl rd, rs1, aq, rl (a)
    Single(0x1200202F), RV32 | RV64, [X, Ref] => [R(7), R(15)], [Ex_A];
],
"sc.d" = [
    // sc.d rd, rs1, rs2, aq, rl (a)
    Single(0x1800302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"sc.d.aq" = [
    // sc.d.aq rd, rs1, rs2, aq, rl (a)
    Single(0x1C00302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"sc.d.aqrl" = [
    // sc.d.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x1E00302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"sc.d.rl" = [
    // sc.d.rl rd, rs1, rs2, aq, rl (a)
    Single(0x1A00302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"sc.w" = [
    // sc.w rd, rs1, rs2, aq, rl (a)
    Single(0x1800202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"sc.w.aq" = [
    // sc.w.aq rd, rs1, rs2, aq, rl (a)
    Single(0x1C00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"sc.w.aqrl" = [
    // sc.w.aqrl rd, rs1, rs2, aq, rl (a)
    Single(0x1E00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],
"sc.w.rl" = [
    // sc.w.rl rd, rs1, rs2, aq, rl (a)
    Single(0x1A00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_A];
],

// Extension(s) c

"c.add" = [
    // c.add rd_rs1_n0, c_rs2_n0 (c)
    Compressed(0x9002), RV32 | RV64, [X, X] => [Rno0(7), Rno0(2)], [Ex_C];
],
"c.addi" = [
    // c.addi rd_rs1_n0, c_nzimm6lo, c_nzimm6hi (c)
    Compressed(0x0001), RV32 | RV64, [X, Imm] => [Rno0(7), SImmNo0(6, 0), BitRange(2, 5, 0), BitRange(12, 1, 5), Next], [Ex_C];
],
"c.addi16sp" = [
    // c.addi16sp c_nzimm10hi, c_nzimm10lo (c)
    Compressed(0x6101), RV32 | RV64, [Reg(RegId::X2), Imm] => [SImmNo0(10, 4), BitRange(6, 1, 4), BitRange(5, 1, 6), BitRange(3, 2, 7), BitRange(2, 1, 5), BitRange(12, 1, 9), Next], [Ex_C];
],
"c.addi4spn" = [
    // c.addi4spn rd_p, c_nzuimm10 (c)
    Compressed(0x0000), RV32 | RV64, [X, Reg(RegId::X2), Imm] => [Rpop(2), UImmNo0(10, 2), BitRange(11, 2, 4), BitRange(7, 4, 6), BitRange(6, 1, 2), BitRange(5, 1, 3), Next], [Ex_C];
],
"c.addiw" = [
    // c.addiw rd_rs1_n0, c_imm6lo, c_imm6hi (c)
    Compressed(0x2001),        RV64, [X, Imm] => [Rno0(7), SImm(6, 0), BitRange(2, 5, 0), BitRange(12, 1, 5), Next], [Ex_C];
],
"c.addw" = [
    // c.addw rd_rs1_p, rs2_p (c)
    Compressed(0x9C21),        RV64, [X, X] => [Rpop(7), Rpop(2)], [Ex_C];
],
"c.and" = [
    // c.and rd_rs1_p, rs2_p (c)
    Compressed(0x8C61), RV32 | RV64, [X, X] => [Rpop(7), Rpop(2)], [Ex_C];
],
"c.andi" = [
    // c.andi rd_rs1_p, c_imm6hi, c_imm6lo (c)
    Compressed(0x8801), RV32 | RV64, [X, Imm] => [Rpop(7), SImm(6, 0), BitRange(2, 5, 0), BitRange(12, 1, 5), Next], [Ex_C];
],
"c.beqz" = [
    // c.beqz rs1_p, c_bimm9lo, c_bimm9hi (c)
    Compressed(0xC001), RV32 | RV64, [X, Offset] => [Rpop(7), Offset(BC)], [Ex_C];
],
"c.bnez" = [
    // c.bnez rs1_p, c_bimm9lo, c_bimm9hi (c)
    Compressed(0xE001), RV32 | RV64, [X, Offset] => [Rpop(7), Offset(BC)], [Ex_C];
],
"c.ebreak" = [
    // c.ebreak  (c)
    Compressed(0x9002), RV32 | RV64, [] => [], [Ex_C];
],
"c.j" = [
    // c.j c_imm12 (c)
    Compressed(0xA001), RV32 | RV64, [Offset] => [Offset(JC)], [Ex_C];
],
"c.jal" = [
    // c.jal c_imm12 (c)
    Compressed(0x2001), RV32       , [Offset] => [Offset(JC)], [Ex_C];
],
"c.jalr" = [
    // c.jalr c_rs1_n0 (c)
    Compressed(0x9002), RV32 | RV64, [X] => [Rno0(7)], [Ex_C];
],
"c.jr" = [
    // c.jr rs1_n0 (c)
    Compressed(0x8002), RV32 | RV64, [X] => [Rno0(7)], [Ex_C];
],
"c.ld" = [
    // c.ld rd_p, rs1_p, c_uimm8lo, c_uimm8hi (c)
    Compressed(0x6000),        RV64, [X, RefOffset] => [Rpop(2), Rpop(7), UImm(8, 3), BitRange(5, 2, 6), BitRange(10, 3, 3), Next], [Ex_C];
],
"c.ldsp" = [
    // c.ldsp rd_n0, c_uimm9sphi, c_uimm9splo (c)
    Compressed(0x6002),        RV64, [X, RefSp] => [Rno0(7), UImm(9, 3), BitRange(5, 2, 3), BitRange(2, 3, 6), BitRange(12, 1, 5), Next], [Ex_C];
],
"c.li" = [
    // c.li rd_n0, c_imm6lo, c_imm6hi (c)
    Compressed(0x4001), RV32 | RV64, [X, Imm] => [Rno0(7), SImm(6, 0), BitRange(2, 5, 0), BitRange(12, 1, 5), Next], [Ex_C];
],
"c.lui" = [
    // c.lui rd_n2, c_nzimm18hi, c_nzimm18lo (c)
    Compressed(0x6001), RV32 | RV64, [X, Imm] => [Rno02(7), SImmNo0(18, 12), BitRange(2, 5, 12), BitRange(12, 1, 17), Next], [Ex_C];
],
"c.lw" = [
    // c.lw rd_p, rs1_p, c_uimm7lo, c_uimm7hi (c)
    Compressed(0x4000), RV32 | RV64, [X, RefOffset] => [Rpop(2), Rpop(7), UImm(7, 2), BitRange(6, 1, 2), BitRange(5, 1, 6), BitRange(10, 3, 3), Next], [Ex_C];
],
"c.lwsp" = [
    // c.lwsp rd_n0, c_uimm8sphi, c_uimm8splo (c)
    Compressed(0x4002), RV32 | RV64, [X, RefSp] => [Rno0(7), UImm(8, 2), BitRange(4, 3, 2), BitRange(2, 2, 6), BitRange(12, 1, 5), Next], [Ex_C];
],
"c.mv" = [
    // c.mv rd_n0, c_rs2_n0 (c)
    Compressed(0x8002), RV32 | RV64, [X, X] => [Rno0(7), Rno0(2)], [Ex_C];
],
"c.nop" = [
    // c.nop c_nzimm6hi, c_nzimm6lo (c)
    Compressed(0x0001), RV32 | RV64, [] => [], [Ex_C];
],
"c.or" = [
    // c.or rd_rs1_p, rs2_p (c)
    Compressed(0x8C41), RV32 | RV64, [X, X] => [Rpop(7), Rpop(2)], [Ex_C];
],
"c.sd" = [
    // c.sd rs1_p, rs2_p, c_uimm8hi, c_uimm8lo (c)
    Compressed(0xE000),        RV64, [X, RefOffset] => [Rpop(2), Rpop(7), UImm(8, 3), BitRange(5, 2, 6), BitRange(10, 3, 3), Next], [Ex_C];
],
"c.sdsp" = [
    // c.sdsp c_rs2, c_uimm9sp_s (c)
    Compressed(0xE002),        RV64, [X, RefSp] => [R(2), UImm(9, 3), BitRange(10, 3, 3), BitRange(7, 3, 6), Next], [Ex_C];
],
"c.slli" = [
    // c.slli rd_rs1_n0, c_nzuimm6lo (subformat of rv64_c::c.slli) (c)
    Compressed(0x0002), RV32       , [X, Imm] => [Rno0(7), UImmNo0(5, 0), BitRange(2, 5, 0), Next], [Ex_C];
    // c.slli rd_rs1_n0, c_nzuimm6hi, c_nzuimm6lo (c)
    Compressed(0x0002),        RV64, [X, Imm] => [Rno0(7), UImmNo0(6, 0), BitRange(2, 5, 0), BitRange(12, 1, 5), Next], [Ex_C];
],
"c.srai" = [
    // c.srai rd_rs1_p, c_nzuimm5 (subformat of rv64_c::c.srai) (c)
    Compressed(0x8401), RV32       , [X, Imm] => [Rpop(7), UImmNo0(5, 0), BitRange(2, 5, 0), Next], [Ex_C];
    // c.srai rd_rs1_p, c_nzuimm6lo, c_nzuimm6hi (c)
    Compressed(0x8401),        RV64, [X, Imm] => [Rpop(7), UImmNo0(6, 0), BitRange(2, 5, 0), BitRange(12, 1, 5), Next], [Ex_C];
],
"c.srli" = [
    // c.srli rd_rs1_p, c_nzuimm5 (subformat of rv64_c::c.srli) (c)
    Compressed(0x8001), RV32       , [X, Imm] => [Rpop(7), UImmNo0(5, 0), BitRange(2, 5, 0), Next], [Ex_C];
    // c.srli rd_rs1_p, c_nzuimm6lo, c_nzuimm6hi (c)
    Compressed(0x8001),        RV64, [X, Imm] => [Rpop(7), UImmNo0(6, 0), BitRange(2, 5, 0), BitRange(12, 1, 5), Next], [Ex_C];
],
"c.sub" = [
    // c.sub rd_rs1_p, rs2_p (c)
    Compressed(0x8C01), RV32 | RV64, [X, X] => [Rpop(7), Rpop(2)], [Ex_C];
],
"c.subw" = [
    // c.subw rd_rs1_p, rs2_p (c)
    Compressed(0x9C01),        RV64, [X, X] => [Rpop(7), Rpop(2)], [Ex_C];
],
"c.sw" = [
    // c.sw rs1_p, rs2_p, c_uimm7lo, c_uimm7hi (c)
    Compressed(0xC000), RV32 | RV64, [X, RefOffset] => [Rpop(2), Rpop(7), UImm(7, 2), BitRange(6, 1, 2), BitRange(5, 1, 6), BitRange(10, 3, 3), Next], [Ex_C];
],
"c.swsp" = [
    // c.swsp c_rs2, c_uimm8sp_s (c)
    Compressed(0xC002), RV32 | RV64, [X, RefSp] => [R(2), UImm(8, 2), BitRange(9, 4, 2), BitRange(7, 2, 6), Next], [Ex_C];
],
"c.unimp" = [
    // guaranteed to not be a valid instruction
    Compressed(0x0000), RV32 | RV64, [] => [], [Ex_C];
],
"c.xor" = [
    // c.xor rd_rs1_p, rs2_p (c)
    Compressed(0x8C21), RV32 | RV64, [X, X] => [Rpop(7), Rpop(2)], [Ex_C];
],

// Extension(s) c_d

"c.fld" = [
    // c.fld rd_p, rs1_p, c_uimm8lo, c_uimm8hi (c_d)
    Compressed(0x2000), RV32 | RV64, [F, RefOffset] => [Rpop(2), Rpop(7), UImm(8, 3), BitRange(5, 2, 6), BitRange(10, 3, 3), Next], [Ex_C | Ex_D];
],
"c.fldsp" = [
    // c.fldsp rd, c_uimm9sphi, c_uimm9splo (c_d)
    Compressed(0x2002), RV32 | RV64, [F, RefSp] => [R(7), UImm(9, 3), BitRange(5, 2, 3), BitRange(2, 3, 6), BitRange(12, 1, 5), Next], [Ex_C | Ex_D];
],
"c.fsd" = [
    // c.fsd rs1_p, rs2_p, c_uimm8lo, c_uimm8hi (c_d)
    Compressed(0xA000), RV32 | RV64, [F, RefOffset] => [Rpop(2), Rpop(7), UImm(8, 3), BitRange(5, 2, 6), BitRange(10, 3, 3), Next], [Ex_C | Ex_D];
],
"c.fsdsp" = [
    // c.fsdsp c_rs2, c_uimm9sp_s (c_d)
    Compressed(0xA002), RV32 | RV64, [F, RefSp] => [R(2), UImm(9, 3), BitRange(10, 3, 3), BitRange(7, 3, 6), Next], [Ex_C | Ex_D];
],

// Extension(s) c_f

"c.flw" = [
    // c.flw rd_p, rs1_p, c_uimm7lo, c_uimm7hi (c_f)
    Compressed(0x6000), RV32       , [F, RefOffset] => [Rpop(2), Rpop(7), UImm(7, 2), BitRange(6, 1, 2), BitRange(5, 1, 6), BitRange(10, 3, 3), Next], [Ex_C | Ex_F];
],
"c.flwsp" = [
    // c.flwsp rd, c_uimm8sphi, c_uimm8splo (c_f)
    Compressed(0x6002), RV32       , [F, RefSp] => [R(7), UImm(8, 2), BitRange(4, 3, 2), BitRange(2, 2, 6), BitRange(12, 1, 5), Next], [Ex_C | Ex_F];
],
"c.fsw" = [
    // c.fsw rs1_p, rs2_p, c_uimm7lo, c_uimm7hi (c_f)
    Compressed(0xE000), RV32       , [F, RefOffset] => [Rpop(2), Rpop(7), UImm(7, 2), BitRange(6, 1, 2), BitRange(5, 1, 6), BitRange(10, 3, 3), Next], [Ex_C | Ex_F];
],
"c.fswsp" = [
    // c.fswsp c_rs2, c_uimm8sp_s (c_f)
    Compressed(0xE002), RV32       , [F, RefSp] => [R(2), UImm(8, 2), BitRange(9, 4, 2), BitRange(7, 2, 6), Next], [Ex_C | Ex_F];
],

// Extension(s) zcmop_zicfiss

"c.sspopchk" = [
    // c.sspopchk.x5  (subformat of rv_zcmop::c.mop.N) (c_zicfiss)
    Compressed(0x6281), RV32 | RV64, [Reg(RegId::X5)] => [], [Ex_Zcmop | Ex_Zicfiss];
],
"c.sspush" = [
    // c.sspush.x1  (subformat of rv_zcmop::c.mop.N) (c_zicfiss)
    Compressed(0x6081), RV32 | RV64, [Reg(RegId::X1)] => [], [Ex_Zcmop | Ex_Zicfiss];
],

// Extension(s) c_zihintntl

"c.ntl.all" = [
    // c.ntl.all  (subformat of rv_c::c.add) (c_zihintntl)
    Compressed(0x9016), RV32 | RV64, [] => [], [Ex_C | Ex_Zihintntl];
],
"c.ntl.p1" = [
    // c.ntl.p1  (subformat of rv_c::c.add) (c_zihintntl)
    Compressed(0x900A), RV32 | RV64, [] => [], [Ex_C | Ex_Zihintntl];
],
"c.ntl.pall" = [
    // c.ntl.pall  (subformat of rv_c::c.add) (c_zihintntl)
    Compressed(0x900E), RV32 | RV64, [] => [], [Ex_C | Ex_Zihintntl];
],
"c.ntl.s1" = [
    // c.ntl.s1  (subformat of rv_c::c.add) (c_zihintntl)
    Compressed(0x9012), RV32 | RV64, [] => [], [Ex_C | Ex_Zihintntl];
],

// Extension(s) d

"fabs.d" = [
    // fabs.d rd, rs1, rs2=rs1 (subformat of rv_d::fsgnjx.d) (d)
    Single(0x22002053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_D];
    Single(0x22002053), RV32       , [X, X] => [Reven(7), Reven(15), Repeat, R(20)], [Ex_Zdinx];
    Single(0x22002053),        RV64, [X, X] => [R(7), R(15), Repeat, R(20)], [Ex_Zdinx];
],
"fadd.d" = [
    // fadd.d rd, rs1, rs2, rm (d)
    Single(0x02000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_D];
    Single(0x02000053), RV32       , [X, X, X, Ident] => [Reven(7), Reven(15), Reven(20), RoundingMode(12)], [Ex_Zdinx];
    Single(0x02000053),        RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zdinx];
    // fadd.d rd, rs1, rs2 (d)
    Single(0x02007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0x02007053), RV32       , [X, X, X] => [Reven(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0x02007053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],
"fclass.d" = [
    // fclass.d rd, rs1 (d)
    Single(0xE2001053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_D];
    Single(0xE2001053), RV32       , [X, X] => [R(7), Reven(15)], [Ex_Zdinx];
    Single(0xE2001053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fcvt.d.l" = [
    // fcvt.d.l rd, rs1, rm (d)
    Single(0xD2200053),        RV64, [F, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_D];
    Single(0xD2200053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zdinx];
    // fcvt.d.l rd, rs1 (d)
    Single(0xD2207053),        RV64, [F, X] => [R(7), R(15)], [Ex_D];
    Single(0xD2207053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fcvt.d.lu" = [
    // fcvt.d.lu rd, rs1, rm (d)
    Single(0xD2300053),        RV64, [F, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_D];
    Single(0xD2300053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zdinx];
    // fcvt.d.lu rd, rs1 (d)
    Single(0xD2307053),        RV64, [F, X] => [R(7), R(15)], [Ex_D];
    Single(0xD2307053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fcvt.d.s" = [
    // fcvt.d.s rd, rs1 (d)
    Single(0x42000053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_D];
    Single(0x42000053), RV32       , [X, X] => [Reven(7), Reven(15)], [Ex_Zdinx];
    Single(0x42000053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fcvt.d.w" = [
    // fcvt.d.w rd, rs1 (d)
    Single(0xD2000053), RV32 | RV64, [F, X] => [R(7), R(15)], [Ex_D];
    Single(0xD2000053), RV32       , [X, X] => [Reven(7), R(15)], [Ex_Zdinx];
    Single(0xD2000053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fcvt.d.wu" = [
    // fcvt.d.wu rd, rs1 (d)
    Single(0xD2100053), RV32 | RV64, [F, X] => [R(7), R(15)], [Ex_D];
    Single(0xD2100053), RV32       , [X, X] => [Reven(7), R(15)], [Ex_Zdinx];
    Single(0xD2100053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fcvt.l.d" = [
    // fcvt.l.d rd, rs1, rm (d)
    Single(0xC2200053),        RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_D];
    Single(0xC2200053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zdinx];
    // fcvt.l.d rd, rs1 (d)
    Single(0xC2207053),        RV64, [X, F] => [R(7), R(15)], [Ex_D];
    Single(0xC2207053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fcvt.lu.d" = [
    // fcvt.lu.d rd, rs1, rm (d)
    Single(0xC2300053),        RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_D];
    Single(0xC2300053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zdinx];
    // fcvt.lu.d rd, rs1 (d)
    Single(0xC2307053),        RV64, [X, F] => [R(7), R(15)], [Ex_D];
    Single(0xC2307053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fcvt.s.d" = [
    // fcvt.s.d rd, rs1, rm (d)
    Single(0x40100053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_D];
    Single(0x40100053), RV32       , [X, X, Ident] => [Reven(7), Reven(15), RoundingMode(12)], [Ex_Zdinx];
    Single(0x40100053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zdinx];
    // fcvt.s.d rd, rs1 (d)
    Single(0x40107053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_D];
    Single(0x40107053), RV32       , [X, X] => [Reven(7), Reven(15)], [Ex_Zdinx];
    Single(0x40107053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fcvt.w.d" = [
    // fcvt.w.d rd, rs1, rm (d)
    Single(0xC2000053), RV32 | RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_D];
    Single(0xC2000053), RV32       , [X, X, Ident] => [R(7), Reven(15), RoundingMode(12)], [Ex_Zdinx];
    Single(0xC2000053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zdinx];
    // fcvt.w.d rd, rs1 (d)
    Single(0xC2007053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_D];
    Single(0xC2007053), RV32       , [X, X] => [R(7), Reven(15)], [Ex_Zdinx];
    Single(0xC2007053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fcvt.wu.d" = [
    // fcvt.wu.d rd, rs1, rm (d)
    Single(0xC2100053), RV32 | RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_D];
    Single(0xC2100053), RV32       , [X, X, Ident] => [R(7), Reven(15), RoundingMode(12)], [Ex_Zdinx];
    Single(0xC2100053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zdinx];
    // fcvt.wu.d rd, rs1 (d)
    Single(0xC2107053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_D];
    Single(0xC2107053), RV32       , [X, X] => [R(7), Reven(15)], [Ex_Zdinx];
    Single(0xC2107053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fdiv.d" = [
    // fdiv.d rd, rs1, rs2, rm (d)
    Single(0x1A000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_D];
    Single(0x1A000053), RV32       , [X, X, X, Ident] => [Reven(7), Reven(15), Reven(20), RoundingMode(12)], [Ex_Zdinx];
    Single(0x1A000053),        RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zdinx];
    // fdiv.d rd, rs1, rs2 (d)
    Single(0x1A007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0x1A007053), RV32       , [X, X, X] => [Reven(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0x1A007053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],
"feq.d" = [
    // feq.d rd, rs1, rs2 (d)
    Single(0xA2002053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0xA2002053), RV32       , [X, X, X] => [R(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0xA2002053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],
"fld" = [
    // fld rd, rs1, imm12 (d)
    Single(0x00003007), RV32 | RV64, [F, RefOffset] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_D];
    // as part of a pc-relative load
    Single(0x00003007), RV32 | RV64, [F, RefLabel] => [R(7), R(15), Offset(LO12)], [Ex_D];
    // Pseudo instruction for auipc rd, hi20(symbol); fld, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00003007), RV32 | RV64, [F, Offset, X] => [R(7+32), Offset(SPLIT32), Rno0(7), Repeat, R(15+32)], [Ex_D];
],
"fle.d" = [
    // fle.d rd, rs1, rs2 (d)
    Single(0xA2000053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0xA2000053), RV32       , [X, X, X] => [R(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0xA2000053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],
"flt.d" = [
    // flt.d rd, rs1, rs2 (d)
    Single(0xA2001053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0xA2001053), RV32       , [X, X, X] => [R(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0xA2001053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],
"fmadd.d" = [
    // fmadd.d rd, rs1, rs2, rs3, rm (d)
    Single(0x02000043), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_D];
    Single(0x02000043), RV32       , [X, X, X, X, Ident] => [Reven(7), Reven(15), Reven(20), Reven(27), RoundingMode(12)], [Ex_Zdinx];
    Single(0x02000043),        RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zdinx];
    // fmadd.d rd, rs1, rs2, rs3 (d)
    Single(0x02007043), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_D];
    Single(0x02007043), RV32       , [X, X, X, X] => [Reven(7), Reven(15), Reven(20), Reven(27)], [Ex_Zdinx];
    Single(0x02007043),        RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zdinx];
],
"fmax.d" = [
    // fmax.d rd, rs1, rs2 (d)
    Single(0x2A001053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0x2A001053), RV32       , [X, X, X] => [Reven(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0x2A001053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],
"fmin.d" = [
    // fmin.d rd, rs1, rs2 (d)
    Single(0x2A000053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0x2A000053), RV32       , [X, X, X] => [Reven(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0x2A000053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],
"fmsub.d" = [
    // fmsub.d rd, rs1, rs2, rs3, rm (d)
    Single(0x02000047), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_D];
    Single(0x02000047), RV32       , [X, X, X, X, Ident] => [Reven(7), Reven(15), Reven(20), Reven(27), RoundingMode(12)], [Ex_Zdinx];
    Single(0x02000047),        RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zdinx];
    // fmsub.d rd, rs1, rs2, rs3 (d)
    Single(0x02007047), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_D];
    Single(0x02007047), RV32       , [X, X, X, X] => [Reven(7), Reven(15), Reven(20), Reven(27)], [Ex_Zdinx];
    Single(0x02007047),        RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zdinx];
],
"fmul.d" = [
    // fmul.d rd, rs1, rs2, rm (d)
    Single(0x12000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_D];
    Single(0x12000053), RV32       , [X, X, X, Ident] => [Reven(7), Reven(15), Reven(20), RoundingMode(12)], [Ex_Zdinx];
    Single(0x12000053),        RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zdinx];
    // fmul.d rd, rs1, rs2 (d)
    Single(0x12007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0x12007053), RV32       , [X, X, X] => [Reven(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0x12007053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],
"fmv.d" = [
    // fmv.d rd, rs1, rs2=rs1 (subformat of rv_d::fsgnj.d) (d)
    Single(0x22000053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_D];
    Single(0x22000053), RV32       , [X, X] => [Reven(7), Reven(15), Repeat, R(20)], [Ex_Zdinx];
    Single(0x22000053),        RV64, [X, X] => [R(7), R(15), Repeat, R(20)], [Ex_Zdinx];
],
"fmv.d.x" = [
    // fmv.d.x rd, rs1 (d)
    Single(0xF2000053),        RV64, [F, X] => [R(7), R(15)], [Ex_D];
],
"fmv.x.d" = [
    // fmv.x.d rd, rs1 (d)
    Single(0xE2000053),        RV64, [X, F] => [R(7), R(15)], [Ex_D];
],
"fneg.d" = [
    // fneg.d rd, rs1, rs2=rs1 (subformat of rv_d::fsgnjn.d) (d)
    Single(0x22001053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_D];
    Single(0x22001053), RV32       , [X, X] => [Reven(7), Reven(15), Repeat, R(20)], [Ex_Zdinx];
    Single(0x22001053),        RV64, [X, X] => [R(7), R(15), Repeat, R(20)], [Ex_Zdinx];
],
"fnmadd.d" = [
    // fnmadd.d rd, rs1, rs2, rs3, rm (d)
    Single(0x0200004F), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_D];
    Single(0x0200004F), RV32       , [X, X, X, X, Ident] => [Reven(7), Reven(15), Reven(20), Reven(27), RoundingMode(12)], [Ex_Zdinx];
    Single(0x0200004F),        RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zdinx];
    // fnmadd.d rd, rs1, rs2, rs3 (d)
    Single(0x0200704F), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_D];
    Single(0x0200704F), RV32       , [X, X, X, X] => [Reven(7), Reven(15), Reven(20), Reven(27)], [Ex_Zdinx];
    Single(0x0200704F),        RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zdinx];
],
"fnmsub.d" = [
    // fnmsub.d rd, rs1, rs2, rs3, rm (d)
    Single(0x0200004B), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_D];
    Single(0x0200004B), RV32       , [X, X, X, X, Ident] => [Reven(7), Reven(15), Reven(20), Reven(27), RoundingMode(12)], [Ex_Zdinx];
    Single(0x0200004B),        RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zdinx];
    // fnmsub.d rd, rs1, rs2, rs3 (d)
    Single(0x0200704B), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_D];
    Single(0x0200704B), RV32       , [X, X, X, X] => [Reven(7), Reven(15), Reven(20), Reven(27)], [Ex_Zdinx];
    Single(0x0200704B),        RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zdinx];
],
"fsd" = [
    // fsd imm12hi, rs1, rs2, imm12lo (d)
    Single(0x00003027), RV32 | RV64, [F, RefOffset] => [R(20), R(15), SImm(12, 0), BitRange(7, 5, 0), BitRange(25, 7, 5), Next], [Ex_D];
    // as part of a pc-relative store
    Single(0x00003027), RV32 | RV64, [F, RefLabel] => [R(20), R(15), Offset(LO12S)], [Ex_D];
    // Pseudo instruction for auipc rt, hi20(symbol); fsd, rd, rt, lo12(symbol)
    Double(0x00000017, 0x00003027), RV32 | RV64, [F, Offset, X] => [R(20+32), Offset(SPLIT32S), Rno0(7), Repeat, R(15+32)], [Ex_D];
],
"fsgnj.d" = [
    // fsgnj.d rd, rs1, rs2 (d)
    Single(0x22000053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0x22000053), RV32       , [X, X, X] => [Reven(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0x22000053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],
"fsgnjn.d" = [
    // fsgnjn.d rd, rs1, rs2 (d)
    Single(0x22001053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0x22001053), RV32       , [X, X, X] => [Reven(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0x22001053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],
"fsgnjx.d" = [
    // fsgnjx.d rd, rs1, rs2 (d)
    Single(0x22002053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0x22002053), RV32       , [X, X, X] => [Reven(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0x22002053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],
"fsqrt.d" = [
    // fsqrt.d rd, rs1, rm (d)
    Single(0x5A000053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_D];
    Single(0x5A000053), RV32       , [X, X, Ident] => [Reven(7), Reven(15), RoundingMode(12)], [Ex_Zdinx];
    Single(0x5A000053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zdinx];
    // fsqrt.d rd, rs1 (d)
    Single(0x5A007053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_D];
    Single(0x5A007053), RV32       , [X, X] => [Reven(7), Reven(15)], [Ex_Zdinx];
    Single(0x5A007053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx];
],
"fsub.d" = [
    // fsub.d rd, rs1, rs2, rm (d)
    Single(0x0A000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_D];
    Single(0x0A000053), RV32       , [X, X, X, Ident] => [Reven(7), Reven(15), Reven(20), RoundingMode(12)], [Ex_Zdinx];
    Single(0x0A000053),        RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zdinx];
    // fsub.d rd, rs1, rs2 (d)
    Single(0x0A007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_D];
    Single(0x0A007053), RV32       , [X, X, X] => [Reven(7), Reven(15), Reven(20)], [Ex_Zdinx];
    Single(0x0A007053),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zdinx];
],

// Extension(s) d_zfa

"fcvtmod.w.d" = [
    // fcvtmod.w.d rd, rs1 (d_zfa)
    Single(0xC2801053), RV32 | RV64, [X, F, Lit(Literal::RTZ)] => [R(7), R(15)], [Ex_D | Ex_Zfa];
],
"fleq.d" = [
    // fleq.d rd, rs1, rs2 (d_zfa)
    Single(0xA2004053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_D | Ex_Zfa];
],
"fli.d" = [
    // fli.d rd, rs1 (d_zfa)
    Single(0xF2100053), RV32 | RV64, [F, Imm] => [R(7), FloatingPointImmediate(15)], [Ex_D | Ex_Zfa];
],
"fltq.d" = [
    // fltq.d rd, rs1, rs2 (d_zfa)
    Single(0xA2005053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_D | Ex_Zfa];
],
"fmaxm.d" = [
    // fmaxm.d rd, rs1, rs2 (d_zfa)
    Single(0x2A003053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_D | Ex_Zfa];
],
"fminm.d" = [
    // fminm.d rd, rs1, rs2 (d_zfa)
    Single(0x2A002053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_D | Ex_Zfa];
],
"fmvh.x.d" = [
    // fmvh.x.d rd, rs1 (d_zfa)
    Single(0xE2100053), RV32       , [X, F] => [R(7), R(15)], [Ex_D | Ex_Zfa];
],
"fmvp.d.x" = [
    // fmvp.d.x rd, rs1, rs2 (d_zfa)
    Single(0xB2000053), RV32       , [F, X, X] => [R(7), R(15), R(20)], [Ex_D | Ex_Zfa];
],
"fround.d" = [
    // fround.d rd, rs1, rm (d_zfa)
    Single(0x42400053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_D | Ex_Zfa];
    // fround.d rd, rs1 (d_zfa)
    Single(0x42407053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_D | Ex_Zfa];
],
"froundnx.d" = [
    // froundnx.d rd, rs1, rm (d_zfa)
    Single(0x42500053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_D | Ex_Zfa];
    // froundnx.d rd, rs1 (d_zfa)
    Single(0x42507053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_D | Ex_Zfa];
],

// Extension(s) d_zfh

"fcvt.d.h" = [
    // fcvt.d.h rd, rs1 (d_zfh)
    Single(0x42200053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_D | Ex_Zfh, Ex_D | Ex_Zfhmin];
    Single(0x42200053), RV32       , [X, X] => [Reven(7), R(15)], [Ex_Zdinx | Ex_Zhinx, Ex_Zdinx | Ex_Zhinxmin];
    Single(0x42200053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx | Ex_Zhinx, Ex_Zdinx | Ex_Zhinxmin];
],
"fcvt.h.d" = [
    // fcvt.h.d rd, rs1, rm (d_zfh)
    Single(0x44100053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_D | Ex_Zfh, Ex_D | Ex_Zfhmin];
    Single(0x44100053), RV32       , [X, X, Ident] => [R(7), Reven(15), RoundingMode(12)], [Ex_Zdinx | Ex_Zhinx, Ex_Zdinx | Ex_Zhinxmin];
    Single(0x44100053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zdinx | Ex_Zhinx, Ex_Zdinx | Ex_Zhinxmin];
    // fcvt.h.d rd, rs1 (d_zfh)
    Single(0x44107053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_D | Ex_Zfh, Ex_D | Ex_Zfhmin];
    Single(0x44107053), RV32       , [X, X] => [R(7), Reven(15)], [Ex_Zdinx | Ex_Zhinx, Ex_Zdinx | Ex_Zhinxmin];
    Single(0x44107053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zdinx | Ex_Zhinx, Ex_Zdinx | Ex_Zhinxmin];
],

// Extension(s) f

"fabs.s" = [
    // fabs.s rd, rs1, rs2=rs1 (subformat of rv_f::fsgnjx.s) (f)
    Single(0x20002053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_F];
    Single(0x20002053), RV32 | RV64, [X, X] => [R(7), R(15), Repeat, R(20)], [Ex_Zfinx];
],
"fadd.s" = [
    // fadd.s rd, rs1, rs2, rm (f)
    Single(0x00000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_F];
    Single(0x00000053), RV32 | RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zfinx];
    // fadd.s rd, rs1, rs2 (f)
    Single(0x00007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0x00007053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"fclass.s" = [
    // fclass.s rd, rs1 (f)
    Single(0xE0001053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_F];
    Single(0xE0001053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zfinx];
],
"fcvt.l.s" = [
    // fcvt.l.s rd, rs1, rm (f)
    Single(0xC0200053),        RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_F];
    Single(0xC0200053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfinx];
    // fcvt.l.s rd, rs1 (f)
    Single(0xC0207053),        RV64, [X, F] => [R(7), R(15)], [Ex_F];
    Single(0xC0207053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zfinx];
],
"fcvt.lu.s" = [
    // fcvt.lu.s rd, rs1, rm (f)
    Single(0xC0300053),        RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_F];
    Single(0xC0300053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfinx];
    // fcvt.lu.s rd, rs1 (f)
    Single(0xC0307053),        RV64, [X, F] => [R(7), R(15)], [Ex_F];
    Single(0xC0307053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zfinx];
],
"fcvt.s.l" = [
    // fcvt.s.l rd, rs1, rm (f)
    Single(0xD0200053),        RV64, [F, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_F];
    Single(0xD0200053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfinx];
    // fcvt.s.l rd, rs1 (f)
    Single(0xD0207053),        RV64, [F, X] => [R(7), R(15)], [Ex_F];
    Single(0xD0207053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zfinx];
],
"fcvt.s.lu" = [
    // fcvt.s.lu rd, rs1, rm (f)
    Single(0xD0300053),        RV64, [F, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_F];
    Single(0xD0300053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfinx];
    // fcvt.s.lu rd, rs1 (f)
    Single(0xD0307053),        RV64, [F, X] => [R(7), R(15)], [Ex_F];
    Single(0xD0307053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zfinx];
],
"fcvt.s.w" = [
    // fcvt.s.w rd, rs1, rm (f)
    Single(0xD0000053), RV32 | RV64, [F, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_F];
    Single(0xD0000053), RV32 | RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfinx];
    // fcvt.s.w rd, rs1 (f)
    Single(0xD0007053), RV32 | RV64, [F, X] => [R(7), R(15)], [Ex_F];
    Single(0xD0007053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zfinx];
],
"fcvt.s.wu" = [
    // fcvt.s.wu rd, rs1, rm (f)
    Single(0xD0100053), RV32 | RV64, [F, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_F];
    Single(0xD0100053), RV32 | RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfinx];
    // fcvt.s.wu rd, rs1 (f)
    Single(0xD0107053), RV32 | RV64, [F, X] => [R(7), R(15)], [Ex_F];
    Single(0xD0107053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zfinx];
],
"fcvt.w.s" = [
    // fcvt.w.s rd, rs1, rm (f)
    Single(0xC0000053), RV32 | RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_F];
    Single(0xC0000053), RV32 | RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfinx];
    // fcvt.w.s rd, rs1 (f)
    Single(0xC0007053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_F];
    Single(0xC0007053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zfinx];
],
"fcvt.wu.s" = [
    // fcvt.wu.s rd, rs1, rm (f)
    Single(0xC0100053), RV32 | RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_F];
    Single(0xC0100053), RV32 | RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfinx];
    // fcvt.wu.s rd, rs1 (f)
    Single(0xC0107053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_F];
    Single(0xC0107053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zfinx];
],
"fdiv.s" = [
    // fdiv.s rd, rs1, rs2, rm (f)
    Single(0x18000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_F];
    Single(0x18000053), RV32 | RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zfinx];
    // fdiv.s rd, rs1, rs2 (f)
    Single(0x18007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0x18007053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"feq.s" = [
    // feq.s rd, rs1, rs2 (f)
    Single(0xA0002053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0xA0002053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"fle.s" = [
    // fle.s rd, rs1, rs2 (f)
    Single(0xA0000053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0xA0000053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"flt.s" = [
    // flt.s rd, rs1, rs2 (f)
    Single(0xA0001053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0xA0001053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"flw" = [
    // flw rd, rs1, imm12 (f)
    Single(0x00002007), RV32 | RV64, [F, RefOffset] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_F];
    // as part of a pc-relative load
    Single(0x00002007), RV32 | RV64, [F, RefLabel] => [R(7), R(15), Offset(LO12)], [Ex_F];
    // Pseudo instruction for auipc rt, hi20(symbol); flw, rd, rt, lo12(symbol)
    Double(0x00000017, 0x00002007), RV32 | RV64, [F, Offset, X] => [R(7+32), Offset(SPLIT32), Rno0(7), Repeat, R(15+32)], [Ex_F];
],
"fmadd.s" = [
    // fmadd.s rd, rs1, rs2, rs3, rm (f)
    Single(0x00000043), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_F];
    Single(0x00000043), RV32 | RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zfinx];
    // fmadd.s rd, rs1, rs2, rs3 (f)
    Single(0x00007043), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_F];
    Single(0x00007043), RV32 | RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zfinx];
],
"fmax.s" = [
    // fmax.s rd, rs1, rs2 (f)
    Single(0x28001053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0x28001053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"fmin.s" = [
    // fmin.s rd, rs1, rs2 (f)
    Single(0x28000053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0x28000053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"fmsub.s" = [
    // fmsub.s rd, rs1, rs2, rs3, rm (f)
    Single(0x00000047), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_F];
    Single(0x00000047), RV32 | RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zfinx];
    // fmsub.s rd, rs1, rs2, rs3 (f)
    Single(0x00007047), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_F];
    Single(0x00007047), RV32 | RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zfinx];
],
"fmul.s" = [
    // fmul.s rd, rs1, rs2, rm (f)
    Single(0x10000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_F];
    Single(0x10000053), RV32 | RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zfinx];
    // fmul.s rd, rs1, rs2 (f)
    Single(0x10007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0x10007053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"fmv.s" = [
    // fmv.s rd, rs1, rs2=rs1 (subformat of rv_f::fsgnj.s) (f)
    Single(0x20000053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_F];
    Single(0x20000053), RV32 | RV64, [X, X] => [R(7), R(15), Repeat, R(20)], [Ex_Zfinx];
],
"fmv.s.x" = [
    // fmv.s.x rd, rs1 (subformat of rv_f::fmv.w.x) (f)
    Single(0xF0000053), RV32 | RV64, [F, X] => [R(7), R(15)], [Ex_F];
],
"fmv.w.x" = [
    // fmv.w.x rd, rs1 (f)
    Single(0xF0000053), RV32 | RV64, [F, X] => [R(7), R(15)], [Ex_F];
],
"fmv.x.s" = [
    // fmv.x.s rd, rs1 (subformat of rv_f::fmv.x.w) (f)
    Single(0xE0000053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_F];
],
"fmv.x.w" = [
    // fmv.x.w rd, rs1 (f)
    Single(0xE0000053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_F];
],
"fneg.s" = [
    // fneg.s rd, rs1, rs2=rs1 (subformat of rv_f::fsgnjn.s) (f)
    Single(0x20001053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_F];
    Single(0x20001053), RV32 | RV64, [X, X] => [R(7), R(15), Repeat, R(20)], [Ex_Zfinx];
],
"fnmadd.s" = [
    // fnmadd.s rd, rs1, rs2, rs3, rm (f)
    Single(0x0000004F), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_F];
    Single(0x0000004F), RV32 | RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zfinx];
    // fnmadd.s rd, rs1, rs2, rs3 (f)
    Single(0x0000704F), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_F];
    Single(0x0000704F), RV32 | RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zfinx];
],
"fnmsub.s" = [
    // fnmsub.s rd, rs1, rs2, rs3, rm (f)
    Single(0x0000004B), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_F];
    Single(0x0000004B), RV32 | RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zfinx];
    // fnmsub.s rd, rs1, rs2, rs3 (f)
    Single(0x0000704B), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_F];
    Single(0x0000704B), RV32 | RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zfinx];
],
"frcsr" = [
    // frcsr rd (subformat of rv_zicsr::csrrs) (f)
    Single(0x00302073), RV32 | RV64, [X] => [R(7)], [Ex_F, Ex_Zfinx];
],
"frflags" = [
    // frflags rd (subformat of rv_zicsr::csrrs) (f)
    Single(0x00102073), RV32 | RV64, [X] => [R(7)], [Ex_F, Ex_Zfinx];
],
"frrm" = [
    // frrm rd (subformat of rv_zicsr::csrrs) (f)
    Single(0x00202073), RV32 | RV64, [X] => [R(7)], [Ex_F, Ex_Zfinx];
],
"fscsr" = [
    // fscsr rd, rs1 (subformat of rv_zicsr::csrrw) (f)
    Single(0x00301073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_F, Ex_Zfinx];
],
"fsflags" = [
    // fsflags rd, rs1 (subformat of rv_zicsr::csrrw) (f)
    Single(0x00101073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_F, Ex_Zfinx];
],
"fsflagsi" = [
    // fsflagsi rd, zimm (subformat of rv_zicsr::csrrwi) (f)
    Single(0x00105073), RV32 | RV64, [X, Imm] => [R(7), UImm(5, 0), BitRange(15, 5, 0), Next], [Ex_F, Ex_Zfinx];
],
"fsgnj.s" = [
    // fsgnj.s rd, rs1, rs2 (f)
    Single(0x20000053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0x20000053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"fsgnjn.s" = [
    // fsgnjn.s rd, rs1, rs2 (f)
    Single(0x20001053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0x20001053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"fsgnjx.s" = [
    // fsgnjx.s rd, rs1, rs2 (f)
    Single(0x20002053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0x20002053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"fsqrt.s" = [
    // fsqrt.s rd, rs1, rm (f)
    Single(0x58000053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_F];
    Single(0x58000053), RV32 | RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfinx];
    // fsqrt.s rd, rs1 (f)
    Single(0x58007053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_F];
    Single(0x58007053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zfinx];
],
"fsrm" = [
    // fsrm rd, rs1 (subformat of rv_zicsr::csrrw) (f)
    Single(0x00201073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_F, Ex_Zfinx];
],
"fsrmi" = [
    // fsrmi rd, zimm (subformat of rv_zicsr::csrrwi) (f)
    Single(0x00205073), RV32 | RV64, [X, Imm] => [R(7), UImm(5, 0), BitRange(15, 5, 0), Next], [Ex_F, Ex_Zfinx];
],
"fsub.s" = [
    // fsub.s rd, rs1, rs2, rm (f)
    Single(0x08000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_F];
    Single(0x08000053), RV32 | RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zfinx];
    // fsub.s rd, rs1, rs2 (f)
    Single(0x08007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_F];
    Single(0x08007053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zfinx];
],
"fsw" = [
    // fsw imm12hi, rs1, rs2, imm12lo (f)
    Single(0x00002027), RV32 | RV64, [F, RefOffset] => [R(20), R(15), SImm(12, 0), BitRange(7, 5, 0), BitRange(25, 7, 5), Next], [Ex_F];
    // as part of a pc-relative store
    Single(0x00002027), RV32 | RV64, [F, RefLabel] => [R(20), R(15), Offset(LO12S)], [Ex_F];
    // Pseudo instruction for auipc rt, hi20(symbol); fsw, rd, rt, lo12(symbol)
    Double(0x00000017, 0x00002027), RV32 | RV64, [F, Offset, X] => [R(20+32), Offset(SPLIT32S), Rno0(7), Repeat, R(15+32)], [Ex_F];
],

// Extension(s) f_zfa

"fleq.s" = [
    // fleq.s rd, rs1, rs2 (f_zfa)
    Single(0xA0004053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_F | Ex_Zfa];
],
"fli.s" = [
    // fli.s rd, rs1 (f_zfa)
    Single(0xF0100053), RV32 | RV64, [F, Imm] => [R(7), FloatingPointImmediate(15)], [Ex_F | Ex_Zfa];
],
"fltq.s" = [
    // fltq.s rd, rs1, rs2 (f_zfa)
    Single(0xA0005053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_F | Ex_Zfa];
],
"fmaxm.s" = [
    // fmaxm.s rd, rs1, rs2 (f_zfa)
    Single(0x28003053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_F | Ex_Zfa];
],
"fminm.s" = [
    // fminm.s rd, rs1, rs2 (f_zfa)
    Single(0x28002053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_F | Ex_Zfa];
],
"fround.s" = [
    // fround.s rd, rs1, rm (f_zfa)
    Single(0x40400053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_F | Ex_Zfa];
    // fround.s rd, rs1 (f_zfa)
    Single(0x40407053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_F | Ex_Zfa];
],
"froundnx.s" = [
    // froundnx.s rd, rs1, rm (f_zfa)
    Single(0x40500053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_F | Ex_Zfa];
    // froundnx.s rd, rs1 (f_zfa)
    Single(0x40507053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_F | Ex_Zfa];
],

// Extension(s) i

"add" = [
    // add rd, rs1, rs2 (i)
    Single(0x00000033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"addi" = [
    // addi rd, rs1, imm12 (i)
    Single(0x00000013), RV32 | RV64, [X, X, Imm] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
    // addi as part of address building
    Single(0x00000013), RV32 | RV64, [X, X, Offset] => [R(7), R(15), Offset(LO12)], [Ex_I];
],
"addiw" = [
    // addiw rd, rs1, imm12 (i)
    Single(0x0000001B),        RV64, [X, X, Imm] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
],
"addw" = [
    // addw rd, rs1, rs2 (i)
    Single(0x0000003B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"and" = [
    // and rd, rs1, rs2 (i)
    Single(0x00007033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"andi" = [
    // andi rd, rs1, imm12 (i)
    Single(0x00007013), RV32 | RV64, [X, X, Imm] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
],
"auipc" = [
    // auipc rd, imm20 (i)
    Single(0x00000017), RV32 | RV64, [X, Offset] => [R(7), Offset(HI20)], [Ex_I];
],
"beq" = [
    // beq bimm12hi, rs1, rs2, bimm12lo (i)
    Single(0x00000063), RV32 | RV64, [X, X, Offset] => [R(15), R(20), Offset(B)], [Ex_I];
],
"beqz" = [
    // beqz bimm12hi, rs1, bimm12lo (subformat of rv_i::beq) (i)
    Single(0x00000063), RV32 | RV64, [X, Offset] => [R(15), Offset(B)], [Ex_I];
],
"bge" = [
    // bge bimm12hi, rs1, rs2, bimm12lo (i)
    Single(0x00005063), RV32 | RV64, [X, X, Offset] => [R(15), R(20), Offset(B)], [Ex_I];
],
"bgeu" = [
    // bgeu bimm12hi, rs1, rs2, bimm12lo (i)
    Single(0x00007063), RV32 | RV64, [X, X, Offset] => [R(15), R(20), Offset(B)], [Ex_I];
],
"bgez" = [
    // bgez bimm12hi, rs1, bimm12lo (subformat of rv_i::bge) (i)
    Single(0x00005063), RV32 | RV64, [X, Offset] => [R(15), Offset(B)], [Ex_I];
],
"bgt" = [
    // bgt bimm12hi, rs2, rs1, bimm12lo (subformat of rv_i::blt) (i)
    Single(0x00004063), RV32 | RV64, [X, X, Offset] => [R(20), R(15), Offset(B)], [Ex_I];
],
"bgtu" = [
    // bgtu bimm12hi, rs2, rs1, bimm12lo (subformat of rv_i::bltu) (i)
    Single(0x00006063), RV32 | RV64, [X, X, Offset] => [R(20), R(15), Offset(B)], [Ex_I];
],
"bgtz" = [
    // bgtz bimm12hi, rs2, bimm12lo (subformat of rv_i::blt) (i)
    Single(0x00004063), RV32 | RV64, [X, Offset] => [R(20), Offset(B)], [Ex_I];
],
"ble" = [
    // ble bimm12hi, rs2, rs1, bimm12lo (subformat of rv_i::bge) (i)
    Single(0x00005063), RV32 | RV64, [X, X, Offset] => [R(20), R(15), Offset(B)], [Ex_I];
],
"bleu" = [
    // bleu bimm12hi, rs2, rs1, bimm12lo (subformat of rv_i::bgeu) (i)
    Single(0x00007063), RV32 | RV64, [X, X, Offset] => [R(20), R(15), Offset(B)], [Ex_I];
],
"blez" = [
    // blez bimm12hi, rs2, bimm12lo (subformat of rv_i::bge) (i)
    Single(0x00005063), RV32 | RV64, [X, Offset] => [R(20), Offset(B)], [Ex_I];
],
"blt" = [
    // blt bimm12hi, rs1, rs2, bimm12lo (i)
    Single(0x00004063), RV32 | RV64, [X, X, Offset] => [R(15), R(20), Offset(B)], [Ex_I];
],
"bltu" = [
    // bltu bimm12hi, rs1, rs2, bimm12lo (i)
    Single(0x00006063), RV32 | RV64, [X, X, Offset] => [R(15), R(20), Offset(B)], [Ex_I];
],
"bltz" = [
    // bltz bimm12hi, rs1, bimm12lo (subformat of rv_i::blt) (i)
    Single(0x00004063), RV32 | RV64, [X, Offset] => [R(15), Offset(B)], [Ex_I];
],
"bne" = [
    // bne bimm12hi, rs1, rs2, bimm12lo (i)
    Single(0x00001063), RV32 | RV64, [X, X, Offset] => [R(15), R(20), Offset(B)], [Ex_I];
],
"bnez" = [
    // bnez bimm12hi, rs1, bimm12lo (subformat of rv_i::bne) (i)
    Single(0x00001063), RV32 | RV64, [X, Offset] => [R(15), Offset(B)], [Ex_I];
],
"call" = [
    // pseudo instruction for auipc x1, imm.roundshift(20); jalr x1, x1, imm & 0xFFF
    Double(0x00000097, 0x000080E7), RV32 | RV64, [Offset] => [Offset(SPLIT32)], [Ex_I];
    // pseudo instruction for auipc rd, imm.roundshift(20); jalr rd, rd, imm & 0xFFF
    Double(0x00000017, 0x00000067), RV32 | RV64, [X, Offset] => [Rno0(7), Repeat, R(7+32), Repeat, R(15+32), Offset(SPLIT32)], [Ex_I];
],
"ebreak" = [
    // ebreak  (i)
    Single(0x00100073), RV32 | RV64, [] => [], [Ex_I];
],
"ecall" = [
    // ecall  (i)
    Single(0x00000073), RV32 | RV64, [] => [], [Ex_I];
],
"fence" = [
    // fence fm, pred, succ, rs1, rd (i)
    Single(0x0000000F), RV32 | RV64, [Ident, Ident] => [FenceSpec(24), FenceSpec(20)], [Ex_I];
    // pseudo-instruction, fence on all memory and i/o
    Single(0x0FF0000F), RV32 | RV64, [] => [], [Ex_I];
],
"fence.tso" = [
    // fence.tso rs1, rd (subformat of rv_i::fence) (i)
    Single(0x8330000F), RV32 | RV64, [] => [], [Ex_I];
],
"j" = [
    // j jimm20 (subformat of rv_i::jal) (i)
    Single(0x0000006F), RV32 | RV64, [Offset] => [Offset(J)], [Ex_I];
],
"jal" = [
    // jal rd, jimm20 (i)
    Single(0x0000006F), RV32 | RV64, [X, Offset] => [R(7), Offset(J)], [Ex_I];
    // jal jimm20 (subformat of rv_i::jal) (i)
    Single(0x000000EF), RV32 | RV64, [Offset] => [Offset(J)], [Ex_I];
],
"jalr" = [
    // jalr rd, rs1, imm12 (i)
    Single(0x00000067), RV32 | RV64, [X, X, Imm] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
    // jalr rd, rs1, imm12 (i)
    Single(0x00000067), RV32 | RV64, [X, X, Offset] => [R(7), R(15), Offset(LO12)], [Ex_I];
    // jalr rs1 (subformat of rv_i::jalr) (i)
    Single(0x000000E7), RV32 | RV64, [X] => [R(15)], [Ex_I];
],
"jump" = [
    // pseudo instruction for auipc xt, imm.roundshift(20); jalr x0, xt, imm & 0xFFF
    Double(0x00000017, 0x00000067), RV32 | RV64, [Offset, X] => [Offset(SPLIT32), Rno0(7), Repeat, R(15+32)], [Ex_I];
],
"jr" = [
    // jr rs1 (subformat of rv_i::jalr) (i)
    Single(0x00000067), RV32 | RV64, [X] => [R(15)], [Ex_I];
],
"la" = [
    // Pseudo instruction for auipc rd, hi20(symbol); addi, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00000013), RV32 | RV64, [X, Offset] => [Rno0(7), Repeat, R(7+32), Repeat, R(15+32), Offset(SPLIT32)], [Ex_I];
],
"lb" = [
    // lb rd, rs1, imm12 (i)
    Single(0x00000003), RV32 | RV64, [X, RefOffset] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
    // as part of a pc-relative load
    Single(0x00000003), RV32 | RV64, [X, RefLabel] => [R(7), R(15), Offset(LO12)], [Ex_I];
    // Pseudo instruction for auipc rd, hi20(symbol); lb, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00000003), RV32 | RV64, [X, Offset] => [Rno0(7), Repeat, R(7+32), Repeat, R(15+32), Offset(SPLIT32)], [Ex_I];
],
"lbu" = [
    // lbu rd, rs1, imm12 (i)
    Single(0x00004003), RV32 | RV64, [X, RefOffset] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
    // as part of a pc-relative load
    Single(0x00004003), RV32 | RV64, [X, RefLabel] => [R(7), R(15), Offset(LO12)], [Ex_I];
    // Pseudo instruction for auipc rd, hi20(symbol); lbu, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00004003), RV32 | RV64, [X, Offset] => [Rno0(7), Repeat, R(7+32), Repeat, R(15+32), Offset(SPLIT32)], [Ex_I];
],
"ld" = [
    // ld rd, rs1, imm12 (i)
    Single(0x00003003),        RV64, [X, RefOffset] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
    // as part of a pc-relative load
    Single(0x00003003),        RV64, [X, RefLabel] => [R(7), R(15), Offset(LO12)], [Ex_I];
    // Pseudo instruction for auipc rd, hi20(symbol); ld, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00003003),        RV64, [X, Offset] => [Rno0(7), Repeat, R(7+32), Repeat, R(15+32), Offset(SPLIT32)], [Ex_I];
],
"lh" = [
    // lh rd, rs1, imm12 (i)
    Single(0x00001003), RV32 | RV64, [X, RefOffset] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
    // as part of a pc-relative load
    Single(0x00001003), RV32 | RV64, [X, RefLabel] => [R(7), R(15), Offset(LO12)], [Ex_I];
    // Pseudo instruction for auipc rd, hi20(symbol); lh, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00001003), RV32 | RV64, [X, Offset] => [Rno0(7), Repeat, R(7+32), Repeat, R(15+32), Offset(SPLIT32)], [Ex_I];
],
"lhu" = [
    // lhu rd, rs1, imm12 (i)
    Single(0x00005003), RV32 | RV64, [X, RefOffset] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
    // as part of a pc-relative load
    Single(0x00005003), RV32 | RV64, [X, RefLabel] => [R(7), R(15), Offset(LO12)], [Ex_I];
    // Pseudo instruction for auipc rd, hi20(symbol); lhu, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00005003), RV32 | RV64, [X, Offset] => [Rno0(7), Repeat, R(7+32), Repeat, R(15+32), Offset(SPLIT32)], [Ex_I];
],
"li" = [
    // alias for
    // lui rd, imm.roundrightshift(12)
    // addi rd, rd, imm & 0xFFF
    Double(0x00000037, 0x00000013), RV32       , [X, Imm] => [
        R(7),
        Repeat, R(7+32), Repeat, R(15+32),
        SImm(32, 0),
        RBitRange(12, 20, 12),
        BitRange(20+32, 12, 0),
        Next
    ], [Ex_I];
    // alias for
    // lui rd, imm.roundrightshift(45)
    // addiw rd, rd, imm >> 33 & 0xFFF
    // slli rd, rd, 11
    // addi rd, rd, imm >> 22 & 0x7FF
    // slli rd, rd, 11
    // addi rd, rd, imm >> 11 & 0x7FF
    // slli rd, rd, 11
    // addi rd, rd, imm & 0x7FF
    Many(&[0x00000037, 0x0000001B, 0x00B01013, 0x00000013, 0x00B01013, 0x00000013, 0x00A01013, 0x00000013]),        RV64, [X, Imm] => [
        R(7),
        Repeat, R(7+32), Repeat, R(15+32),
        Repeat, R(7+64), Repeat, R(15+64),
        Repeat, R(7+96), Repeat, R(15+96),
        Repeat, R(7+128), Repeat, R(15+128),
        Repeat, R(7+160), Repeat, R(15+160),
        Repeat, R(7+192), Repeat, R(15+192),
        Repeat, R(7+224), Repeat, R(15+224),
        BigImm(64),
        RBitRange(12, 20, 44),
        BitRange(20+32, 12, 32),
        BitRange(20+96, 11, 21),
        BitRange(20+160, 11, 10),
        BitRange(20+224, 10, 0),
        Next
    ], [Ex_I];
],
"li.32" = [
    // alias for
    // lui rd, imm.roundrightshift(12)
    // addiw rd, rd, imm & 0xFFF
    Double(0x00000037, 0x0000001B),        RV64, [X, Imm] => [
        R(7),
        Repeat, R(7+32), Repeat, R(15+32),
        SImm(32, 0),
        RBitRange(12, 20, 12),
        BitRange(20+32, 12, 0),
        Next
    ], [Ex_I];
],
"li.12" = [
    // alias for addi rd, x0, imm
    Single(0x00000013), RV32 | RV64, [X, Imm] => [R(7), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
],
"li.43" = [
    // alias for
    // lui rd, imm.roundrightshift(23)
    // addiw rd, rd, imm >> 11 & 0xFFF
    // slli rd, rd, 11
    // addi rd, rd, imm & 0x7FF
    Many(&[0x00000037, 0x0000001B, 0x00B01013, 0x00000013]),        RV64, [X, Imm] => [
        R(7),
        Repeat, R(7+32), Repeat, R(15+32),
        Repeat, R(7+64), Repeat, R(15+64),
        Repeat, R(7+96), Repeat, R(15+96),
        BigImm(43),
        RBitRange(12, 20, 23),
        BitRange(20+32, 12, 11),
        BitRange(20+96, 11, 0),
        Next
    ], [Ex_I];
],
"li.54" = [
    // alias for
    // lui rd, imm.roundrightshift(34) & 0xFFF
    // addiw rd, rd, imm >> 22 & 0xFFF
    // slli rd, rd, 11
    // addi rd, rd, imm >> 11 & 0x7FF
    // slli rd, rd, 11
    // addi rd, rd, imm & 0x7FF
    Many(&[0x00000037, 0x0000001B, 0x00B01013, 0x00000013, 0x00B01013, 0x00000013]),        RV64, [X, Imm] => [
        R(7),
        Repeat, R(7+32), Repeat, R(15+32),
        Repeat, R(7+64), Repeat, R(15+64),
        Repeat, R(7+96), Repeat, R(15+96),
        Repeat, R(7+128), Repeat, R(15+128),
        Repeat, R(7+160), Repeat, R(15+160),
        BigImm(54),
        RBitRange(12, 20, 34),
        BitRange(20+32, 12, 22),
        BitRange(20+96, 11, 11),
        BitRange(20+160, 11, 0),
        Next
    ], [Ex_I];
],
"lui" = [
    // lui rd, imm20 (i)
    Single(0x00000037), RV32 | RV64, [X, Imm] => [R(7), SImm(32, 12), BitRange(12, 20, 12), Next], [Ex_I];
],
"lw" = [
    // lw rd, rs1, imm12 (i)
    Single(0x00002003), RV32 | RV64, [X, RefOffset] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
    // as part of a pc-relative load
    Single(0x00002003), RV32 | RV64, [X, RefLabel] => [R(7), R(15), Offset(LO12)], [Ex_I];
    // Pseudo instruction for auipc rd, hi20(symbol); lw, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00002003), RV32 | RV64, [X, Offset] => [Rno0(7), Repeat, R(7+32), Repeat, R(15+32), Offset(SPLIT32)], [Ex_I];
],
"lwu" = [
    // lwu rd, rs1, imm12 (i)
    Single(0x00006003),        RV64, [X, RefOffset] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
    // as part of a pc-relative load
    Single(0x00006003),        RV64, [X, RefLabel] => [R(7), R(15), Offset(LO12)], [Ex_I];
    // Pseudo instruction for auipc rd, hi20(symbol); lwu, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00006003),        RV64, [X, Offset] => [Rno0(7), Repeat, R(7+32), Repeat, R(15+32), Offset(SPLIT32)], [Ex_I];
],
"mv" = [
    // mv rd, rs1 (subformat of rv_i::addi) (i)
    Single(0x00000013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_I];
],
"neg" = [
    // neg rd, rs1 (subformat of rv_i::sub) (i)
    Single(0x40000033), RV32 | RV64, [X, X] => [R(7), R(20)], [Ex_I];
],
"negw" = [
    // negw rd, rs1 (subformat of rv_i::subw) (i)
    Single(0x4000003B),        RV64, [X, X] => [R(7), R(20)], [Ex_I];
],
"nop" = [
    // nop  (subformat of rv_i::addi) (i)
    Single(0x00000013), RV32 | RV64, [] => [], [Ex_I];
],
"not" = [
    // nop  (subformat of rv_i::xori) (i)
    Single(0xFFF04013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_I];
],
"or" = [
    // or rd, rs1, rs2 (i)
    Single(0x00006033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"ori" = [
    // ori rd, rs1, imm12 (i)
    Single(0x00006013), RV32 | RV64, [X, X, Imm] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
],
"pause" = [
    // pause  (subformat of rv_i::fence) (i)
    Single(0x0100000F), RV32 | RV64, [] => [], [Ex_Zihintpause];
],
"ret" = [
    // ret  (subformat of rv_i::jalr) (i)
    Single(0x00008067), RV32 | RV64, [] => [], [Ex_I];
],
"sb" = [
    // sb imm12hi, rs1, rs2, imm12lo (i)
    Single(0x00000023), RV32 | RV64, [X, RefOffset] => [R(20), R(15), SImm(12, 0), BitRange(7, 5, 0), BitRange(25, 7, 5), Next], [Ex_I];
    // as part of a pc-relative store
    Single(0x00000023), RV32 | RV64, [X, RefLabel] => [R(20), R(15), Offset(LO12S)], [Ex_I];
    // Pseudo instruction for auipc rt, hi20(symbol); sb, rd, rt, lo12(symbol)
    Double(0x00000017, 0x00000023), RV32 | RV64, [X, Offset, X] => [R(20+32), Offset(SPLIT32S), Rno0(7), Repeat, R(15+32)], [Ex_I];
],
"sbreak" = [
    // sbreak  (subformat of rv_i::ebreak) (i)
    Single(0x00100073), RV32 | RV64, [] => [], [Ex_I];
],
"scall" = [
    // scall  (subformat of rv_i::ecall) (i)
    Single(0x00000073), RV32 | RV64, [] => [], [Ex_I];
],
"sd" = [
    // sd imm12hi, rs1, rs2, imm12lo (i)
    Single(0x00003023),        RV64, [X, RefOffset] => [R(20), R(15), SImm(12, 0), BitRange(7, 5, 0), BitRange(25, 7, 5), Next], [Ex_I];
    // as part of a pc-relative store
    Single(0x00003023),        RV64, [X, RefLabel] => [R(20), R(15), Offset(LO12S)], [Ex_I];
    // Pseudo instruction for auipc rt, hi20(symbol); sd, rd, rt, lo12(symbol)
    Double(0x00000017, 0x00003023),        RV64, [X, Offset, X] => [R(20+32), Offset(SPLIT32S), Rno0(7), Repeat, R(15+32)], [Ex_I];
],
"seqz" = [
    // seqz rd, rs1 (subformat of rv_i::sltiu) (i)
    Single(0x00103013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_I];
],
"sext.w" = [
    // sext.w rd, rs1 (subformat of rv64_i::addiw) (i)
    Single(0x0000001B),        RV64, [X, X] => [R(7), R(15)], [Ex_I];
],
"sgtz" = [
    // sgtz rd, rs2 (subformat of rv_i::slt) (i)
    Single(0x00002033), RV32 | RV64, [X, X] => [R(7), R(20)], [Ex_I];
],
"sh" = [
    // sh imm12hi, rs1, rs2, imm12lo (i)
    Single(0x00001023), RV32 | RV64, [X, RefOffset] => [R(20), R(15), SImm(12, 0), BitRange(7, 5, 0), BitRange(25, 7, 5), Next], [Ex_I];
    // as part of a pc-relative store
    Single(0x00001023), RV32 | RV64, [X, RefLabel] => [R(20), R(15), Offset(LO12S)], [Ex_I];
    // Pseudo instruction for auipc rt, hi20(symbol); sh, rd, rt, lo12(symbol)
    Double(0x00000017, 0x00001023), RV32 | RV64, [X, Offset, X] => [R(20+32), Offset(SPLIT32S), Rno0(7), Repeat, R(15+32)], [Ex_I];
],
"sll" = [
    // sll rd, rs1, rs2 (i)
    Single(0x00001033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"slli" = [
    // slli rd, rs1, shamtw (subformat of rv64_i::slli) (i)
    Single(0x00001013), RV32       , [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_I];
    // slli rd, rs1, shamtd (i)
    Single(0x00001013),        RV64, [X, X, Imm] => [R(7), R(15), UImm(6, 0), BitRange(20, 6, 0), Next], [Ex_I];
],
"slliw" = [
    // slliw rd, rs1, shamtw (i)
    Single(0x0000101B),        RV64, [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_I];
],
"sllw" = [
    // sllw rd, rs1, rs2 (i)
    Single(0x0000103B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"slt" = [
    // slt rd, rs1, rs2 (i)
    Single(0x00002033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"slti" = [
    // slti rd, rs1, imm12 (i)
    Single(0x00002013), RV32 | RV64, [X, X, Imm] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
],
"sltiu" = [
    // sltiu rd, rs1, imm12 (i)
    Single(0x00003013), RV32 | RV64, [X, X, Imm] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
],
"sltu" = [
    // sltu rd, rs1, rs2 (i)
    Single(0x00003033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"sltz" = [
    // sltz rd, rs1 (subformat of rv_i::slt) (i)
    Single(0x00002033), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_I];
],
"snez" = [
    // snez rd, rs2 (subformat of rv_i::sltu) (i)
    Single(0x00003033), RV32 | RV64, [X, X] => [R(7), R(20)], [Ex_I];
],
"sra" = [
    // sra rd, rs1, rs2 (i)
    Single(0x40005033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"srai" = [
    // srai rd, rs1, shamtw (subformat of rv64_i::srai) (i)
    Single(0x40005013), RV32       , [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_I];
    // srai rd, rs1, shamtd (i)
    Single(0x40005013),        RV64, [X, X, Imm] => [R(7), R(15), UImm(6, 0), BitRange(20, 6, 0), Next], [Ex_I];
],
"sraiw" = [
    // sraiw rd, rs1, shamtw (i)
    Single(0x4000501B),        RV64, [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_I];
],
"sraw" = [
    // sraw rd, rs1, rs2 (i)
    Single(0x4000503B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"srl" = [
    // srl rd, rs1, rs2 (i)
    Single(0x00005033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"srli" = [
    // srli rd, rs1, shamtw (subformat of rv64_i::srli) (i)
    Single(0x00005013), RV32       , [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_I];
    // srli rd, rs1, shamtd (i)
    Single(0x00005013),        RV64, [X, X, Imm] => [R(7), R(15), UImm(6, 0), BitRange(20, 6, 0), Next], [Ex_I];
],
"srliw" = [
    // srliw rd, rs1, shamtw (i)
    Single(0x0000501B),        RV64, [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_I];
],
"srlw" = [
    // srlw rd, rs1, rs2 (i)
    Single(0x0000503B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"sub" = [
    // sub rd, rs1, rs2 (i)
    Single(0x40000033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"subw" = [
    // subw rd, rs1, rs2 (i)
    Single(0x4000003B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"sw" = [
    // sw imm12hi, rs1, rs2, imm12lo (i)
    Single(0x00002023), RV32 | RV64, [X, RefOffset] => [R(20), R(15), SImm(12, 0), BitRange(7, 5, 0), BitRange(25, 7, 5), Next], [Ex_I];
    // as part of a pc-relative store
    Single(0x00002023), RV32 | RV64, [X, RefLabel] => [R(20), R(15), Offset(LO12S)], [Ex_I];
    // Pseudo instruction for auipc rt, hi20(symbol); sw, rd, rt, lo12(symbol)
    Double(0x00000017, 0x00002023), RV32 | RV64, [X, Offset, X] => [R(20+32), Offset(SPLIT32S), Rno0(7), Repeat, R(15+32)], [Ex_I];
],
"tail" = [
    // pseudo instruction for auipc x7, imm.roundshift(20); jalr x0, x7, imm & 0xFFF
    Double(0x00000397, 0x00038067), RV32 | RV64, [Offset] => [Offset(SPLIT32)], [Ex_Zicfilp];
    // pseudo instruction for auipc x6, imm.roundshift(20); jalr x0, x6, imm & 0xFFF
    Double(0x00000317, 0x00030067), RV32 | RV64, [Offset] => [Offset(SPLIT32)], [Ex_I];
],
"unimp" = [
    // guaranteed to not be a valid instruction (it is a write to a read-only CSR)
    Single(0xC0001073), RV32 | RV64, [] => [], [Ex_I];
],
"xor" = [
    // xor rd, rs1, rs2 (i)
    Single(0x00004033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_I];
],
"xori" = [
    // xori rd, rs1, imm12 (i)
    Single(0x00004013), RV32 | RV64, [X, X, Imm] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_I];
],
"zext.b" = [
    // zext.b rd, rs1 (subformat of rv_i::andi) (i)
    Single(0x0FF07013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_I];
],

// Extension(s) m

"div" = [
    // div rd, rs1, rs2 (m)
    Single(0x02004033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"divu" = [
    // divu rd, rs1, rs2 (m)
    Single(0x02005033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"divuw" = [
    // divuw rd, rs1, rs2 (m)
    Single(0x0200503B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"divw" = [
    // divw rd, rs1, rs2 (m)
    Single(0x0200403B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"mul" = [
    // mul rd, rs1, rs2 (m)
    Single(0x02000033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"mulh" = [
    // mulh rd, rs1, rs2 (m)
    Single(0x02001033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"mulhsu" = [
    // mulhsu rd, rs1, rs2 (m)
    Single(0x02002033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"mulhu" = [
    // mulhu rd, rs1, rs2 (m)
    Single(0x02003033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"mulw" = [
    // mulw rd, rs1, rs2 (m)
    Single(0x0200003B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"rem" = [
    // rem rd, rs1, rs2 (m)
    Single(0x02006033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"remu" = [
    // remu rd, rs1, rs2 (m)
    Single(0x02007033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"remuw" = [
    // remuw rd, rs1, rs2 (m)
    Single(0x0200703B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],
"remw" = [
    // remw rd, rs1, rs2 (m)
    Single(0x0200603B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_M];
],

// Extension(s) q

"fabs.q" = [
    // fabs.q rd, rs1, rs2=rs1 (subformat of rv_q::fsgnjx.q) (q)
    Single(0x26002053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_Q];
],
"fadd.q" = [
    // fadd.q rd, rs1, rs2, rm (q)
    Single(0x06000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Q];
    // fadd.q rd, rs1, rs2 (q)
    Single(0x06007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],
"fclass.q" = [
    // fclass.q rd, rs1 (q)
    Single(0xE6001053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_Q];
],
"fcvt.d.q" = [
    // fcvt.d.q rd, rs1, rm (q)
    Single(0x42300053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Q];
    // fcvt.d.q rd, rs1 (q)
    Single(0x42307053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Q];
],
"fcvt.l.q" = [
    // fcvt.l.q rd, rs1, rm (q)
    Single(0xC6200053),        RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Q];
    // fcvt.l.q rd, rs1 (q)
    Single(0xC6207053),        RV64, [X, F] => [R(7), R(15)], [Ex_Q];
],
"fcvt.lu.q" = [
    // fcvt.lu.q rd, rs1, rm (q)
    Single(0xC6300053),        RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Q];
    // fcvt.lu.q rd, rs1 (q)
    Single(0xC6307053),        RV64, [X, F] => [R(7), R(15)], [Ex_Q];
],
"fcvt.q.d" = [
    // fcvt.q.d rd, rs1 (q)
    Single(0x46100053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Q];
],
"fcvt.q.l" = [
    // fcvt.q.l rd, rs1 (q)
    Single(0xD6200053),        RV64, [F, X] => [R(7), R(15)], [Ex_Q];
],
"fcvt.q.lu" = [
    // fcvt.q.lu rd, rs1 (q)
    Single(0xD6300053),        RV64, [F, X] => [R(7), R(15)], [Ex_Q];
],
"fcvt.q.s" = [
    // fcvt.q.s rd, rs1 (q)
    Single(0x46000053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Q];
],
"fcvt.q.w" = [
    // fcvt.q.w rd, rs1 (q)
    Single(0xD6000053), RV32 | RV64, [F, X] => [R(7), R(15)], [Ex_Q];
],
"fcvt.q.wu" = [
    // fcvt.q.wu rd, rs1 (q)
    Single(0xD6100053), RV32 | RV64, [F, X] => [R(7), R(15)], [Ex_Q];
],
"fcvt.s.q" = [
    // fcvt.s.q rd, rs1, rm (q)
    Single(0x40300053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Q];
    // fcvt.s.q rd, rs1 (q)
    Single(0x40307053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Q];
],
"fcvt.w.q" = [
    // fcvt.w.q rd, rs1, rm (q)
    Single(0xC6000053), RV32 | RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Q];
    // fcvt.w.q rd, rs1 (q)
    Single(0xC6007053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_Q];
],
"fcvt.wu.q" = [
    // fcvt.wu.q rd, rs1, rm (q)
    Single(0xC6100053), RV32 | RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Q];
    // fcvt.wu.q rd, rs1 (q)
    Single(0xC6107053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_Q];
],
"fdiv.q" = [
    // fdiv.q rd, rs1, rs2, rm (q)
    Single(0x1E000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Q];
    // fdiv.q rd, rs1, rs2 (q)
    Single(0x1E007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],
"feq.q" = [
    // feq.q rd, rs1, rs2 (q)
    Single(0xA6002053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],
"fle.q" = [
    // fle.q rd, rs1, rs2 (q)
    Single(0xA6000053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],
"flq" = [
    // flq rd, rs1, imm12 (q)
    Single(0x00004007), RV32 | RV64, [F, RefOffset] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_Q];
    // as part of a pc-relative load
    Single(0x00004007), RV32 | RV64, [F, RefLabel] => [R(7), R(15), Offset(LO12)], [Ex_Q];
    // Pseudo instruction for auipc rd, hi20(symbol); fld, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00004007), RV32 | RV64, [F, Offset, X] => [R(7+32), Offset(SPLIT32), Rno0(7), Repeat, R(15+32)], [Ex_Q];
],
"flt.q" = [
    // flt.q rd, rs1, rs2 (q)
    Single(0xA6001053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],
"fmadd.q" = [
    // fmadd.q rd, rs1, rs2, rs3, rm (q)
    Single(0x06000043), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Q];
    // fmadd.q rd, rs1, rs2, rs3 (q)
    Single(0x06007043), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_Q];
],
"fmax.q" = [
    // fmax.q rd, rs1, rs2 (q)
    Single(0x2E001053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],
"fmin.q" = [
    // fmin.q rd, rs1, rs2 (q)
    Single(0x2E000053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],
"fmsub.q" = [
    // fmsub.q rd, rs1, rs2, rs3, rm (q)
    Single(0x06000047), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Q];
    // fmsub.q rd, rs1, rs2, rs3 (q)
    Single(0x06007047), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_Q];
],
"fmul.q" = [
    // fmul.q rd, rs1, rs2, rm (q)
    Single(0x16000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Q];
    // fmul.q rd, rs1, rs2 (q)
    Single(0x16007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],
"fmv.q" = [
    // fmv.q rd, rs1, rs2=rs1 (subformat of rv_q::fsgnj.q) (q)
    Single(0x26000053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_Q];
],
"fneg.q" = [
    // fneg.q rd, rs1, rs2=rs1 (subformat of rv_q::fsgnjn.q) (q)
    Single(0x26001053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_Q];
],
"fnmadd.q" = [
    // fnmadd.q rd, rs1, rs2, rs3, rm (q)
    Single(0x0600004F), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Q];
    // fnmadd.q rd, rs1, rs2, rs3 (q)
    Single(0x0600704F), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_Q];
],
"fnmsub.q" = [
    // fnmsub.q rd, rs1, rs2, rs3, rm (q)
    Single(0x0600004B), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Q];
    // fnmsub.q rd, rs1, rs2, rs3 (q)
    Single(0x0600704B), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_Q];
],
"fsgnj.q" = [
    // fsgnj.q rd, rs1, rs2 (q)
    Single(0x26000053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],
"fsgnjn.q" = [
    // fsgnjn.q rd, rs1, rs2 (q)
    Single(0x26001053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],
"fsgnjx.q" = [
    // fsgnjx.q rd, rs1, rs2 (q)
    Single(0x26002053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],
"fsq" = [
    // fsq imm12hi, rs1, rs2, imm12lo (q)
    Single(0x00004027), RV32 | RV64, [F, RefOffset] => [R(20), R(15), SImm(12, 0), BitRange(7, 5, 0), BitRange(25, 7, 5), Next], [Ex_Q];
    // as part of a pc-relative load
    Single(0x00004027), RV32 | RV64, [F, RefLabel] => [R(20), R(15), Offset(LO12S)], [Ex_Q];
    // Pseudo instruction for auipc rd, hi20(symbol); fld, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00004027), RV32 | RV64, [F, Offset, X] => [R(20+32), Offset(SPLIT32S), Rno0(7), Repeat, R(15+32)], [Ex_Q];
],
"fsqrt.q" = [
    // fsqrt.q rd, rs1, rm (q)
    Single(0x5E000053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Q];
    // fsqrt.q rd, rs1 (q)
    Single(0x5E007053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Q];
],
"fsub.q" = [
    // fsub.q rd, rs1, rs2, rm (q)
    Single(0x0E000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Q];
    // fsub.q rd, rs1, rs2 (q)
    Single(0x0E007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Q];
],

// Extension(s) q_zfa

"fleq.q" = [
    // fleq.q rd, rs1, rs2 (q_zfa)
    Single(0xA6004053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_Q | Ex_Zfa];
],
"fli.q" = [
    // fli.q rd, rs1 (q_zfa)
    Single(0xF6100053), RV32 | RV64, [F, Imm] => [R(7), FloatingPointImmediate(15)], [Ex_Q | Ex_Zfa];
],
"fltq.q" = [
    // fltq.q rd, rs1, rs2 (q_zfa)
    Single(0xA6005053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_Q | Ex_Zfa];
],
"fmaxm.q" = [
    // fmaxm.q rd, rs1, rs2 (q_zfa)
    Single(0x2E003053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Q | Ex_Zfa];
],
"fminm.q" = [
    // fminm.q rd, rs1, rs2 (q_zfa)
    Single(0x2E002053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Q | Ex_Zfa];
],
"fmvh.x.q" = [
    // fmvh.x.q rd, rs1 (q_zfa)
    Single(0xE6100053),        RV64, [X, F] => [R(7), R(15)], [Ex_Q | Ex_Zfa];
],
"fmvp.q.x" = [
    // fmvp.q.x rd, rs1, rs2 (q_zfa)
    Single(0xB6000053),        RV64, [F, X, X] => [R(7), R(15), R(20)], [Ex_Q | Ex_Zfa];
],
"fround.q" = [
    // fround.q rd, rs1, rm (q_zfa)
    Single(0x46400053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Q | Ex_Zfa];
    // fround.q rd, rs1 (q_zfa)
    Single(0x46407053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Q | Ex_Zfa];
],
"froundnx.q" = [
    // froundnx.q rd, rs1, rm (q_zfa)
    Single(0x46500053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Q | Ex_Zfa];
    // froundnx.q rd, rs1 (q_zfa)
    Single(0x46507053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Q | Ex_Zfa];
],

// Extension(s) q_zfh

"fcvt.h.q" = [
    // fcvt.h.q rd, rs1, rm (q_zfh)
    Single(0x44300053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Q | Ex_Zfh, Ex_Q | Ex_Zfhmin];
    // fcvt.h.q rd, rs1 (q_zfh)
    Single(0x44307053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Q | Ex_Zfh, Ex_Q | Ex_Zfhmin];
],
"fcvt.q.h" = [
    // fcvt.q.h rd, rs1 (q_zfh)
    Single(0x46200053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Q | Ex_Zfh, Ex_Q | Ex_Zfhmin];
],

// Extension(s) zabha

"amoadd.b" = [
    // amoadd.b rd, rs1, rs2, aq, rl (zabha)
    Single(0x0000002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoadd.b.aq" = [
    // amoadd.b.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x0400002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoadd.b.aqrl" = [
    // amoadd.b.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x0600002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoadd.b.rl" = [
    // amoadd.b.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x0200002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoadd.h" = [
    // amoadd.h rd, rs1, rs2, aq, rl (zabha)
    Single(0x0000102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoadd.h.aq" = [
    // amoadd.h.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x0400102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoadd.h.aqrl" = [
    // amoadd.h.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x0600102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoadd.h.rl" = [
    // amoadd.h.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x0200102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoand.b" = [
    // amoand.b rd, rs1, rs2, aq, rl (zabha)
    Single(0x6000002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoand.b.aq" = [
    // amoand.b.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x6400002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoand.b.aqrl" = [
    // amoand.b.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x6600002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoand.b.rl" = [
    // amoand.b.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x6200002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoand.h" = [
    // amoand.h rd, rs1, rs2, aq, rl (zabha)
    Single(0x6000102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoand.h.aq" = [
    // amoand.h.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x6400102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoand.h.aqrl" = [
    // amoand.h.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x6600102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoand.h.rl" = [
    // amoand.h.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x6200102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomax.b" = [
    // amomax.b rd, rs1, rs2, aq, rl (zabha)
    Single(0xA000002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomax.b.aq" = [
    // amomax.b.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0xA400002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomax.b.aqrl" = [
    // amomax.b.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0xA600002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomax.b.rl" = [
    // amomax.b.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0xA200002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomax.h" = [
    // amomax.h rd, rs1, rs2, aq, rl (zabha)
    Single(0xA000102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomax.h.aq" = [
    // amomax.h.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0xA400102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomax.h.aqrl" = [
    // amomax.h.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0xA600102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomax.h.rl" = [
    // amomax.h.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0xA200102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomaxu.b" = [
    // amomaxu.b rd, rs1, rs2, aq, rl (zabha)
    Single(0xE000002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomaxu.b.aq" = [
    // amomaxu.b.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0xE400002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomaxu.b.aqrl" = [
    // amomaxu.b.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0xE600002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomaxu.b.rl" = [
    // amomaxu.b.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0xE200002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomaxu.h" = [
    // amomaxu.h rd, rs1, rs2, aq, rl (zabha)
    Single(0xE000102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomaxu.h.aq" = [
    // amomaxu.h.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0xE400102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomaxu.h.aqrl" = [
    // amomaxu.h.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0xE600102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomaxu.h.rl" = [
    // amomaxu.h.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0xE200102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomin.b" = [
    // amomin.b rd, rs1, rs2, aq, rl (zabha)
    Single(0x8000002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomin.b.aq" = [
    // amomin.b.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x8400002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomin.b.aqrl" = [
    // amomin.b.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x8600002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomin.b.rl" = [
    // amomin.b.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x8200002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomin.h" = [
    // amomin.h rd, rs1, rs2, aq, rl (zabha)
    Single(0x8000102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomin.h.aq" = [
    // amomin.h.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x8400102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomin.h.aqrl" = [
    // amomin.h.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x8600102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amomin.h.rl" = [
    // amomin.h.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x8200102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amominu.b" = [
    // amominu.b rd, rs1, rs2, aq, rl (zabha)
    Single(0xC000002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amominu.b.aq" = [
    // amominu.b.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0xC400002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amominu.b.aqrl" = [
    // amominu.b.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0xC600002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amominu.b.rl" = [
    // amominu.b.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0xC200002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amominu.h" = [
    // amominu.h rd, rs1, rs2, aq, rl (zabha)
    Single(0xC000102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amominu.h.aq" = [
    // amominu.h.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0xC400102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amominu.h.aqrl" = [
    // amominu.h.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0xC600102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amominu.h.rl" = [
    // amominu.h.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0xC200102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoor.b" = [
    // amoor.b rd, rs1, rs2, aq, rl (zabha)
    Single(0x4000002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoor.b.aq" = [
    // amoor.b.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x4400002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoor.b.aqrl" = [
    // amoor.b.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x4600002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoor.b.rl" = [
    // amoor.b.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x4200002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoor.h" = [
    // amoor.h rd, rs1, rs2, aq, rl (zabha)
    Single(0x4000102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoor.h.aq" = [
    // amoor.h.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x4400102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoor.h.aqrl" = [
    // amoor.h.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x4600102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoor.h.rl" = [
    // amoor.h.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x4200102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoswap.b" = [
    // amoswap.b rd, rs1, rs2, aq, rl (zabha)
    Single(0x0800002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoswap.b.aq" = [
    // amoswap.b.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x0C00002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoswap.b.aqrl" = [
    // amoswap.b.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x0E00002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoswap.b.rl" = [
    // amoswap.b.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x0A00002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoswap.h" = [
    // amoswap.h rd, rs1, rs2, aq, rl (zabha)
    Single(0x0800102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoswap.h.aq" = [
    // amoswap.h.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x0C00102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoswap.h.aqrl" = [
    // amoswap.h.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x0E00102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoswap.h.rl" = [
    // amoswap.h.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x0A00102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoxor.b" = [
    // amoxor.b rd, rs1, rs2, aq, rl (zabha)
    Single(0x2000002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoxor.b.aq" = [
    // amoxor.b.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x2400002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoxor.b.aqrl" = [
    // amoxor.b.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x2600002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoxor.b.rl" = [
    // amoxor.b.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x2200002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoxor.h" = [
    // amoxor.h rd, rs1, rs2, aq, rl (zabha)
    Single(0x2000102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoxor.h.aq" = [
    // amoxor.h.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x2400102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoxor.h.aqrl" = [
    // amoxor.h.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x2600102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],
"amoxor.h.rl" = [
    // amoxor.h.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x2200102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha];
],

// Extension(s) zabha_zacas

"amocas.b" = [
    // amocas.b rd, rs1, rs2, aq, rl (zabha)
    Single(0x2800002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha | Ex_Zacas];
],
"amocas.b.aq" = [
    // amocas.b.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x2C00002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha | Ex_Zacas];
],
"amocas.b.aqrl" = [
    // amocas.b.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x2E00002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha | Ex_Zacas];
],
"amocas.b.rl" = [
    // amocas.b.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x2A00002F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha | Ex_Zacas];
],
"amocas.h" = [
    // amocas.h rd, rs1, rs2, aq, rl (zabha)
    Single(0x2800102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha | Ex_Zacas];
],
"amocas.h.rl" = [
    // amocas.h.rl rd, rs1, rs2, aq, rl (zabha)
    Single(0x2A00102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha | Ex_Zacas];
],
"amocas.h.aq" = [
    // amocas.h.aq rd, rs1, rs2, aq, rl (zabha)
    Single(0x2C00102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha | Ex_Zacas];
],
"amocas.h.aqrl" = [
    // amocas.h.aqrl rd, rs1, rs2, aq, rl (zabha)
    Single(0x2E00102F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zabha | Ex_Zacas];
],

// Extension(s) zacas

"amocas.d" = [
    // amocas.d rd, rs1, rs2, aq, rl (zacas)
    Single(0x2800302F), RV32       , [X, X, Ref] => [Reven(7), Reven(20), R(15)], [Ex_Zacas];
    // amocas.d rd, rs1, rs2, aq, rl (zacas)
    Single(0x2800302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zacas];
],
"amocas.d.aq" = [
    // amocas.d.aq rd, rs1, rs2, aq, rl (zacas)
    Single(0x2C00302F), RV32       , [X, X, Ref] => [Reven(7), Reven(20), R(15)], [Ex_Zacas];
    // amocas.d.aq rd, rs1, rs2, aq, rl (zacas)
    Single(0x2C00302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zacas];
],
"amocas.d.aqrl" = [
    // amocas.d.aqrl rd, rs1, rs2, aq, rl (zacas)
    Single(0x2E00302F), RV32       , [X, X, Ref] => [Reven(7), Reven(20), R(15)], [Ex_Zacas];
    // amocas.d.aqrl rd, rs1, rs2, aq, rl (zacas)
    Single(0x2E00302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zacas];
],
"amocas.d.rl" = [
    // amocas.d.rl rd, rs1, rs2, aq, rl (zacas)
    Single(0x2A00302F), RV32       , [X, X, Ref] => [Reven(7), Reven(20), R(15)], [Ex_Zacas];
    // amocas.d.rl rd, rs1, rs2, aq, rl (zacas)
    Single(0x2A00302F),        RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zacas];
],
"amocas.q" = [
    // amocas.q rd, rs1, rs2, aq, rl (zacas)
    Single(0x2800402F),        RV64, [X, X, Ref] => [Reven(7), Reven(20), R(15)], [Ex_Zacas];
],
"amocas.q.aq" = [
    // amocas.q.aq rd, rs1, rs2, aq, rl (zacas)
    Single(0x2C00402F),        RV64, [X, X, Ref] => [Reven(7), Reven(20), R(15)], [Ex_Zacas];
],
"amocas.q.aqrl" = [
    // amocas.q.aqrl rd, rs1, rs2, aq, rl (zacas)
    Single(0x2E00402F),        RV64, [X, X, Ref] => [Reven(7), Reven(20), R(15)], [Ex_Zacas];
],
"amocas.q.rl" = [
    // amocas.q.rl rd, rs1, rs2, aq, rl (zacas)
    Single(0x2A00402F),        RV64, [X, X, Ref] => [Reven(7), Reven(20), R(15)], [Ex_Zacas];
],
"amocas.w" = [
    // amocas.w rd, rs1, rs2, aq, rl (zacas)
    Single(0x2800202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zacas];
],
"amocas.w.aq" = [
    // amocas.w.aq rd, rs1, rs2, aq, rl (zacas)
    Single(0x2C00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zacas];
],
"amocas.w.aqrl" = [
    // amocas.w.aqrl rd, rs1, rs2, aq, rl (zacas)
    Single(0x2E00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zacas];
],
"amocas.w.rl" = [
    // amocas.w.rl rd, rs1, rs2, aq, rl (zacas)
    Single(0x2A00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zacas];
],

// Extension(s) zawrs

"wrs.nto" = [
    // wrs.nto  (zawrs)
    Single(0x00D00073), RV32 | RV64, [] => [], [Ex_Zawrs];
],
"wrs.sto" = [
    // wrs.sto  (zawrs)
    Single(0x01D00073), RV32 | RV64, [] => [], [Ex_Zawrs];
],

// Extension(s) zba

"add.uw" = [
    // add.uw rd, rs1, rs2 (zba)
    Single(0x0800003B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zba];
],
"sh1add" = [
    // sh1add rd, rs1, rs2 (zba)
    Single(0x20002033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zba];
],
"sh1add.uw" = [
    // sh1add.uw rd, rs1, rs2 (zba)
    Single(0x2000203B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zba];
],
"sh2add" = [
    // sh2add rd, rs1, rs2 (zba)
    Single(0x20004033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zba];
],
"sh2add.uw" = [
    // sh2add.uw rd, rs1, rs2 (zba)
    Single(0x2000403B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zba];
],
"sh3add" = [
    // sh3add rd, rs1, rs2 (zba)
    Single(0x20006033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zba];
],
"sh3add.uw" = [
    // sh3add.uw rd, rs1, rs2 (zba)
    Single(0x2000603B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zba];
],
"slli.uw" = [
    // slli.uw rd, rs1, shamtd (zba)
    Single(0x0800101B),        RV64, [X, X, Imm] => [R(7), R(15), UImm(6, 0), BitRange(20, 6, 0), Next], [Ex_Zba];
],
"zext.w" = [
    // zext.w rd, rs1 (subformat of rv64_zba::add.uw) (zba)
    Single(0x0800003B),        RV64, [X, X] => [R(7), R(15)], [Ex_Zba];
    // alias for slli rd, rs, 32; srli rd, rd, 32
    Double(0x02001013, 0x02005013),       RV64, [X, X] => [R(7), Repeat, R(7+32), Repeat, R(15+32), R(15)], [Ex_I];
],

// Extension(s) zbb

"clz" = [
    // clz rd, rs1 (zbb)
    Single(0x60001013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zbb];
],
"clzw" = [
    // clzw rd, rs1 (zbb)
    Single(0x6000101B),        RV64, [X, X] => [R(7), R(15)], [Ex_Zbb];
],
"cpop" = [
    // cpop rd, rs1 (zbb)
    Single(0x60201013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zbb];
],
"cpopw" = [
    // cpopw rd, rs1 (zbb)
    Single(0x6020101B),        RV64, [X, X] => [R(7), R(15)], [Ex_Zbb];
],
"ctz" = [
    // ctz rd, rs1 (zbb)
    Single(0x60101013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zbb];
],
"ctzw" = [
    // ctzw rd, rs1 (zbb)
    Single(0x6010101B),        RV64, [X, X] => [R(7), R(15)], [Ex_Zbb];
],
"max" = [
    // max rd, rs1, rs2 (zbb)
    Single(0x0A006033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbb];
],
"maxu" = [
    // maxu rd, rs1, rs2 (zbb)
    Single(0x0A007033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbb];
],
"min" = [
    // min rd, rs1, rs2 (zbb)
    Single(0x0A004033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbb];
],
"minu" = [
    // minu rd, rs1, rs2 (zbb)
    Single(0x0A005033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbb];
],
"orc.b" = [
    // orc.b rd, rs1 (subformat of rv64_zbp::gorci) (zbb)
    Single(0x28705013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zbb];
],
"sext.b" = [
    // sext.b rd, rs1 (zbb)
    Single(0x60401013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zbb];
    // alias for slli rd, rs, 24; srai rd, rd, 24
    Double(0x01801013, 0x41805013), RV32      , [X, X] => [R(7), Repeat, R(7+32), Repeat, R(15+32), R(15)], [Ex_I];
    // alias for slli rd, rs, 56; srai rd, rd, 56
    Double(0x03801013, 0x43805013),       RV64, [X, X] => [R(7), Repeat, R(7+32), Repeat, R(15+32), R(15)], [Ex_I];
],
"sext.h" = [
    // sext.h rd, rs1 (zbb)
    Single(0x60501013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zbb];
    // alias for slli rd, rs, 16; srai rd, rd, 16
    Double(0x01001013, 0x41005013), RV32      , [X, X] => [R(7), Repeat, R(7+32), Repeat, R(15+32), R(15)], [Ex_I];
    // alias for slli rd, rs, 48; srai rd, rd, 48
    Double(0x03001013, 0x43005013),       RV64, [X, X] => [R(7), Repeat, R(7+32), Repeat, R(15+32), R(15)], [Ex_I];
],
"zext.h" = [
    // zext.h rd, rs1 (subformat of rv_zbkb::pack) (zbb)
    Single(0x08004033), RV32       , [X, X] => [R(7), R(15)], [Ex_Zbb];
    // zext.h rd, rs1 (subformat of rv64_zbkb::packw) (zbb)
    Single(0x0800403B),        RV64, [X, X] => [R(7), R(15)], [Ex_Zbb];
    // alias for slli rd, rs, 16; srli rd, rd, 16
    Double(0x01001013, 0x01005013), RV32      , [X, X] => [R(7), Repeat, R(7+32), Repeat, R(15+32), R(15)], [Ex_I];
    // alias for slli rd, rs, 48; srli rd, rd, 48
    Double(0x03001013, 0x03005013),       RV64, [X, X] => [R(7), Repeat, R(7+32), Repeat, R(15+32), R(15)], [Ex_I];
],

// Extension(s) zbb, zbkb, zk, zkn, zks

"andn" = [
    // andn rd, rs1, rs2 (zbb, zbkb, zk, zkn, zks)
    Single(0x40007033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"orn" = [
    // orn rd, rs1, rs2 (zbb, zbkb, zk, zkn, zks)
    Single(0x40006033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"rev8" = [
    // rev8 rd, rs1 (subformat of rv64_zbp::grevi) (zbb, zbkb, zk, zkn, zks)
    Single(0x69805013), RV32       , [X, X] => [R(7), R(15)], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
    // rev8 rd, rs1 (subformat of rv64_zbp::grevi) (zbb, zbkb, zk, zkn, zks)
    Single(0x6B805013),        RV64, [X, X] => [R(7), R(15)], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"rol" = [
    // rol rd, rs1, rs2 (zbb, zbkb, zk, zkn, zks)
    Single(0x60001033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"rolw" = [
    // rolw rd, rs1, rs2 (zbb, zbkb, zk, zkn, zks)
    Single(0x6000103B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"ror" = [
    // ror rd, rs1, rs2 (zbb, zbkb, zk, zkn, zks)
    Single(0x60005033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"rori" = [
    // rori rd, rs1, shamtw (subformat of rv64_zbb::rori) (zbb, zbkb, zk, zkn, zks)
    Single(0x60005013), RV32       , [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
    // rori rd, rs1, shamtd (zbb, zbkb, zk, zkn, zks)
    Single(0x60005013),        RV64, [X, X, Imm] => [R(7), R(15), UImm(6, 0), BitRange(20, 6, 0), Next], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"roriw" = [
    // roriw rd, rs1, shamtw (zbb, zbkb, zk, zkn, zks)
    Single(0x6000501B),        RV64, [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"rorw" = [
    // rorw rd, rs1, rs2 (zbb, zbkb, zk, zkn, zks)
    Single(0x6000503B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"xnor" = [
    // xnor rd, rs1, rs2 (zbb, zbkb, zk, zkn, zks)
    Single(0x40004033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbb, Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],

// Extension(s) zbc

"clmulr" = [
    // clmulr rd, rs1, rs2 (zbc)
    Single(0x0A002033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbc];
],

// Extension(s) zbc, zbkc, zk, zkn, zks

"clmul" = [
    // clmul rd, rs1, rs2 (zbc, zbkc, zk, zkn, zks)
    Single(0x0A001033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbc, Ex_Zbkc, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"clmulh" = [
    // clmulh rd, rs1, rs2 (zbc, zbkc, zk, zkn, zks)
    Single(0x0A003033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbc, Ex_Zbkc, Ex_Zk, Ex_Zkn, Ex_Zks];
],

// Extension(s) zbkb, zk, zkn, zks

"brev8" = [
    // brev8 rd, rs1 (subformat of rv64_zbp::grevi) (zbkb, zk, zkn, zks)
    Single(0x68705013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"pack" = [
    // pack rd, rs1, rs2 (zbkb, zk, zkn, zks)
    Single(0x08004033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"packh" = [
    // packh rd, rs1, rs2 (zbkb, zk, zkn, zks)
    Single(0x08007033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"packw" = [
    // packw rd, rs1, rs2 (zbkb, zk, zkn, zks)
    Single(0x0800403B),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"unzip" = [
    // unzip rd, rs1 (subformat of rv64_zbp::unshfli) (zbkb, zk, zkn, zks)
    Single(0x08F05013), RV32       , [X, X] => [R(7), R(15)], [Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"zip" = [
    // zip rd, rs1 (subformat of rv64_zbp::shfli) (zbkb, zk, zkn, zks)
    Single(0x08F01013), RV32       , [X, X] => [R(7), R(15)], [Ex_Zbkb, Ex_Zk, Ex_Zkn, Ex_Zks];
],

// Extension(s) zbkx, zk, zkn, zks

"xperm4" = [
    // xperm4 rd, rs1, rs2 (zbkx, zk, zkn, zks)
    Single(0x28002033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbkx, Ex_Zk, Ex_Zkn, Ex_Zks];
],
"xperm8" = [
    // xperm8 rd, rs1, rs2 (zbkx, zk, zkn, zks)
    Single(0x28004033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbkx, Ex_Zk, Ex_Zkn, Ex_Zks];
],

// Extension(s) zbs

"bclr" = [
    // bclr rd, rs1, rs2 (zbs)
    Single(0x48001033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbs];
],
"bclri" = [
    // bclri rd, rs1, shamtw (subformat of rv64_zbs::bclri) (zbs)
    Single(0x48001013), RV32       , [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_Zbs];
    // bclri rd, rs1, shamtd (zbs)
    Single(0x48001013),        RV64, [X, X, Imm] => [R(7), R(15), UImm(6, 0), BitRange(20, 6, 0), Next], [Ex_Zbs];
],
"bext" = [
    // bext rd, rs1, rs2 (zbs)
    Single(0x48005033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbs];
],
"bexti" = [
    // bexti rd, rs1, shamtw (subformat of rv64_zbs::bexti) (zbs)
    Single(0x48005013), RV32       , [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_Zbs];
    // bexti rd, rs1, shamtd (zbs)
    Single(0x48005013),        RV64, [X, X, Imm] => [R(7), R(15), UImm(6, 0), BitRange(20, 6, 0), Next], [Ex_Zbs];
],
"binv" = [
    // binv rd, rs1, rs2 (zbs)
    Single(0x68001033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbs];
],
"binvi" = [
    // binvi rd, rs1, shamtw (subformat of rv64_zbs::binvi) (zbs)
    Single(0x68001013), RV32       , [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_Zbs];
    // binvi rd, rs1, shamtd (zbs)
    Single(0x68001013),        RV64, [X, X, Imm] => [R(7), R(15), UImm(6, 0), BitRange(20, 6, 0), Next], [Ex_Zbs];
],
"bset" = [
    // bset rd, rs1, rs2 (zbs)
    Single(0x28001033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zbs];
],
"bseti" = [
    // bseti rd, rs1, shamtw (subformat of rv64_zbs::bseti) (zbs)
    Single(0x28001013), RV32       , [X, X, Imm] => [R(7), R(15), UImm(5, 0), BitRange(20, 5, 0), Next], [Ex_Zbs];
    // bseti rd, rs1, shamtd (zbs)
    Single(0x28001013),        RV64, [X, X, Imm] => [R(7), R(15), UImm(6, 0), BitRange(20, 6, 0), Next], [Ex_Zbs];
],

// Extension(s) zcb

"c.lbu" = [
    // c.lbu rd_p, rs1_p, c_uimm2 (zcb)
    Compressed(0x8000), RV32 | RV64, [X, RefOffset] => [Rpop(2), Rpop(7), UImm(2, 0), BitRange(6, 1, 0), BitRange(5, 1, 1), Next], [Ex_Zcb];
],
"c.lh" = [
    // c.lh rd_p, rs1_p, c_uimm1 (zcb)
    Compressed(0x8440), RV32 | RV64, [X, RefOffset] => [Rpop(2), Rpop(7), UImm(2, 1), BitRange(5, 1, 1), Next], [Ex_Zcb];
],
"c.lhu" = [
    // c.lhu rd_p, rs1_p, c_uimm1 (zcb)
    Compressed(0x8400), RV32 | RV64, [X, RefOffset] => [Rpop(2), Rpop(7), UImm(2, 1), BitRange(5, 1, 1), Next], [Ex_Zcb];
],
"c.not" = [
    // c.not rd_rs1_p (zcb)
    Compressed(0x9C75), RV32 | RV64, [X] => [Rpop(7)], [Ex_Zcb];
],
"c.sb" = [
    // c.sb rs2_p, rs1_p, c_uimm2 (zcb)
    Compressed(0x8800), RV32 | RV64, [X, RefOffset] => [Rpop(2), Rpop(7), UImm(2, 0), BitRange(6, 1, 0), BitRange(5, 1, 1), Next], [Ex_Zcb];
],
"c.sh" = [
    // c.sh rs2_p, rs1_p, c_uimm1 (zcb)
    Compressed(0x8C00), RV32 | RV64, [X, RefOffset] => [Rpop(2), Rpop(7), UImm(2, 1), BitRange(5, 1, 1), Next], [Ex_Zbb | Ex_Zcb];
],
"c.zext.b" = [
    // c.zext.b rd_rs1_p (zcb)
    Compressed(0x9C61), RV32 | RV64, [X] => [Rpop(7)], [Ex_Zcb];
],

// Extension(s) zbb_zcb

"c.sext.b" = [
    // c.sext.b rd_rs1_p (zcb)
    Compressed(0x9C65), RV32 | RV64, [X] => [Rpop(7)], [Ex_Zbb | Ex_Zcb];
],
"c.sext.h" = [
    // c.sext.h rd_rs1_p (zcb)
    Compressed(0x9C6D), RV32 | RV64, [X] => [Rpop(7)], [Ex_Zbb | Ex_Zcb];
],
"c.sext.w" = [
    // c.sext.w rd_rs1_n0 (subformat of rv64_c::c.addiw) (zcb)
    Compressed(0x2001),        RV64, [X] => [Rno0(7)], [Ex_Zbb | Ex_Zcb];
],
"c.zext.h" = [
    // c.zext.h rd_rs1_p (zcb)
    Compressed(0x9C69), RV32 | RV64, [X] => [Rpop(7)], [Ex_Zbb | Ex_Zcb];
],

// Extension(s) zba_zcb

"c.zext.w" = [
    // c.zext.w rd_rs1_p (zcb)
    Compressed(0x9C71),        RV64, [X] => [Rpop(7)], [Ex_Zba | Ex_Zcb];
],

// Extension(s) m_zcb
"c.mul" = [
    // c.mul rd_rs1_p, rs2_p (zcb)
    Compressed(0x9C41), RV32 | RV64, [X, X] => [Rpop(7), Rpop(2)], [Ex_Zcb | Ex_M];
],

// Extension(s) zcmop

"c.mop.1" = [
    // c.mop.1  (subformat of rv_zcmop::c.mop.N) (zcmop)
    Compressed(0x6081), RV32 | RV64, [] => [], [Ex_Zcmop];
],
"c.mop.11" = [
    // c.mop.11  (subformat of rv_zcmop::c.mop.N) (zcmop)
    Compressed(0x6581), RV32 | RV64, [] => [], [Ex_Zcmop];
],
"c.mop.13" = [
    // c.mop.13  (subformat of rv_zcmop::c.mop.N) (zcmop)
    Compressed(0x6681), RV32 | RV64, [] => [], [Ex_Zcmop];
],
"c.mop.15" = [
    // c.mop.15  (subformat of rv_zcmop::c.mop.N) (zcmop)
    Compressed(0x6781), RV32 | RV64, [] => [], [Ex_Zcmop];
],
"c.mop.3" = [
    // c.mop.3  (subformat of rv_zcmop::c.mop.N) (zcmop)
    Compressed(0x6181), RV32 | RV64, [] => [], [Ex_Zcmop];
],
"c.mop.5" = [
    // c.mop.5  (subformat of rv_zcmop::c.mop.N) (zcmop)
    Compressed(0x6281), RV32 | RV64, [] => [], [Ex_Zcmop];
],
"c.mop.7" = [
    // c.mop.7  (subformat of rv_zcmop::c.mop.N) (zcmop)
    Compressed(0x6381), RV32 | RV64, [] => [], [Ex_Zcmop];
],
"c.mop.9" = [
    // c.mop.9  (subformat of rv_zcmop::c.mop.N) (zcmop)
    Compressed(0x6481), RV32 | RV64, [] => [], [Ex_Zcmop];
],
"c.mop.N" = [
    // c.mop.N c_mop_t (zcmop)
    Compressed(0x6081), RV32 | RV64, [Imm] => [UImmOdd(4, 1), BitRange(8, 3, 1), Next], [Ex_Zcmop];
],

// Extension(s) zcmp

"cm.mva01s" = [
    // cm.mva01s c_sreg1, c_sreg2 (zcmp)
    Compressed(0xAC62), RV32 | RV64, [X, X] => [Rpops(7), Rpops(2)], [Ex_Zcmp];
],
"cm.mvsa01" = [
    // cm.mvsa01 c_sreg1, c_sreg2 (zcmp)
    Compressed(0xAC22), RV32 | RV64, [X, X] => [Rpops(7), Rpops2(2)], [Ex_Zcmp];
],
"cm.pop" = [
    // cm.pop c_rlist, c_spimm (zcmp)
    Compressed(0xBA02), RV32 | RV64, [Xlist, Imm] => [Rlist(4), SPImm(2, false)], [Ex_Zcmp];
],
"cm.popret" = [
    // cm.popret c_rlist, c_spimm (zcmp)
    Compressed(0xBE02), RV32 | RV64, [Xlist, Imm] => [Rlist(4), SPImm(2, false)], [Ex_Zcmp];
],
"cm.popretz" = [
    // cm.popretz c_rlist, c_spimm (zcmp)
    Compressed(0xBC02), RV32 | RV64, [Xlist, Imm] => [Rlist(4), SPImm(2, false)], [Ex_Zcmp];
],
"cm.push" = [
    // cm.push c_rlist, c_spimm (zcmp)
    Compressed(0xB802), RV32 | RV64, [Xlist, Imm] => [Rlist(4), SPImm(2, true)], [Ex_Zcmp];
],

// Extension(s) zcmt

"cm.jalt" = [
    // cm.jalt c_index (zcmt)
    Compressed(0xA002), RV32 | RV64, [Imm] => [UImmRange(32, 255), BitRange(2, 8, 0), Next], [Ex_Zcmt];
],
"cm.jt" = [
    // cm.jalt c_index (zcmt)
    Compressed(0xA002), RV32 | RV64, [Imm] => [UImmRange(0, 31), BitRange(2, 8, 0), Next], [Ex_Zcmt];
],

// Extension(s) zfa_zfh

"fleq.h" = [
    // fleq.h rd, rs1, rs2 (zfa_zfh)
    Single(0xA4004053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_Zfa | Ex_Zfh];
],
"fli.h" = [
    // fli.h rd, rs1 (zfa_zfh)
    Single(0xF4100053), RV32 | RV64, [F, Imm] => [R(7), FloatingPointImmediate(15)], [Ex_Zfa | Ex_Zfh];
],
"fltq.h" = [
    // fltq.h rd, rs1, rs2 (zfa_zfh)
    Single(0xA4005053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_Zfa | Ex_Zfh];
],
"fmaxm.h" = [
    // fmaxm.h rd, rs1, rs2 (zfa_zfh)
    Single(0x2C003053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Zfa | Ex_Zfh];
],
"fminm.h" = [
    // fminm.h rd, rs1, rs2 (zfa_zfh)
    Single(0x2C002053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Zfa | Ex_Zfh];
],
"fround.h" = [
    // fround.h rd, rs1, rm (zfa_zfh)
    Single(0x44400053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfa | Ex_Zfh];
    // fround.h rd, rs1 (zfa_zfh)
    Single(0x44407053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Zfa | Ex_Zfh];
],
"froundnx.h" = [
    // froundnx.h rd, rs1, rm (zfa_zfh)
    Single(0x44500053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfa | Ex_Zfh];
    // froundnx.h rd, rs1 (zfa_zfh)
    Single(0x44507053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Zfa | Ex_Zfh];
],

// Extension(s) zfbfmin

"fcvt.bf16.s" = [
    // fcvt.bf16.s rd, rs1, rm (zfbfmin)
    Single(0x44800053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfbfmin];
    // fcvt.bf16.s rd, rs1 (zfbfmin)
    Single(0x44807053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Zfbfmin];
],
"fcvt.s.bf16" = [
    // fcvt.s.bf16 rd, rs1 (zfbfmin)
    Single(0x40600053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Zfbfmin];
],

// Extension(s) zfh

"fabs.h" = [
    // fabs.h rd, rs1, rs2=rs1 (subformat of rv_zfh::fsgnjx.h) (zfh)
    Single(0x24002053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_Zfh];
    Single(0x24002053), RV32 | RV64, [X, X] => [R(7), R(15), Repeat, R(20)], [Ex_Zhinx];
],
"fadd.h" = [
    // fadd.h rd, rs1, rs2, rm (zfh)
    Single(0x04000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zfh];
    Single(0x04000053), RV32 | RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zhinx];
    // fadd.h rd, rs1, rs2 (zfh)
    Single(0x04007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0x04007053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],
"fclass.h" = [
    // fclass.h rd, rs1 (zfh)
    Single(0xE4001053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_Zfh];
    Single(0xE4001053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx];
],
"fcvt.h.l" = [
    // fcvt.h.l rd, rs1, rm (zfh)
    Single(0xD4200053),        RV64, [F, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfh];
    Single(0xD4200053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zhinx];
    // fcvt.h.l rd, rs1 (zfh)
    Single(0xD4207053),        RV64, [F, X] => [R(7), R(15)], [Ex_Zfh];
    Single(0xD4207053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx];
],
"fcvt.h.lu" = [
    // fcvt.h.lu rd, rs1, rm (zfh)
    Single(0xD4300053),        RV64, [F, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfh];
    Single(0xD4300053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zhinx];
    // fcvt.h.lu rd, rs1 (zfh)
    Single(0xD4307053),        RV64, [F, X] => [R(7), R(15)], [Ex_Zfh];
    Single(0xD4307053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx];
],
"fcvt.h.s" = [
    // fcvt.h.s rd, rs1, rm (zfh)
    Single(0x44000053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfh, Ex_Zfhmin];
    Single(0x44000053), RV32 | RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zhinx, Ex_Zhinxmin];
    // fcvt.h.s rd, rs1 (zfh)
    Single(0x44007053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Zfh, Ex_Zfhmin];
    Single(0x44007053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx, Ex_Zhinxmin];
],
"fcvt.h.w" = [
    // fcvt.h.w rd, rs1, rm (zfh)
    Single(0xD4000053), RV32 | RV64, [F, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfh];
    Single(0xD4000053), RV32 | RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zhinx];
    // fcvt.h.w rd, rs1 (zfh)
    Single(0xD4007053), RV32 | RV64, [F, X] => [R(7), R(15)], [Ex_Zfh];
    Single(0xD4007053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx];
],
"fcvt.h.wu" = [
    // fcvt.h.wu rd, rs1, rm (zfh)
    Single(0xD4100053), RV32 | RV64, [F, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfh];
    Single(0xD4100053), RV32 | RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zhinx];
    // fcvt.h.wu rd, rs1 (zfh)
    Single(0xD4107053), RV32 | RV64, [F, X] => [R(7), R(15)], [Ex_Zfh];
    Single(0xD4107053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx];
],
"fcvt.l.h" = [
    // fcvt.l.h rd, rs1, rm (zfh)
    Single(0xC4200053),        RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfh];
    Single(0xC4200053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zhinx];
    // fcvt.l.h rd, rs1 (zfh)
    Single(0xC4207053),        RV64, [X, F] => [R(7), R(15)], [Ex_Zfh];
    Single(0xC4207053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx];
],
"fcvt.lu.h" = [
    // fcvt.lu.h rd, rs1, rm (zfh)
    Single(0xC4300053),        RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfh];
    Single(0xC4300053),        RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zhinx];
    // fcvt.lu.h rd, rs1 (zfh)
    Single(0xC4307053),        RV64, [X, F] => [R(7), R(15)], [Ex_Zfh];
    Single(0xC4307053),        RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx];
],
"fcvt.s.h" = [
    // fcvt.s.h rd, rs1 (zfh)
    Single(0x40200053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Zfh, Ex_Zfhmin];
    Single(0x40200053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx, Ex_Zhinxmin];
],
"fcvt.w.h" = [
    // fcvt.w.h rd, rs1, rm (zfh)
    Single(0xC4000053), RV32 | RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfh];
    Single(0xC4000053), RV32 | RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zhinx];
    // fcvt.w.h rd, rs1 (zfh)
    Single(0xC4007053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_Zfh];
    Single(0xC4007053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx];
],
"fcvt.wu.h" = [
    // fcvt.wu.h rd, rs1, rm (zfh)
    Single(0xC4100053), RV32 | RV64, [X, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfh];
    Single(0xC4100053), RV32 | RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zhinx];
    // fcvt.wu.h rd, rs1 (zfh)
    Single(0xC4107053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_Zfh];
    Single(0xC4107053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx];
],
"fdiv.h" = [
    // fdiv.h rd, rs1, rs2, rm (zfh)
    Single(0x1C000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zfh];
    Single(0x1C000053), RV32 | RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zhinx];
    // fdiv.h rd, rs1, rs2 (zfh)
    Single(0x1C007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0x1C007053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],
"feq.h" = [
    // feq.h rd, rs1, rs2 (zfh)
    Single(0xA4002053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0xA4002053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],
"fle.h" = [
    // fle.h rd, rs1, rs2 (zfh)
    Single(0xA4000053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0xA4000053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],
"flh" = [
    // flh rd, rs1, imm12 (zfh)
    Single(0x00001007), RV32 | RV64, [F, RefOffset] => [R(7), R(15), SImm(12, 0), BitRange(20, 12, 0), Next], [Ex_Zfh, Ex_Zfhmin];
    // as part of a pc-relative load
    Single(0x00001007), RV32 | RV64, [F, RefLabel] => [R(7), R(15), Offset(LO12)], [Ex_Zfh, Ex_Zfhmin];
    // Pseudo instruction for auipc rd, hi20(symbol); flh, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00001007), RV32 | RV64, [F, Offset, X] => [R(7+32), Offset(SPLIT32), Rno0(7), Repeat, R(15+32)], [Ex_Zfh, Ex_Zfhmin];
],
"flt.h" = [
    // flt.h rd, rs1, rs2 (zfh)
    Single(0xA4001053), RV32 | RV64, [X, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0xA4001053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],
"fmadd.h" = [
    // fmadd.h rd, rs1, rs2, rs3, rm (zfh)
    Single(0x04000043), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zfh];
    Single(0x04000043), RV32 | RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zhinx];
    // fmadd.h rd, rs1, rs2, rs3 (zfh)
    Single(0x04007043), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_Zfh];
    Single(0x04007043), RV32 | RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zhinx];
],
"fmax.h" = [
    // fmax.h rd, rs1, rs2 (zfh)
    Single(0x2C001053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0x2C001053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],
"fmin.h" = [
    // fmin.h rd, rs1, rs2 (zfh)
    Single(0x2C000053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0x2C000053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],
"fmsub.h" = [
    // fmsub.h rd, rs1, rs2, rs3, rm (zfh)
    Single(0x04000047), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zfh];
    Single(0x04000047), RV32 | RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zhinx];
    // fmsub.h rd, rs1, rs2, rs3 (zfh)
    Single(0x04007047), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_Zfh];
    Single(0x04007047), RV32 | RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zhinx];
],
"fmul.h" = [
    // fmul.h rd, rs1, rs2, rm (zfh)
    Single(0x14000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zfh];
    Single(0x14000053), RV32 | RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zhinx];
    // fmul.h rd, rs1, rs2 (zfh)
    Single(0x14007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0x14007053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],
"fmv.h" = [
    // fmv.h rd, rs1, rs2=rs1 (subformat of rv_zfh::fsgnj.h) (zfh)
    Single(0x24000053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_Zfh];
    Single(0x24000053), RV32 | RV64, [X, X] => [R(7), R(15), Repeat, R(20)], [Ex_Zhinx];
],
"fmv.h.x" = [
    // fmv.h.x rd, rs1 (zfh)
    Single(0xF4000053), RV32 | RV64, [F, X] => [R(7), R(15)], [Ex_Zfh, Ex_Zfhmin];
],
"fmv.x.h" = [
    // fmv.x.h rd, rs1 (zfh)
    Single(0xE4000053), RV32 | RV64, [X, F] => [R(7), R(15)], [Ex_Zfh, Ex_Zfhmin];
],
"fneg.h" = [
    // fneg.h rd, rs1, rs2=rs1 (subformat of rv_zfh::fsgnjn.h) (zfh)
    Single(0x24001053), RV32 | RV64, [F, F] => [R(7), R(15), Repeat, R(20)], [Ex_Zfh];
    Single(0x24001053), RV32 | RV64, [X, X] => [R(7), R(15), Repeat, R(20)], [Ex_Zhinx];
],
"fnmadd.h" = [
    // fnmadd.h rd, rs1, rs2, rs3, rm (zfh)
    Single(0x0400004F), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zfh];
    Single(0x0400004F), RV32 | RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zhinx];
    // fnmadd.h rd, rs1, rs2, rs3 (zfh)
    Single(0x0400704F), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_Zfh];
    Single(0x0400704F), RV32 | RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zhinx];
],
"fnmsub.h" = [
    // fnmsub.h rd, rs1, rs2, rs3, rm (zfh)
    Single(0x0400004B), RV32 | RV64, [F, F, F, F, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zfh];
    Single(0x0400004B), RV32 | RV64, [X, X, X, X, Ident] => [R(7), R(15), R(20), R(27), RoundingMode(12)], [Ex_Zhinx];
    // fnmsub.h rd, rs1, rs2, rs3 (zfh)
    Single(0x0400704B), RV32 | RV64, [F, F, F, F] => [R(7), R(15), R(20), R(27)], [Ex_Zfh];
    Single(0x0400704B), RV32 | RV64, [X, X, X, X] => [R(7), R(15), R(20), R(27)], [Ex_Zhinx];
],
"fsgnj.h" = [
    // fsgnj.h rd, rs1, rs2 (zfh)
    Single(0x24000053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0x24000053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],
"fsgnjn.h" = [
    // fsgnjn.h rd, rs1, rs2 (zfh)
    Single(0x24001053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0x24001053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],
"fsgnjx.h" = [
    // fsgnjx.h rd, rs1, rs2 (zfh)
    Single(0x24002053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0x24002053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],
"fsh" = [
    // fsh imm12hi, rs1, rs2, imm12lo (zfh)
    Single(0x00001027), RV32 | RV64, [F, RefOffset] => [R(20), R(15), SImm(12, 0), BitRange(7, 5, 0), BitRange(25, 7, 5), Next], [Ex_Zfh, Ex_Zfhmin];
    // as part of a pc-relative load
    Single(0x00001027), RV32 | RV64, [F, RefLabel] => [R(20), R(15), Offset(LO12S)], [Ex_Zfh, Ex_Zfhmin];
    // Pseudo instruction for auipc rd, hi20(symbol); fsh, rd, rd, lo12(symbol)
    Double(0x00000017, 0x00001027), RV32 | RV64, [F, Offset, X] => [R(20+32), Offset(SPLIT32S), Rno0(7), Repeat, R(15+32)], [Ex_Zfh, Ex_Zfhmin];
],
"fsqrt.h" = [
    // fsqrt.h rd, rs1, rm (zfh)
    Single(0x5C000053), RV32 | RV64, [F, F, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zfh];
    Single(0x5C000053), RV32 | RV64, [X, X, Ident] => [R(7), R(15), RoundingMode(12)], [Ex_Zhinx];
    // fsqrt.h rd, rs1 (zfh)
    Single(0x5C007053), RV32 | RV64, [F, F] => [R(7), R(15)], [Ex_Zfh];
    Single(0x5C007053), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zhinx];
],
"fsub.h" = [
    // fsub.h rd, rs1, rs2, rm (zfh)
    Single(0x0C000053), RV32 | RV64, [F, F, F, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zfh];
    Single(0x0C000053), RV32 | RV64, [X, X, X, Ident] => [R(7), R(15), R(20), RoundingMode(12)], [Ex_Zhinx];
    // fsub.h rd, rs1, rs2 (zfh)
    Single(0x0C007053), RV32 | RV64, [F, F, F] => [R(7), R(15), R(20)], [Ex_Zfh];
    Single(0x0C007053), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zhinx];
],

// Extension(s) zicbom

"cbo.clean" = [
    // cbo.clean rs1 (zicbo)
    Single(0x0010200F), RV32 | RV64, [Ref] => [R(15)], [Ex_Zicbom];
],
"cbo.flush" = [
    // cbo.flush rs1 (zicbo)
    Single(0x0020200F), RV32 | RV64, [Ref] => [R(15)], [Ex_Zicbom];
],
"cbo.inval" = [
    // cbo.inval rs1 (zicbo)
    Single(0x0000200F), RV32 | RV64, [Ref] => [R(15)], [Ex_Zicbom];
],

// Extension(s) zicbop

"prefetch.i" = [
    // prefetch.i rs1, imm12hi (subformat of rv_i::ori) (zicbo)
    Single(0x00006013), RV32 | RV64, [RefOffset] => [R(15), SImm(12, 5), BitRange(25, 7, 5), Next], [Ex_Zicbop];
],
"prefetch.r" = [
    // prefetch.r rs1, imm12hi (subformat of rv_i::ori) (zicbo)
    Single(0x00106013), RV32 | RV64, [RefOffset] => [R(15), SImm(12, 5), BitRange(25, 7, 5), Next], [Ex_Zicbop];
],
"prefetch.w" = [
    // prefetch.w rs1, imm12hi (subformat of rv_i::ori) (zicbo)
    Single(0x00306013), RV32 | RV64, [RefOffset] => [R(15), SImm(12, 5), BitRange(25, 7, 5), Next], [Ex_Zicbop];
],

// Extension(s) zicboz

"cbo.zero" = [
    // cbo.zero rs1 (zicbo)
    Single(0x0040200F), RV32 | RV64, [Ref] => [R(15)], [Ex_Zicboz];
],

// Extension(s) zicfilp

"lpad" = [
    // lpad imm20 (subformat of rv_i::auipc) (zicfilp)
    Single(0x00000017), RV32 | RV64, [Imm] => [UImm(20, 0), BitRange(12, 20, 0), Next], [Ex_Zicfilp];
],

// Extension(s) zicfiss

"ssamoswap.d" = [
    // ssamoswap.d rd, rs1, rs2, aq, rl (zicfiss)
    Single(0x4800302F), RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zicfiss];
],
"ssamoswap.d.aq" = [
    // ssamoswap.d.aq rd, rs1, rs2, aq, rl (zicfiss)
    Single(0x4C00302F), RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zicfiss];
],
"ssamoswap.d.aqrl" = [
    // ssamoswap.d.aqrl rd, rs1, rs2, aq, rl (zicfiss)
    Single(0x4E00302F), RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zicfiss];
],
"ssamoswap.d.rl" = [
    // ssamoswap.d.rl rd, rs1, rs2, aq, rl (zicfiss)
    Single(0x4A00302F), RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zicfiss];
],
"ssamoswap.w" = [
    // ssamoswap.w rd, rs1, rs2, aq, rl (zicfiss)
    Single(0x4800202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zicfiss];
],
"ssamoswap.w.aq" = [
    // ssamoswap.w.aq rd, rs1, rs2, aq, rl (zicfiss)
    Single(0x4C00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zicfiss];
],
"ssamoswap.w.aqrl" = [
    // ssamoswap.w.aqrl rd, rs1, rs2, aq, rl (zicfiss)
    Single(0x4E00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zicfiss];
],
"ssamoswap.w.rl" = [
    // ssamoswap.w.rl rd, rs1, rs2, aq, rl (zicfiss)
    Single(0x4A00202F), RV32 | RV64, [X, X, Ref] => [R(7), R(20), R(15)], [Ex_Zicfiss];
],
"sspopchk" = [
    // sspopchk.x1  (subformat of rv_zimop::mop.r.N) (zicfiss)
    Single(0xCDC0C073), RV32 | RV64, [Reg(RegId::X1)] => [], [Ex_Zicfiss];
    // sspopchk.x5  (subformat of rv_zimop::mop.r.N) (zicfiss)
    Single(0xCDC2C073), RV32 | RV64, [Reg(RegId::X5)] => [], [Ex_Zicfiss];
],

"sspush" = [
    // sspush.x1  (subformat of rv_zimop::mop.rr.N) (zicfiss)
    Single(0xCE104073), RV32 | RV64, [Reg(RegId::X1)] => [], [Ex_Zicfiss];
    // sspush.x5  (subformat of rv_zimop::mop.rr.N) (zicfiss)
    Single(0xCE504073), RV32 | RV64, [Reg(RegId::X5)] => [], [Ex_Zicfiss];
],
"ssrdp" = [
    // ssrdp rd_n0 (subformat of rv_zimop::mop.r.N) (zicfiss)
    Single(0xCDC04073), RV32 | RV64, [X] => [Rno0(7)], [Ex_Zicfiss];
],

// Extension(s) zicntr

"rdcycle" = [
    // rdcycle rd (subformat of rv_zicsr::csrrs) (zicntr)
    Single(0xC0002073), RV32 | RV64, [X] => [R(7)], [Ex_Zicntr];
],
"rdcycleh" = [
    // rdcycleh rd (subformat of rv_zicsr::csrrs) (zicntr)
    Single(0xC8002073), RV32       , [X] => [R(7)], [Ex_Zicntr];
],
"rdinstret" = [
    // rdinstret rd (subformat of rv_zicsr::csrrs) (zicntr)
    Single(0xC0202073), RV32 | RV64, [X] => [R(7)], [Ex_Zicntr];
],
"rdinstreth" = [
    // rdinstreth rd (subformat of rv_zicsr::csrrs) (zicntr)
    Single(0xC8202073), RV32       , [X] => [R(7)], [Ex_Zicntr];
],
"rdtime" = [
    // rdtime rd (subformat of rv_zicsr::csrrs) (zicntr)
    Single(0xC0102073), RV32 | RV64, [X] => [R(7)], [Ex_Zicntr];
],
"rdtimeh" = [
    // rdtimeh rd (subformat of rv_zicsr::csrrs) (zicntr)
    Single(0xC8102073), RV32       , [X] => [R(7)], [Ex_Zicntr];
],

// Extension(s) zicond

"czero.eqz" = [
    // czero.eqz rd, rs1, rs2 (zicond)
    Single(0x0E005033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zicond];
],
"czero.nez" = [
    // czero.nez rd, rs1, rs2 (zicond)
    Single(0x0E007033), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zicond];
],

// Extension(s) zicsr

"csrc" = [
    // csrc rs1, csr (subformat of rv_zicsr::csrrc) (zicsr)
    Single(0x00003073), RV32 | RV64, [Imm, X] => [Csr(20), R(15)], [Ex_Zicsr];
],
"csrci" = [
    // csrci csr, zimm (subformat of rv_zicsr::csrrci) (zicsr)
    Single(0x00007073), RV32 | RV64, [Imm, Imm] => [Csr(20), UImm(5, 0), BitRange(15, 5, 0), Next], [Ex_Zicsr];
],
"csrr" = [
    // csrr rd, csr (subformat of rv_zicsr::csrrs) (zicsr)
    Single(0x00002073), RV32 | RV64, [X, Imm] => [R(7), Csr(20)], [Ex_Zicsr];
],
"csrrc" = [
    // csrrc rd, rs1, csr (zicsr)
    Single(0x00003073), RV32 | RV64, [X, Imm, X] => [R(7), Csr(20), R(15)], [Ex_Zicsr];
],
"csrrci" = [
    // csrrci rd, csr, zimm (zicsr)
    Single(0x00007073), RV32 | RV64, [X, Imm, Imm] => [R(7), Csr(20), UImm(5, 0), BitRange(15, 5, 0), Next], [Ex_Zicsr];
],
"csrrs" = [
    // csrrs rd, rs1, csr (zicsr)
    Single(0x00002073), RV32 | RV64, [X, Imm, X] => [R(7), Csr(20), R(15)], [Ex_Zicsr];
],
"csrrsi" = [
    // csrrsi rd, csr, zimm (zicsr)
    Single(0x00006073), RV32 | RV64, [X, Imm, Imm] => [R(7), Csr(20), UImm(5, 0), BitRange(15, 5, 0), Next], [Ex_Zicsr];
],
"csrrw" = [
    // csrrw rd, rs1, csr (zicsr)
    Single(0x00001073), RV32 | RV64, [X, Imm, X] => [R(7), Csr(20), R(15)], [Ex_Zicsr];
],
"csrrwi" = [
    // csrrwi rd, csr, zimm (zicsr)
    Single(0x00005073), RV32 | RV64, [X, Imm, Imm] => [R(7), Csr(20), UImm(5, 0), BitRange(15, 5, 0), Next], [Ex_Zicsr];
],
"csrs" = [
    // csrs rs1, csr (subformat of rv_zicsr::csrrs) (zicsr)
    Single(0x00002073), RV32 | RV64, [Imm, X] => [Csr(20), R(15)], [Ex_Zicsr];
],
"csrsi" = [
    // csrsi csr, zimm (subformat of rv_zicsr::csrrsi) (zicsr)
    Single(0x00006073), RV32 | RV64, [Imm, Imm] => [Csr(20), UImm(5, 0), BitRange(15, 5, 0), Next], [Ex_Zicsr];
],
"csrw" = [
    // csrw rs1, csr (subformat of rv_zicsr::csrrw) (zicsr)
    Single(0x00001073), RV32 | RV64, [Imm, X] => [Csr(20), R(15)], [Ex_Zicsr];
],
"csrwi" = [
    // csrwi csr, zimm (subformat of rv_zicsr::csrrwi) (zicsr)
    Single(0x00005073), RV32 | RV64, [Imm, Imm] => [Csr(20), UImm(5, 0), BitRange(15, 5, 0), Next], [Ex_Zicsr];
],

// Extension(s) zifencei

"fence.i" = [
    // fence.i (zifencei)
    Single(0x0000100F), RV32 | RV64, [] => [], [Ex_Zifencei];
],

// Extension(s) zihintntl

"ntl.all" = [
    // ntl.all  (subformat of rv_i::add) (zihintntl)
    Single(0x00500033), RV32 | RV64, [] => [], [Ex_Zihintntl];
],
"ntl.p1" = [
    // ntl.p1  (subformat of rv_i::add) (zihintntl)
    Single(0x00200033), RV32 | RV64, [] => [], [Ex_Zihintntl];
],
"ntl.pall" = [
    // ntl.pall  (subformat of rv_i::add) (zihintntl)
    Single(0x00300033), RV32 | RV64, [] => [], [Ex_Zihintntl];
],
"ntl.s1" = [
    // ntl.s1  (subformat of rv_i::add) (zihintntl)
    Single(0x00400033), RV32 | RV64, [] => [], [Ex_Zihintntl];
],

// Extension(s) zimop

"mop.r.0" = [
    // mop.r.0 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x81C04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.1" = [
    // mop.r.1 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x81D04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.10" = [
    // mop.r.10 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x89E04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.11" = [
    // mop.r.11 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x89F04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.12" = [
    // mop.r.12 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x8DC04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.13" = [
    // mop.r.13 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x8DD04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.14" = [
    // mop.r.14 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x8DE04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.15" = [
    // mop.r.15 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x8DF04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.16" = [
    // mop.r.16 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC1C04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.17" = [
    // mop.r.17 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC1D04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.18" = [
    // mop.r.18 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC1E04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.19" = [
    // mop.r.19 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC1F04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.2" = [
    // mop.r.2 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x81E04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.20" = [
    // mop.r.20 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC5C04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.21" = [
    // mop.r.21 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC5D04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.22" = [
    // mop.r.22 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC5E04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.23" = [
    // mop.r.23 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC5F04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.24" = [
    // mop.r.24 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC9C04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.25" = [
    // mop.r.25 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC9D04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.26" = [
    // mop.r.26 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC9E04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.27" = [
    // mop.r.27 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xC9F04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.28" = [
    // mop.r.28 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xCDC04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.29" = [
    // mop.r.29 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xCDD04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.3" = [
    // mop.r.3 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x81F04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.30" = [
    // mop.r.30 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xCDE04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.31" = [
    // mop.r.31 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0xCDF04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.4" = [
    // mop.r.4 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x85C04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.5" = [
    // mop.r.5 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x85D04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.6" = [
    // mop.r.6 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x85E04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.7" = [
    // mop.r.7 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x85F04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.8" = [
    // mop.r.8 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x89C04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.9" = [
    // mop.r.9 rd, rs1 (subformat of rv_zimop::mop.r.N) (zimop)
    Single(0x89D04073), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zimop];
],
"mop.r.N" = [
    // mop.r.N mop_r_t_30, mop_r_t_27_26, mop_r_t_21_20, rd, rs1 (zimop)
    Single(0x81C04073), RV32 | RV64, [Imm, X, X] => [UImm(5, 0), BitRange(20, 2, 0), BitRange(26, 2, 2), BitRange(30, 1, 4), Next, R(7), R(15)], [Ex_Zimop];
],
"mop.rr.0" = [
    // mop.rr.0 rd, rs1, rs2 (subformat of rv_zimop::mop.rr.N) (zimop)
    Single(0x82004073), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zimop];
],
"mop.rr.1" = [
    // mop.rr.1 rd, rs1, rs2 (subformat of rv_zimop::mop.rr.N) (zimop)
    Single(0x86004073), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zimop];
],
"mop.rr.2" = [
    // mop.rr.2 rd, rs1, rs2 (subformat of rv_zimop::mop.rr.N) (zimop)
    Single(0x8A004073), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zimop];
],
"mop.rr.3" = [
    // mop.rr.3 rd, rs1, rs2 (subformat of rv_zimop::mop.rr.N) (zimop)
    Single(0x8E004073), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zimop];
],
"mop.rr.4" = [
    // mop.rr.4 rd, rs1, rs2 (subformat of rv_zimop::mop.rr.N) (zimop)
    Single(0xC2004073), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zimop];
],
"mop.rr.5" = [
    // mop.rr.5 rd, rs1, rs2 (subformat of rv_zimop::mop.rr.N) (zimop)
    Single(0xC6004073), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zimop];
],
"mop.rr.6" = [
    // mop.rr.6 rd, rs1, rs2 (subformat of rv_zimop::mop.rr.N) (zimop)
    Single(0xCA004073), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zimop];
],
"mop.rr.7" = [
    // mop.rr.7 rd, rs1, rs2 (subformat of rv_zimop::mop.rr.N) (zimop)
    Single(0xCE004073), RV32 | RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zimop];
],
"mop.rr.N" = [
    // mop.rr.N mop_rr_t_30, mop_rr_t_27_26, rd, rs1, rs2 (zimop)
    Single(0x82004073), RV32 | RV64, [Imm, X, X, X] => [UImm(3, 0), BitRange(26, 2, 0), BitRange(30, 1, 2), Next, R(7), R(15), R(20)], [Ex_Zimop];
],

// Extension(s) zk, zkn, zknd

"aes32dsi" = [
    // aes32dsi rd, rs1, rs2, bs (zk, zkn, zknd)
    Single(0x2A000033), RV32       , [X, X, X, Imm] => [R(7), R(15), R(20), UImm(2, 0), BitRange(30, 2, 0), Next], [Ex_Zk, Ex_Zkn, Ex_Zknd];
],
"aes32dsmi" = [
    // aes32dsmi rd, rs1, rs2, bs (zk, zkn, zknd)
    Single(0x2E000033), RV32       , [X, X, X, Imm] => [R(7), R(15), R(20), UImm(2, 0), BitRange(30, 2, 0), Next], [Ex_Zk, Ex_Zkn, Ex_Zknd];
],
"aes64ds" = [
    // aes64ds rd, rs1, rs2 (zk, zkn, zknd)
    Single(0x3A000033),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zk, Ex_Zkn, Ex_Zknd];
],
"aes64dsm" = [
    // aes64dsm rd, rs1, rs2 (zk, zkn, zknd)
    Single(0x3E000033),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zk, Ex_Zkn, Ex_Zknd];
],
"aes64im" = [
    // aes64im rd, rs1 (zk, zkn, zknd)
    Single(0x30001013),        RV64, [X, X] => [R(7), R(15)], [Ex_Zk, Ex_Zkn, Ex_Zknd];
],

// Extension(s) zk, zkn, zknd, zkne

"aes64ks1i" = [
    // aes64ks1i rd, rs1, rnum (zk, zkn, zknd, zkne)
    Single(0x31001013),        RV64, [X, X, Imm] => [R(7), R(15), UImmRange(0, 10), BitRange(20, 4, 0), Next], [Ex_Zk, Ex_Zkn, Ex_Zknd, Ex_Zkne];
],
"aes64ks2" = [
    // aes64ks2 rd, rs1, rs2 (zk, zkn, zknd, zkne)
    Single(0x7E000033),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zk, Ex_Zkn, Ex_Zknd, Ex_Zkne];
],

// Extension(s) zk, zkn, zkne

"aes32esi" = [
    // aes32esi rd, rs1, rs2, bs (zk, zkn, zkne)
    Single(0x22000033), RV32       , [X, X, X, Imm] => [R(7), R(15), R(20), UImm(2, 0), BitRange(30, 2, 0), Next], [Ex_Zk, Ex_Zkn, Ex_Zkne];
],
"aes32esmi" = [
    // aes32esmi rd, rs1, rs2, bs (zk, zkn, zkne)
    Single(0x26000033), RV32       , [X, X, X, Imm] => [R(7), R(15), R(20), UImm(2, 0), BitRange(30, 2, 0), Next], [Ex_Zk, Ex_Zkn, Ex_Zkne];
],
"aes64es" = [
    // aes64es rd, rs1, rs2 (zk, zkn, zkne)
    Single(0x32000033),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zk, Ex_Zkn, Ex_Zkne];
],
"aes64esm" = [
    // aes64esm rd, rs1, rs2 (zk, zkn, zkne)
    Single(0x36000033),        RV64, [X, X, X] => [R(7), R(15), R(20)], [Ex_Zk, Ex_Zkn, Ex_Zkne];
],

// Extension(s) zk, zkn, zknh

"sha256sig0" = [
    // sha256sig0 rd, rs1 (zk, zkn, zknh)
    Single(0x10201013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha256sig1" = [
    // sha256sig1 rd, rs1 (zk, zkn, zknh)
    Single(0x10301013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha256sum0" = [
    // sha256sum0 rd, rs1 (zk, zkn, zknh)
    Single(0x10001013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha256sum1" = [
    // sha256sum1 rd, rs1 (zk, zkn, zknh)
    Single(0x10101013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha512sig0" = [
    // sha512sig0 rd, rs1 (zk, zkn, zknh)
    Single(0x10601013),        RV64, [X, X] => [R(7), R(15)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha512sig0h" = [
    // sha512sig0h rd, rs1, rs2 (zk, zkn, zknh)
    Single(0x5C000033), RV32       , [X, X, X] => [R(7), R(15), R(20)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha512sig0l" = [
    // sha512sig0l rd, rs1, rs2 (zk, zkn, zknh)
    Single(0x54000033), RV32       , [X, X, X] => [R(7), R(15), R(20)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha512sig1" = [
    // sha512sig1 rd, rs1 (zk, zkn, zknh)
    Single(0x10701013),        RV64, [X, X] => [R(7), R(15)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha512sig1h" = [
    // sha512sig1h rd, rs1, rs2 (zk, zkn, zknh)
    Single(0x5E000033), RV32       , [X, X, X] => [R(7), R(15), R(20)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha512sig1l" = [
    // sha512sig1l rd, rs1, rs2 (zk, zkn, zknh)
    Single(0x56000033), RV32       , [X, X, X] => [R(7), R(15), R(20)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha512sum0" = [
    // sha512sum0 rd, rs1 (zk, zkn, zknh)
    Single(0x10401013),        RV64, [X, X] => [R(7), R(15)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha512sum0r" = [
    // sha512sum0r rd, rs1, rs2 (zk, zkn, zknh)
    Single(0x50000033), RV32       , [X, X, X] => [R(7), R(15), R(20)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha512sum1" = [
    // sha512sum1 rd, rs1 (zk, zkn, zknh)
    Single(0x10501013),        RV64, [X, X] => [R(7), R(15)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],
"sha512sum1r" = [
    // sha512sum1r rd, rs1, rs2 (zk, zkn, zknh)
    Single(0x52000033), RV32       , [X, X, X] => [R(7), R(15), R(20)], [Ex_Zk, Ex_Zkn, Ex_Zknh];
],

// Extension(s) zks, zksed

"sm4ed" = [
    // sm4ed rd, rs1, rs2, bs (zks, zksed)
    Single(0x30000033), RV32 | RV64, [X, X, X, Imm] => [R(7), R(15), R(20), UImm(2, 0), BitRange(30, 2, 0), Next], [Ex_Zks, Ex_Zksed];
],
"sm4ks" = [
    // sm4ks rd, rs1, rs2, bs (zks, zksed)
    Single(0x34000033), RV32 | RV64, [X, X, X, Imm] => [R(7), R(15), R(20), UImm(2, 0), BitRange(30, 2, 0), Next], [Ex_Zks, Ex_Zksed];
],

// Extension(s) zks, zksh

"sm3p0" = [
    // sm3p0 rd, rs1 (zks, zksh)
    Single(0x10801013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zks, Ex_Zksh];
],
"sm3p1" = [
    // sm3p1 rd, rs1 (zks, zksh)
    Single(0x10901013), RV32 | RV64, [X, X] => [R(7), R(15)], [Ex_Zks, Ex_Zksh];
],

)