Module dw1000::ll [−][src]
Expand description
Low-level interface to the DW1000
This module implements a register-level interface to the DW1000. Users of this library should typically not need to use this. Please consider using the high-level interface instead.
If you’re using the low-level interface because the high-level interface doesn’t cover your use case, please consider filing an issue.
NOTE: Many field access methods accept types that have a larger number of bits than the field actually consists of. If you use such a method to pass a value that is too large to be written to the field, it will be silently truncated.
Modules
AGC Tuning register 1
AGC Tuning register 2
AON Configuration Register 0
AON Configuration Register 1
AON Control Register
AON Wakeup Configuration Register
Channel Control Register
Device identifier
Preamble detection timeou
SFD timeout
Digital Tuning Register 0b
Digital Tuning Register 1a
Digital Tuning Register 1b
Digital Tuning Register 2
Digital Tuning Register 4h
Delayed Send or Receive Time
Carrier Recovery Integrator Register
External Clock Sync Counter Config
External clock offset to first path 1 GHz counter
External clock synchronisation counter captured on RMARKER
Extended Unique Identifier
Event Counter Control
Half Period Warning Counter
TX Power-Up Warning Counter
Frequency synth - PLL configuration
Frequency synth - PLL Tuning
GPIO Direction Control Register
GPIO Data Output register
GPIO Interrupt “Both Edge” Select
GPIO Interrupt Latch Clear
GPIO Interrupt De-bounce Enable
GPIO Interrupt Mode (Level / Edge)
GPIO Interrupt Enable
GPIO Interrupt Sense Selection
GPIO Mode Control Register
GPIO raw state
LDE Configuration Register 1
LDE Configuration Register 2
LDE Peak Path Amplitude
LDE Peak Path Index
LDE Replica Coefficient configuration
RX Antenna Delay
LDO voltage tuning parameter
OTP Address
OTP Control
OTP Read Data
PAN Identifier and Short Address
PMSC Control Register 0
PMSC Control Register 1
PMSC LED Control Register
Analog RX Control Register
RF Status Register
Analog TX Control Register
Receive Data Buffer
RX Frame Information
Rx Frame Quality Information
Receive Time Stamp
Receiver Time Tracking Interval
Receiver Time Tracking Offset
Digital debug register. Unsaturated accumulated preamble symbols.
This is the length of the SFD sequence used when the data rate is 850kbps and higher.
System Configuration
System Control Register
System Event Mask Register
System State information
System Event Status Register
System Time Counter
Pulse Generator Delay
TX Antenna Delay
Transmit Data Buffer
TX Frame Control
TX Power Control
Transmit Time Stamp
Structs
AGC Tuning register 1
AGC Tuning register 2
AON Configuration Register 0
AON Configuration Register 1
AON Control Register
AON Wakeup Configuration Register
Channel Control Register
Device identifier
Carrier Recovery Integrator Register
Preamble detection timeou
SFD timeout
Digital Tuning Register 0b
Digital Tuning Register 1a
Digital Tuning Register 1b
Digital Tuning Register 2
Digital Tuning Register 4h
Entry point to the DW1000 driver’s low-level API
Delayed Send or Receive Time
External Clock Sync Counter Config
External clock offset to first path 1 GHz counter
External clock synchronisation counter captured on RMARKER
Extended Unique Identifier
Event Counter Control
Half Period Warning Counter
TX Power-Up Warning Counter
Frequency synth - PLL configuration
Frequency synth - PLL Tuning
GPIO Direction Control Register
GPIO Data Output register
GPIO Interrupt “Both Edge” Select
GPIO Interrupt Latch Clear
GPIO Interrupt De-bounce Enable
GPIO Interrupt Mode (Level / Edge)
GPIO Interrupt Enable
GPIO Interrupt Sense Selection
GPIO Mode Control Register
GPIO raw state
LDE Configuration Register 1
LDE Configuration Register 2
LDE Peak Path Amplitude
LDE Peak Path Index
LDE Replica Coefficient configuration
RX Antenna Delay
LDO voltage tuning parameter
OTP Address
OTP Control
OTP Read Data
PAN Identifier and Short Address
PMSC Control Register 0
PMSC Control Register 1
PMSC LED Control Register
Analog RX Control Register
RF Status Register
Analog TX Control Register
Digital debug register. Unsaturated accumulated preamble symbols.
Receive Data Buffer
RX Frame Information
Rx Frame Quality Information
Receive Time Stamp
Receiver Time Tracking Interval
Receiver Time Tracking Offset
Provides access to a register
This is the length of the SFD sequence used when the data rate is 850kbps and higher.
System Configuration
System Control Register
System Event Mask Register
System State information
System Event Status Register
System Time Counter
Pulse Generator Delay
TX Antenna Delay
Transmit Data Buffer
TX Frame Control
TX Power Control
Transmit Time Stamp
Enums
An SPI error that can occur when communicating with the DW1000