1use crate::{DeviceDma, Direction, DmaError, common::DCommon};
2
3pub struct DBox<T> {
4 data: DCommon<T>,
5}
6
7impl<T> DBox<T> {
8 pub(crate) fn new_zero(
9 os: &DeviceDma,
10 align: usize,
11 direction: Direction,
12 ) -> Result<Self, DmaError> {
13 let mut data = DCommon::new(os, core::mem::size_of::<T>(), align, direction)?;
14 data.as_mut_slice().fill(0);
15 data.confirm_write_all();
16 Ok(Self { data })
17 }
18
19 pub fn dma_addr(&self) -> crate::DmaAddr {
20 self.data.handle.dma_addr
21 }
22
23 pub fn read(&self) -> T {
24 unsafe {
25 self.data.prepare_read(0, core::mem::size_of::<T>());
26 let ptr = self.data.get_ptr(0).cast::<T>();
27 ptr.read_volatile()
28 }
29 }
30
31 pub fn write(&mut self, value: T) {
32 unsafe {
33 let ptr = self.data.get_ptr(0).cast::<T>();
34 ptr.write_volatile(value);
35 self.data.confirm_write(0, core::mem::size_of::<T>());
36 }
37 }
38
39 pub fn modify(&mut self, f: impl FnOnce(&mut T)) {
40 let mut value = self.read();
41 f(&mut value);
42 self.write(value);
43 }
44
45 pub unsafe fn as_buff_slice_mut(&mut self) -> &mut [u8] {
51 self.data.as_mut_slice()
52 }
53}