use super::device::Device;
use super::ram::Ram;
#[derive(Default, Clone, Copy)]
pub struct Rom<const SIZE: usize> {
internal: Ram<SIZE>,
}
impl<const SIZE: usize> Rom<SIZE> {
pub fn new() -> Self {
Self::default()
}
pub fn as_slice(&self) -> &[u8] {
self.internal.as_slice()
}
}
impl<const SIZE: usize> Device for Rom<SIZE> {
fn with_data(data: &[u8]) -> Self {
Self {
internal: Ram::<SIZE>::with_data(data),
}
}
fn init_data(&mut self, data: &[u8]) {
self.internal.init_data(data);
}
fn cache_current_read_data(&self, destination: &mut [u8]) {
self.internal.cache_current_read_data(destination);
}
fn read(&self, addr: u16) -> u8 {
self.internal.read(addr)
}
fn write(&mut self, _data: u8, _addr: u16) {}
fn addr_space_size() -> u32 {
Ram::<SIZE>::size()
}
fn addr_bits_count() -> u8 {
Ram::<SIZE>::bits_count()
}
fn addr_space_size_dyn(&self) -> u32 {
Ram::<SIZE>::size()
}
fn addr_bits_count_dyn(&self) -> u8 {
Ram::<SIZE>::bits_count()
}
}
#[cfg(test)]
mod tests {
use super::*;
#[test]
fn createrom_write_writesignored() {
let mut rom = Rom::<16>::new();
for i in 0u16..16 {
rom.write(i as u8, i);
}
for i in 0u16..16 {
assert_eq!(rom.internal.read(i), 0);
}
}
}