decuda 0.1.1

CUDA to HIP, SYCL, OpenCL, and Rust GPU migration tool — automatic source-code translator for porting CUDA C++ kernels to AMD ROCm HIP, Intel oneAPI SYCL, Khronos OpenCL, and Rust GPU (cust / rust-gpu)
Documentation 
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// Generated by decuda.
// Host-side runtime calls are translated to the `cust` crate. Kernels
// are emitted as `TODO(decuda)` blocks: rust-gpu translation requires
// the kernel to be authored as a Rust fn. See `examples/` for a
// scaffolded SPIR-V kernel module you can flesh out.
//
// Add to your Cargo.toml:
//   [dependencies]
//   cust = "0.3"

// Advanced fixture: inline PTX assembly constructs.
//
// Exercises:
//   - asm("...") with output/input operands
//   - asm volatile("...") with no operands
//   - asm with memory clobber
//   - All PTX constructs are flagged as warnings (NVIDIA-specific, no
//     equivalent in HIP/SYCL/OpenCL/Rust — manual rewrite required)
//   - __global__ kernel, threadIdx.x, blockIdx.x, blockDim.x
//   - cuda_runtime.h header
// was: #include cuda_runtime.h  ->  cust::cuda_build_setup() /* TODO: import cust crate */

// TODO(decuda): rewrite as rust-gpu kernel fn
 void ptx_bswap(int* data, int n) {
    int i = block_idx * block_dim + thread_idx;
    if (i >= n) return;

    int x = data[i];

    // Byte-swap via PTX `prmt` instruction.
    int result;
    asm("prmt.b32 %0, %1, 0, 0x0123;" : "=r"(result) : "r"(x));
    data[i] = result;
}

// TODO(decuda): rewrite as rust-gpu kernel fn
 void ptx_membar(int* data, int n) {
    int i = block_idx * block_dim + thread_idx;
    if (i >= n) return;

    // Memory barrier via PTX.
    asm volatile("membar.gl;");
    data[i] += 1;
}

// TODO(decuda): rewrite as rust-gpu kernel fn
 void ptx_clock(unsigned long long* cycles) {
    // Read the GPU clock counter via PTX.
    unsigned long long c;
    asm volatile("mov.u64 %0, %%clock64;" : "=l"(c));
    if (block_idx * block_dim + thread_idx == 0) {
        *cycles = c;
    }
}

// TODO(decuda): rewrite as rust-gpu kernel fn
 void ptx_lanemask(unsigned int* mask) {
    // Get the active lane mask via PTX.
    unsigned int m;
    asm volatile("activemask.b32 %0;" : "=r"(m));
    if (block_idx * block_dim + thread_idx == 0) {
        *mask = m;
    }
}

int main(void) {
    const int N = 1024;
    int* d_data = nullptr;
    unsigned long long* d_cycles = nullptr;
    unsigned int* d_mask = nullptr;

    cudaMalloc((void**)&d_data, N * sizeof(int));
    cudaMalloc((void**)&d_cycles, sizeof(unsigned long long));
    cudaMalloc((void**)&d_mask, sizeof(unsigned int));

    dim3 grid(N / 256);
    dim3 block(256);

    { /* decuda cust launch */ let _kernel = modules.get_function("ptx_bswap"); unsafe { let _ = launch!( _kernel<<<grid as grid_size, block as block_size, 0 as usize, default>>>(d_data, N) ); } };
    { /* decuda cust launch */ let _kernel = modules.get_function("ptx_membar"); unsafe { let _ = launch!( _kernel<<<grid as grid_size, block as block_size, 0 as usize, default>>>(d_data, N) ); } };
    { /* decuda cust launch */ let _kernel = modules.get_function("ptx_clock"); unsafe { let _ = launch!( _kernel<<<1 as grid_size, 1 as block_size, 0 as usize, default>>>(d_cycles) ); } };
    { /* decuda cust launch */ let _kernel = modules.get_function("ptx_lanemask"); unsafe { let _ = launch!( _kernel<<<1 as grid_size, 1 as block_size, 0 as usize, default>>>(d_mask) ); } };

    cudaDeviceSynchronize();
    cudaFree(d_data);
    cudaFree(d_cycles);
    cudaFree(d_mask);
    return 0;
}